Kernel updates since December 2009

include/l4/platform/pba9/irq.h

@@ -0,0 +1,34 @@
+/*
+ * Support for generic irq handling using platform irq controller (GIC)
+ *
+ * Copyright (C) 2007 B Labs Ltd.
+ */
+#ifndef __PLATFORM_IRQ_H__
+#define __PLATFORM_IRQ_H__
+
+
+/* TODO: Not sure about this, need to check */
+#define IRQ_CHIPS_MAX		1
+#define IRQS_MAX		96
+#define IRQ_OFFSET		0
+
+/* IRQ indices. */
+#define IRQ_TIMER0		34
+#define IRQ_TIMER1		35
+#define IRQ_RTC			36
+#define IRQ_UART0		37
+#define IRQ_UART1		38
+#define IRQ_UART2		39
+#define IRQ_UART3		40
+#define IRQ_CLCD0		46
+
+/*
+ * Interrupt Distribution:
+ * 0-31: SI, provided by distributed interrupt controller
+ * 32-63: Externel peripheral interrupts
+ * 64-71: Tile site interrupt
+ * 72-95: Externel peripheral interrupts
+ */
+
+#endif /* __PLATFORM_IRQ_H__ */
+

include/l4/platform/pba9/offsets.h

@@ -0,0 +1,35 @@
+/*
+ * Describes physical memory layout of pb926 platform.
+ *
+ * This only include physical and memory offsets that
+ * are not included in realview/offsets.h
+ *
+ * Copyright (C) 2010 B Labs Ltd.
+ * Author: Bahadir Balban <bbalban@b-labs.co.uk>
+ */
+
+#ifndef __PLATFORM_PBA9_OFFSETS_H__
+#define __PLATFORM_PBA9_OFFSETS_H__
+
+#include <l4/platform/realview/offsets.h>
+
+/*
+ * Device offsets in physical memory
+ * Naming of devices done starting with 0 subscript,
+ * as we use these names for device capability
+ */
+#define PLATFORM_TIMER2_BASE		0x10018000 /* Timers 2 and 3 */
+#define PLATFORM_TIMER3_BASE		0x10019000 /* Timers 2 and 3 */
+#define PLATFORM_SYSCTRL1_BASE		0x1001A000 /* System controller1 */
+
+#define PLATFORM_GIC0_BASE              0x1E000000 /* GIC 0 */
+
+#define MPCORE_PRIVATE_BASE		0x1E000000
+#define MPCORE_PRIVATE_VBASE	(IO_AREA0_VADDR + (13 * DEVICE_PAGE))
+
+#define SCU_BASE		MPCORE_PRIVATE_BASE
+#define SCU_VBASE		MPCORE_PRIVATE_VBASE
+#define GIC0_CPU_VBASE		(MPCORE_PRIVATE_VBASE + 0x100)
+#define GIC0_DIST_VBASE		(MPCORE_PRIVATE_VBASE + 0x1000)
+
+#endif /* __PLATFORM_PBA9_OFFSETS_H__ */

include/l4/platform/pba9/platform.h

@@ -0,0 +1,12 @@
+#ifndef __PBA9_PLATFORM_H__
+#define __PBA9_PLATFORM_H__
+/*
+ * Platform specific ties between drivers and generic APIs used by the kernel.
+ * E.g. system timer and console.
+ *
+ * Copyright (C) Bahadir Balban 2007
+ */
+
+#include <l4/platform/realview/platform.h>
+
+#endif /* __PBA9_PLATFORM_H__ */

include/l4/platform/pba9/platsmp.h

@@ -0,0 +1,21 @@
+/*
+ * Copyright 2010 B Labs Ltd.
+ * Author: Prem Mallappa <prem.mallappa@b-labs.co.uk>
+ */
+
+#ifndef __VXA9_PLATSMP_H__
+#define __VXA9_PLATSMP_H__
+
+#include <l4/generic/irq.h>
+#include <l4/generic/space.h>
+#include <l4/drivers/irq/gic/gic.h>
+#include <l4/generic/smp.h>
+#include INC_GLUE(smp.h)
+#include INC_PLAT(sysctrl.h)
+
+void boot_secondary(int);
+void platform_smp_init(int ncpus);
+int platform_smp_start(int cpu, void (*start)(int));
+void secondary_init_platform(void);
+
+#endif /* VXA9_PLATSMP_H */

include/l4/platform/pba9/sysctrl.h

@@ -0,0 +1,95 @@
+#ifndef __EB_SYSCTRL_H__
+#define __EB_SYSCTRL_H__
+/* TODO: Better to stick this file in a ARM specific folder as most realview boards
+ * tend to have this component
+ */
+#define SYS_ID			0x0000
+#define SYS_SW			0x0004
+#define SYS_LED			0x0008
+
+#define SYS_OSC0		0x000C
+#define SYS_OSC1		0x0010
+#define SYS_OSC2		0x0014
+#define SYS_OSC3		0x0018
+#define SYS_OSC4		0x001C
+
+#define SYS_LOCK		0x0020
+#define SYS_100HZ		0x0024
+
+#define SYS_CFGDATA0		0x0028
+#define SYS_CFGDATA1		0x002C
+
+#define SYS_FLAGS		0x0030
+#define SYS_FLAGS_SET		0x0030
+#define SYS_FLAGS_CLR		0x0034
+#define SYS_NVFLAGS		0x0038
+#define SYS_NVFLAGS_SET		0x0038
+#define SYS_NVFLAGS_CLR		0x003C
+
+#define SYS_PCICTL		0x0044
+#define SYS_MCI			0x0048
+#define SYS_FLASH		0x004C
+#define SYS_CLCD		0x0050
+#define SYS_CLCDSER		0x0054
+#define SYS_BOOTCS		0x0058
+
+#define SYS_24MHZ		0x005C
+#define SYS_MISC		0x0060
+#define SYS_DMAPSR0		0x0064
+#define SYS_DMAPSR1		0x0068
+#define SYS_DMAPSR2		0x006C
+#define SYS_IOSEL		0x0070
+#define SYS_PLDCTL1		0x0074
+#define SYS_PLDCTL2		0x0078
+
+#define SYS_BUSID		0x0080
+#define SYS_PROCID1		0x0084
+#define SYS_PROCID0		0x0088
+
+#define SYS_OSCRESET0		0x008C
+#define SYS_OSCRESET1		0x0090
+#define SYS_OSCRESET2		0x0094
+#define SYS_OSCRESET3		0x0098
+#define SYS_OSCRESET4		0x009C
+
+
+/* System Controller Lock/Unlock */
+#define SYSCTRL_LOCK		0xFF
+#define SYSCTRL_UNLOCK		0xA05F
+
+
+#define ID_MASK_REV		0xF0000000
+#define ID_MASK_HBI		0x0FFF0000
+#define ID_MASK_BUILD		0x0000F000
+#define ID_MASK_ARCH		0x00000F00
+#define ID_MASK_FPGA		0x000000FF
+
+
+#define SW_MASK_BOOTSEL		0x0000FF00
+#define SW_MASK_GP		0x000000FF
+
+#define LED_MASK_LED		0x000000FF
+
+#define FLASH_WRITE_EN		0x1
+#define FLASH_WRITE_DIS		0x0
+
+#define CLCD_QVGA		(0 << 8) /* 320x240 */
+#define CLDE_VGA		(1 << 8) /* 640x480 */
+#define CLCD_SMALL		(2 << 8) /* 220x176 */
+#define CLCD_SSP_CS		(1 << 7) /* SSP Chip Select */
+#define CLCD_TS_EN		(1 << 6) /* Touch Screen Enable */
+/* Different Voltages */
+#define CLCD_NEG_EN		(1 << 5)
+#define CLCD_3V5V_EN		(1 << 4)
+#define CLCD_POS_EN		(1 << 3)
+#define CLCD_IO_ON		(1 << 2)
+
+
+/* Normal without DCC, no FIQ, recommended for SMP */
+#define PLD_CTRL1_INTMOD_WITHOUT_DCC	(1 << 22)
+/* Not Recommended */
+#define PLD_CTRL1_INTMOD_WITH_DCC	(2 << 22)
+/* For single cpu such as 1136 */
+#define PLD_CTRL1_INTMOD_LEGACY		(4 << 22)
+
+#endif	/* __EB_SYSCTRL_H__ */

include/l4/platform/pba9/uart.h

@@ -0,0 +1,6 @@
+#ifndef __PBA9_UART_H__
+#define __PBA9_UART_H__
+
+#include <l4/platform/realview/uart.h>
+
+#endif /* __PBA9_UART_H__ */