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Cleaning loader libc and uart

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This commit is contained in:
Amit Mahajan
2009-10-29 12:48:16 +05:30
parent b8829118e0
commit a81574b899
108 changed files with 261 additions and 11596 deletions
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87
loader/libs/c/include/arch/arm/arch/inttypes.h
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@@ -1,87 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Author: Ben Leslie
*/
#define __LENGTH_8_MOD "hh"
#define __LENGTH_16_MOD "h"
#define __LENGTH_32_MOD
#define __LENGTH_64_MOD "ll"
#define __LENGTH_MAX_MOD "ll"
#define __LENGTH_PTR_MOD

408
loader/libs/c/include/arch/arm/arch/pl011_uart.h
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@@ -1,408 +0,0 @@
#ifndef __PL011__UART__H__
#define __PL011__UART__H__
/*
* PL011 UART Generic driver implementation.
* Copyright Bahadir Balban (C) 2006
*
* The particular intention of this code is that it has been carefully
* written as decoupled from os-specific code and in a verbose way such
* that it clearly demonstrates how the device operates, reducing the
* amount of time to be spent for understanding the operational model
* and implementing a driver from scratch. This is the very first to be
* such a driver so far, hopefully it will turn out to be useful.
*/
/* Default base address for this chip */
#define PL011_DEFAULT_PHYSICAL_BASE 0x101F1000
#define PL011_BASE PL011_DEFAULT_PHYSICAL_BASE
/* Architecture specific memory access macros */
#define read(val, address) val = *((volatile unsigned int *) address)
#define write(val, address) *((volatile unsigned int *) address) = val
/* Register offsets */
#define PL011_UARTDR (PL011_BASE + 0x00)
#define PL011_UARTRSR (PL011_BASE + 0x04)
#define PL011_UARTECR (PL011_BASE + 0x04)
#define PL011_UARTFR (PL011_BASE + 0x18)
#define PL011_UARTILPR (PL011_BASE + 0x20)
#define PL011_UARTIBRD (PL011_BASE + 0x24)
#define PL011_UARTFBRD (PL011_BASE + 0x28)
#define PL011_UARTLCR_H (PL011_BASE + 0x2C)
#define PL011_UARTCR (PL011_BASE + 0x30)
#define PL011_UARTIFLS (PL011_BASE + 0x34)
#define PL011_UARTIMSC (PL011_BASE + 0x38)
#define PL011_UARTRIS (PL011_BASE + 0x3C)
#define PL011_UARTMIS (PL011_BASE + 0x40)
#define PL011_UARTICR (PL011_BASE + 0x44)
#define PL011_UARTDMACR (PL011_BASE + 0x48)
/* IRQ bits for each uart irq event */
#define PL011_RXIRQ (1 << 4)
#define PL011_TXIRQ (1 << 5)
#define PL011_RXTIMEOUTIRQ (1 << 6)
#define PL011_FEIRQ (1 << 7)
#define PL011_PEIRQ (1 << 8)
#define PL011_BEIRQ (1 << 9)
#define PL011_OEIRQ (1 << 10)
struct pl011_uart;
int pl011_initialise(struct pl011_uart *);
int pl011_tx_char(char);
int pl011_rx_char(char *);
void pl011_set_baudrate(unsigned int, unsigned int);
void pl011_set_irq_mask(unsigned int);
void pl011_clr_irq_mask(unsigned int);
void pl011_irq_handler(struct pl011_uart *);
void pl011_tx_irq_handler(struct pl011_uart *, unsigned int);
void pl011_rx_irq_handler(struct pl011_uart *, unsigned int);
void pl011_error_irq_handler(struct pl011_uart *, unsigned int);
static inline void pl011_uart_enable(void);
static inline void pl011_uart_disable(void);
static inline void pl011_tx_enable(void);
static inline void pl011_tx_disable(void);
static inline void pl011_rx_enable(void);
static inline void pl011_rx_disable(void);
static inline void pl011_irq_clear(unsigned int flags);
static inline unsigned int pl011_read_irqstat(void);
static inline unsigned int pl011_read_irqmask(void);
static inline void pl011_rx_dma_disable(void);
static inline void pl011_rx_dma_enable(void);
static inline void pl011_tx_dma_enable(void);
static inline void pl011_tx_dma_disable(void);
static inline void pl011_set_irq_fifolevel(unsigned int xfer,
unsigned int level);
static inline void pl011_set_word_width(int size);
static inline void pl011_disable_fifos(void);
static inline void pl011_set_parity_even(void);
static inline void pl011_parity_enable(void);
static inline void pl011_set_stopbits(int stopbits);
static inline void pl011_set_parity_odd(void);
static inline void pl011_enable_fifos(void);
static inline void pl011_parity_disable(void);
struct pl011_uart_ops {
int (*initialise)(struct pl011_uart *);
int (*tx_char)(char);
int (*rx_char)(char *);
void (*set_baudrate)(unsigned int, unsigned int);
void (*set_irq_mask)(unsigned int);
void (*clr_irq_mask)(unsigned int);
void (*irq_handler)(struct pl011_uart *);
void (*tx_irq_handler)(struct pl011_uart *, unsigned int);
void (*rx_irq_handler)(struct pl011_uart *, unsigned int);
void (*error_irq_handler)(struct pl011_uart *, unsigned int);
};
struct pl011_uart {
const unsigned int base;
struct pl011_uart_ops ops;
unsigned int frame_errors;
unsigned int parity_errors;
unsigned int break_errors;
unsigned int overrun_errors;
unsigned int rx_timeout_errors;
};
#define PL011_UARTEN (1 << 0)
static inline void pl011_uart_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val |= PL011_UARTEN;
write(val, PL011_UARTCR);
return;
}
static inline void pl011_uart_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val &= ~PL011_UARTEN;
write(val, PL011_UARTCR);
return;
}
#define PL011_TXE (1 << 8)
static inline void pl011_tx_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val |= PL011_TXE;
write(val, PL011_UARTCR);
return;
}
static inline void pl011_tx_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val &= ~PL011_TXE;
write(val, PL011_UARTCR);
return;
}
#define PL011_RXE (1 << 9)
static inline void pl011_rx_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val |= PL011_RXE;
write(val, PL011_UARTCR);
return;
}
static inline void pl011_rx_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val &= ~PL011_RXE;
write(val, PL011_UARTCR);
return;
}
#define PL011_TWO_STOPBITS_SELECT (1 << 3)
static inline void pl011_set_stopbits(int stopbits)
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
if(stopbits == 2) { /* Set to two bits */
val |= PL011_TWO_STOPBITS_SELECT;
} else { /* Default is 1 */
val &= ~PL011_TWO_STOPBITS_SELECT;
}
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_PARITY_ENABLE (1 << 1)
static inline void pl011_parity_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val |= PL011_PARITY_ENABLE;
write(val, PL011_UARTLCR_H);
return;
}
static inline void pl011_parity_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val &= ~PL011_PARITY_ENABLE;
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_PARITY_EVEN (1 << 2)
static inline void pl011_set_parity_even()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val |= PL011_PARITY_EVEN;
write(val, PL011_UARTLCR_H);
return;
}
static inline void pl011_set_parity_odd()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val &= ~PL011_PARITY_EVEN;
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_ENABLE_FIFOS (1 << 4)
static inline void pl011_enable_fifos()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val |= PL011_ENABLE_FIFOS;
write(val, PL011_UARTLCR_H);
return;
}
static inline void pl011_disable_fifos()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val &= ~PL011_ENABLE_FIFOS;
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_WORD_WIDTH_SHIFT (5)
/* Sets the transfer word width for the data register. */
static inline void pl011_set_word_width(int size)
{
unsigned int val;
val = 0;
if(size < 5 || size > 8) /* Default is 8 */
size = 8;
/* Clear size field */
read(val, PL011_UARTLCR_H);
val &= ~(0x3 << PL011_WORD_WIDTH_SHIFT);
write(val, PL011_UARTLCR_H);
/* The formula is to write 5 less of size given:
* 11 = 8 bits
* 10 = 7 bits
* 01 = 6 bits
* 00 = 5 bits
*/
read(val, PL011_UARTLCR_H);
val |= (size - 5) << PL011_WORD_WIDTH_SHIFT;
write(val, PL011_UARTLCR_H);
return;
}
/*
* Defines at which level of fifo fullness an irq will be generated.
* @xfer: tx fifo = 0, rx fifo = 1
* @level: Generate irq if:
* 0 rxfifo >= 1/8 full txfifo <= 1/8 full
* 1 rxfifo >= 1/4 full txfifo <= 1/4 full
* 2 rxfifo >= 1/2 full txfifo <= 1/2 full
* 3 rxfifo >= 3/4 full txfifo <= 3/4 full
* 4 rxfifo >= 7/8 full txfifo <= 7/8 full
* 5-7 reserved reserved
*/
static inline void pl011_set_irq_fifolevel(unsigned int xfer, unsigned int level)
{
if(xfer != 1 && xfer != 0) /* Invalid fifo */
return;
if(level > 4) /* Invalid level */
return;
write(level << (xfer * 3), PL011_UARTIFLS);
return;
}
/* returns which irqs are masked */
static inline unsigned int pl011_read_irqmask(void)
{
unsigned int flags;
read(flags, PL011_UARTIMSC);
return flags;
}
/* returns masked irq status */
static inline unsigned int pl011_read_irqstat(void)
{
unsigned int irqstatus;
read(irqstatus, PL011_UARTMIS);
return irqstatus;
}
/* Clears the given asserted irqs */
static inline void pl011_irq_clear(unsigned int flags)
{
if(flags > 0x3FF) { /* Invalid irq clearing bitvector */
return;
}
/* Simply write the flags since it's a write-only register */
write(flags, PL011_UARTICR);
return;
}
#define PL011_TXDMAEN (1 << 1)
#define PL011_RXDMAEN (1 << 0)
/* Enables dma transfers for uart. The dma controller
* must be initialised, set-up and enabled separately.
*/
static inline void pl011_tx_dma_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val |= PL011_TXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
/* Disables dma transfers for uart */
static inline void pl011_tx_dma_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val &= ~PL011_TXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
static inline void pl011_rx_dma_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val |= PL011_RXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
static inline void pl011_rx_dma_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val &= ~PL011_RXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
#endif /* __PL011__UART__ */

83
loader/libs/c/include/arch/arm/arch/setjmp.h
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@@ -1,83 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Author: Alex Webster
*/
typedef int jmp_buf[10];

92
loader/libs/c/include/arch/arm/arch/stdint.h
View File

@@ -1,92 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Author: Ben Leslie
*/
typedef signed char int8_t;
typedef short int16_t;
typedef int int32_t;
typedef long long int64_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef unsigned long long uint64_t;
#define __PTR_SIZE 32

403
loader/libs/c/include/arch/pl011_uart.h
View File

@@ -2,42 +2,42 @@
#ifndef __PL011__UART__H__
#define __PL011__UART__H__
/*
/*
* PL011 UART Generic driver implementation.
* Copyright Bahadir Balban (C) 2006
*
* The particular intention of this code is that it has been carefully
* The particular intention of this code is that it has been carefully
* written as decoupled from os-specific code and in a verbose way such
* that it clearly demonstrates how the device operates, reducing the
* amount of time to be spent for understanding the operational model
* that it clearly demonstrates how the device operates, reducing the
* amount of time to be spent for understanding the operational model
* and implementing a driver from scratch. This is the very first to be
* such a driver so far, hopefully it will turn out to be useful.
*/
/* Default base address for this chip */
/* FIXME: Select based on arch */
#define PL011_DEFAULT_PHYSICAL_BASE 0x101F1000
#define PL011_BASE PL011_DEFAULT_PHYSICAL_BASE
#define PL011_BASE PL011_DEFAULT_PHYSICAL_BASE
/* Architecture specific memory access macros */
#define read(val, address) val = *((volatile unsigned int *) address)
#define write(val, address) *((volatile unsigned int *) address) = val
/* Register offsets */
#define PL011_UARTDR (PL011_BASE + 0x00)
#define PL011_UARTRSR (PL011_BASE + 0x04)
#define PL011_UARTECR (PL011_BASE + 0x04)
#define PL011_UARTFR (PL011_BASE + 0x18)
#define PL011_UARTILPR (PL011_BASE + 0x20)
#define PL011_UARTIBRD (PL011_BASE + 0x24)
#define PL011_UARTFBRD (PL011_BASE + 0x28)
#define PL011_UARTLCR_H (PL011_BASE + 0x2C)
#define PL011_UARTCR (PL011_BASE + 0x30)
#define PL011_UARTIFLS (PL011_BASE + 0x34)
#define PL011_UARTIMSC (PL011_BASE + 0x38)
#define PL011_UARTRIS (PL011_BASE + 0x3C)
#define PL011_UARTMIS (PL011_BASE + 0x40)
#define PL011_UARTICR (PL011_BASE + 0x44)
#define PL011_UARTDMACR (PL011_BASE + 0x48)
#define PL011_UARTDR 0x00
#define PL011_UARTRSR 0x04
#define PL011_UARTECR 0x04
#define PL011_UARTFR 0x18
#define PL011_UARTILPR 0x20
#define PL011_UARTIBRD 0x24
#define PL011_UARTFBRD 0x28
#define PL011_UARTLCR_H 0x2C
#define PL011_UARTCR 0x30
#define PL011_UARTIFLS 0x34
#define PL011_UARTIMSC 0x38
#define PL011_UARTRIS 0x3C
#define PL011_UARTMIS 0x40
#define PL011_UARTICR 0x44
#define PL011_UARTDMACR 0x48
/* IRQ bits for each uart irq event */
#define PL011_RXIRQ (1 << 4)
@@ -48,262 +48,228 @@
#define PL011_BEIRQ (1 << 9)
#define PL011_OEIRQ (1 << 10)
/* FIXME: Need to define this somewhere else */
struct pl011_uart;
int pl011_initialise(struct pl011_uart *);
int pl011_tx_char(char);
int pl011_rx_char(char *);
int pl011_initialise(struct pl011_uart *uart);
int pl011_tx_char(unsigned int base, char c);
int pl011_rx_char(unsigned int base, char *c);
void pl011_set_baudrate(unsigned int base, unsigned int baud,
unsigned int clkrate);
void pl011_set_irq_mask(unsigned int base, unsigned int flags);
void pl011_clr_irq_mask(unsigned int base, unsigned int flags);
void pl011_set_baudrate(unsigned int, unsigned int);
void pl011_set_irq_mask(unsigned int);
void pl011_clr_irq_mask(unsigned int);
void pl011_irq_handler(struct pl011_uart *);
void pl011_tx_irq_handler(struct pl011_uart *, unsigned int);
void pl011_rx_irq_handler(struct pl011_uart *, unsigned int);
void pl011_error_irq_handler(struct pl011_uart *, unsigned int);
void pl011_tx_irq_handler(struct pl011_uart *uart, unsigned int);
void pl011_rx_irq_handler(struct pl011_uart *uart, unsigned int);
void pl011_error_irq_handler(struct pl011_uart *uart, unsigned int);
static inline void pl011_uart_enable(void);
static inline void pl011_uart_disable(void);
static inline void pl011_tx_enable(void);
static inline void pl011_tx_disable(void);
static inline void pl011_rx_enable(void);
static inline void pl011_rx_disable(void);
static inline void pl011_irq_clear(unsigned int flags);
static inline unsigned int pl011_read_irqstat(void);
static inline unsigned int pl011_read_irqmask(void);
static inline void pl011_rx_dma_disable(void);
static inline void pl011_rx_dma_enable(void);
static inline void pl011_tx_dma_enable(void);
static inline void pl011_tx_dma_disable(void);
static inline void pl011_set_irq_fifolevel(unsigned int xfer,
unsigned int level);
static inline void pl011_set_word_width(int size);
static inline void pl011_disable_fifos(void);
static inline void pl011_set_parity_even(void);
static inline void pl011_parity_enable(void);
static inline void pl011_set_stopbits(int stopbits);
static inline void pl011_uart_enable(unsigned int base);
static inline void pl011_uart_disable(unsigned int base);
static inline void pl011_tx_enable(unsigned int base);
static inline void pl011_tx_disable(unsigned int base);
static inline void pl011_rx_enable(unsigned int base);
static inline void pl011_rx_disable(unsigned int base);
static inline void pl011_irq_clear(unsigned int base, unsigned int flags);
static inline unsigned int pl011_read_irqstat(unsigned int base);
static inline unsigned int pl011_read_irqmask(unsigned int base);
static inline void pl011_rx_dma_disable(unsigned int base);
static inline void pl011_rx_dma_enable(unsigned int base);
static inline void pl011_tx_dma_enable(unsigned int base);
static inline void pl011_tx_dma_disable(unsigned int base);
static inline void pl011_set_irq_fifolevel(unsigned int base,
unsigned int xfer, unsigned int level);
static inline void pl011_set_word_width(unsigned int base, int size);
static inline void pl011_disable_fifos(unsigned int base);
static inline void pl011_set_parity_even(unsigned int base);
static inline void pl011_parity_enable(unsigned int base);
static inline void pl011_set_stopbits(unsigned int base, int stopbits);
static inline void pl011_set_parity_odd(void);
static inline void pl011_enable_fifos(void);
static inline void pl011_parity_disable(void);
struct pl011_uart_ops {
int (*initialise)(struct pl011_uart *);
int (*tx_char)(char);
int (*rx_char)(char *);
void (*set_baudrate)(unsigned int, unsigned int);
void (*set_irq_mask)(unsigned int);
void (*clr_irq_mask)(unsigned int);
void (*irq_handler)(struct pl011_uart *);
void (*tx_irq_handler)(struct pl011_uart *, unsigned int);
void (*rx_irq_handler)(struct pl011_uart *, unsigned int);
void (*error_irq_handler)(struct pl011_uart *, unsigned int);
};
static inline void pl011_set_parity_odd(unsigned int base);
static inline void pl011_enable_fifos(unsigned int base);
static inline void pl011_parity_disable(unsigned int base);
struct pl011_uart {
const unsigned int base;
struct pl011_uart_ops ops;
unsigned int base;
unsigned int frame_errors;
unsigned int parity_errors;
unsigned int break_errors;
unsigned int overrun_errors;
unsigned int rx_timeout_errors;
};
};
#define PL011_UARTEN (1 << 0)
static inline void pl011_uart_enable()
static inline void pl011_uart_enable(unsigned int base)
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
unsigned int val = 0;
read(val, (base + PL011_UARTCR));
val |= PL011_UARTEN;
write(val, PL011_UARTCR);
return;
write(val, (base + PL011_UARTCR));
return;
}
static inline void pl011_uart_disable()
static inline void pl011_uart_disable(unsigned int base)
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
unsigned int val = 0;
read(val, (base + PL011_UARTCR));
val &= ~PL011_UARTEN;
write(val, PL011_UARTCR);
write(val, (base + PL011_UARTCR));
return;
}
#define PL011_TXE (1 << 8)
static inline void pl011_tx_enable()
static inline void pl011_tx_enable(unsigned int base)
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
unsigned int val = 0;
read(val, (base + PL011_UARTCR));
val |= PL011_TXE;
write(val, PL011_UARTCR);
write(val, (base + PL011_UARTCR));
return;
}
static inline void pl011_tx_disable()
static inline void pl011_tx_disable(unsigned int base)
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
unsigned int val = 0;
read(val, (base + PL011_UARTCR));
val &= ~PL011_TXE;
write(val, PL011_UARTCR);
write(val, (base + PL011_UARTCR));
return;
}
#define PL011_RXE (1 << 9)
static inline void pl011_rx_enable()
static inline void pl011_rx_enable(unsigned int base)
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
unsigned int val = 0;
read(val, (base + PL011_UARTCR));
val |= PL011_RXE;
write(val, PL011_UARTCR);
write(val, (base + PL011_UARTCR));
return;
}
static inline void pl011_rx_disable()
static inline void pl011_rx_disable(unsigned int base)
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
unsigned int val = 0;
read(val, (base + PL011_UARTCR));
val &= ~PL011_RXE;
write(val, PL011_UARTCR);
write(val, (base + PL011_UARTCR));
return;
}
#define PL011_TWO_STOPBITS_SELECT (1 << 3)
static inline void pl011_set_stopbits(int stopbits)
static inline void pl011_set_stopbits(unsigned int base, int stopbits)
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
unsigned int val = 0;
read(val, (base + PL011_UARTLCR_H));
if(stopbits == 2) { /* Set to two bits */
val |= PL011_TWO_STOPBITS_SELECT;
} else { /* Default is 1 */
val &= ~PL011_TWO_STOPBITS_SELECT;
}
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_PARITY_ENABLE (1 << 1)
static inline void pl011_parity_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val |= PL011_PARITY_ENABLE;
write(val, PL011_UARTLCR_H);
write(val, (base + PL011_UARTLCR_H));
return;
}
static inline void pl011_parity_disable()
#define PL011_PARITY_ENABLE (1 << 1)
static inline void pl011_parity_enable(unsigned int base)
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
unsigned int val = 0;
read(val, (base +PL011_UARTLCR_H));
val |= PL011_PARITY_ENABLE;
write(val, (base + PL011_UARTLCR_H));
return;
}
static inline void pl011_parity_disable(unsigned int base)
{
unsigned int val = 0;
read(val, (base + PL011_UARTLCR_H));
val &= ~PL011_PARITY_ENABLE;
write(val, PL011_UARTLCR_H);
write(val, (base + PL011_UARTLCR_H));
return;
}
#define PL011_PARITY_EVEN (1 << 2)
static inline void pl011_set_parity_even()
static inline void pl011_set_parity_even(unsigned int base)
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
unsigned int val = 0;
read(val, (base + PL011_UARTLCR_H));
val |= PL011_PARITY_EVEN;
write(val, PL011_UARTLCR_H);
write(val, (base + PL011_UARTLCR_H));
return;
}
static inline void pl011_set_parity_odd()
static inline void pl011_set_parity_odd(unsigned int base)
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
unsigned int val = 0;
read(val, (base + PL011_UARTLCR_H));
val &= ~PL011_PARITY_EVEN;
write(val, PL011_UARTLCR_H);
write(val, (base + PL011_UARTLCR_H));
return;
}
#define PL011_ENABLE_FIFOS (1 << 4)
static inline void pl011_enable_fifos()
static inline void pl011_enable_fifos(unsigned int base)
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
unsigned int val = 0;
read(val, (base + PL011_UARTLCR_H));
val |= PL011_ENABLE_FIFOS;
write(val, PL011_UARTLCR_H);
write(val, (base + PL011_UARTLCR_H));
return;
}
static inline void pl011_disable_fifos()
static inline void pl011_disable_fifos(unsigned int base)
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
unsigned int val = 0;
read(val, (base + PL011_UARTLCR_H));
val &= ~PL011_ENABLE_FIFOS;
write(val, PL011_UARTLCR_H);
write(val, (base + PL011_UARTLCR_H));
return;
}
#define PL011_WORD_WIDTH_SHIFT (5)
/* Sets the transfer word width for the data register. */
static inline void pl011_set_word_width(int size)
static inline void pl011_set_word_width(unsigned int base, int size)
{
unsigned int val;
val = 0;
unsigned int val = 0;
if(size < 5 || size > 8) /* Default is 8 */
size = 8;
/* Clear size field */
read(val, PL011_UARTLCR_H);
val &= ~(0x3 << PL011_WORD_WIDTH_SHIFT);
write(val, PL011_UARTLCR_H);
/* The formula is to write 5 less of size given:
/* Clear size field */
read(val, (base + PL011_UARTLCR_H));
val &= ~(0x3 << PL011_WORD_WIDTH_SHIFT);
write(val, (base + PL011_UARTLCR_H));
/*
* The formula is to write 5 less of size given:
* 11 = 8 bits
* 10 = 7 bits
* 01 = 6 bits
* 00 = 5 bits
*/
read(val, PL011_UARTLCR_H);
read(val, (base + PL011_UARTLCR_H));
val |= (size - 5) << PL011_WORD_WIDTH_SHIFT;
write(val, PL011_UARTLCR_H);
write(val, (base + PL011_UARTLCR_H));
return;
}
/*
/*
* Defines at which level of fifo fullness an irq will be generated.
* @xfer: tx fifo = 0, rx fifo = 1
* @level: Generate irq if:
@@ -314,95 +280,92 @@ static inline void pl011_set_word_width(int size)
* 4 rxfifo >= 7/8 full txfifo <= 7/8 full
* 5-7 reserved reserved
*/
static inline void pl011_set_irq_fifolevel(unsigned int xfer, unsigned int level)
static inline void pl011_set_irq_fifolevel(unsigned int base, \
unsigned int xfer, unsigned int level)
{
if(xfer != 1 && xfer != 0) /* Invalid fifo */
return;
if(level > 4) /* Invalid level */
return;
write(level << (xfer * 3), PL011_UARTIFLS);
return;
write(level << (xfer * 3), (base + PL011_UARTIFLS));
return;
}
/* returns which irqs are masked */
static inline unsigned int pl011_read_irqmask(void)
static inline unsigned int pl011_read_irqmask(unsigned int base)
{
unsigned int flags;
read(flags, PL011_UARTIMSC);
read(flags, (base + PL011_UARTIMSC));
return flags;
}
/* returns masked irq status */
static inline unsigned int pl011_read_irqstat(void)
static inline unsigned int pl011_read_irqstat(unsigned int base)
{
unsigned int irqstatus;
read(irqstatus, PL011_UARTMIS);
return irqstatus;
read(irqstatus, (base + PL011_UARTMIS));
return irqstatus;
}
/* Clears the given asserted irqs */
static inline void pl011_irq_clear(unsigned int flags)
static inline void pl011_irq_clear(unsigned int base, unsigned int flags)
{
if(flags > 0x3FF) { /* Invalid irq clearing bitvector */
if(flags > 0x3FF) {
/* Invalid irq clearing bitvector */
return;
}
/* Simply write the flags since it's a write-only register */
write(flags, PL011_UARTICR);
write(flags, (base + PL011_UARTICR));
return;
}
#define PL011_TXDMAEN (1 << 1)
#define PL011_RXDMAEN (1 << 0)
/* Enables dma transfers for uart. The dma controller
* must be initialised, set-up and enabled separately.
/*
* Enables dma transfers for uart. The dma controller
* must be initialised, set-up and enabled separately.
*/
static inline void pl011_tx_dma_enable()
static inline void pl011_tx_dma_enable(unsigned int base)
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
unsigned int val = 0;
read(val, (base + PL011_UARTDMACR));
val |= PL011_TXDMAEN;
write(val, PL011_UARTDMACR);
write(val, (base + PL011_UARTDMACR));
return;
}
/* Disables dma transfers for uart */
static inline void pl011_tx_dma_disable()
static inline void pl011_tx_dma_disable(unsigned int base)
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
unsigned int val = 0;
read(val, (base + PL011_UARTDMACR));
val &= ~PL011_TXDMAEN;
write(val, PL011_UARTDMACR);
write(val, (base + PL011_UARTDMACR));
return;
}
static inline void pl011_rx_dma_enable()
static inline void pl011_rx_dma_enable(unsigned int base)
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
unsigned int val = 0;
read(val, (base + PL011_UARTDMACR));
val |= PL011_RXDMAEN;
write(val, PL011_UARTDMACR);
write(val, (base + PL011_UARTDMACR));
return;
}
static inline void pl011_rx_dma_disable()
static inline void pl011_rx_dma_disable(unsigned int base)
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
unsigned int val = 0;
read(val, (base + PL011_UARTDMACR));
val &= ~PL011_RXDMAEN;
write(val, PL011_UARTDMACR);
write(val, (base +PL011_UARTDMACR));
return;
}
#endif /* __PL011__UART__ */

83
loader/libs/c/include/arch/setjmp.h
View File

@@ -1,83 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Author: Alex Webster
*/
typedef int jmp_buf[10];

212
loader/libs/c/include/complex.h
View File

@@ -1,212 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Authors: Ben Leslie
Description:
Complex arithmetic as per 7.3
Status: Functions defined, not implemented
*/
#error The complex library is incomplete
#define complex _Complex
#define _Complex_I (const float _Complex) foo
#define I _Complex_I
/* 7.3.5 Trigonometric functions */
/* 7.3.5.1 cacos */
double complex cacos(double complex z);
float complex cacosf(float complex z);
long double complex cacosl(long double complex z);
/* 7.3.5.2 casin */
double complex casin(double complex z);
float complex casinf(float complex z);
long double complex casinl(long double complex z);
/* 7.3.5.3 catan */
double complex catan(double complex z);
float complex catanf(float complex z);
long double complex catanl(long double complex z);
/* 7.3.5.4 ccos */
double complex ccos(double complex z);
float complex ccosf(float complex z);
long double complex ccosl(long double complex z);
/* 7.3.5.5 csin */
double complex csin(double complex z);
float complex csinf(float complex z);
long double complex csinl(long double complex z);
/* 7.3.5.6 ctan */
double complex ctan(double complex z);
float complex ctanf(float complex z);
long double complex ctanl(long double complex z);
/* 7.3.6 Hyperbolic functions */
/* 7.3.6.1 cacosh */
double complex cacosh(double complex z);
float complex cacoshf(float complex z);
long double complex cacoshf(long double complex z);
/* 7.3.6.2 casinh */
double complex casinh(double complex z);
float complex casinhf(float complex z);
long double complex casinhl(long double complex z);
/* 7.3.6.3 catanh */
double complex catanh(double complex z);
float complex catanhf(float complex z);
long double complex catanhl(long double complex z);
/* 7.3.6.4 ccosh */
double complex ccosh(double complex z);
float complex ccoshf(float complex z);
long double complex ccoshl(long double complex z);
/* 7.3.6.5 csinh */
double complex csinh(double complex z);
float complex csinhf(float complex z);
long double complex csinhl(long double complex z);
/* 7.3.6.6 ctanh */
double complex ctanh(double complex z);
float complex ctanhl(float complex z);
long double complex ctanhl(long double complex z);
/* 7.3.7 Exponential and logarithmic functions */
/* 7.3.7.1 cexp */
double complex cexp(double complex z);
float complex cexpf(float complex z);
long double complex cexpl(long double complex z);
/* 7.3.7.2 clog */
double complex clog(double complex z);
float complex clogf(float complex z);
long double complex clogl(long double complex z);
/* 7.3.8 Power and absolute value functions */
/* 7.3.8.1 cabs */
double complex cabs(double complex z);
float complex cabsf(float complex z);
long double complex cabsl(long double complex z);
/* 7.3.8.2 cpow */
double complex cpow(double complex z);
float complex cpowf(float complex z);
long double complex cpowl(long double complex z);
/* 7.3.8.3 csqrt */
double complex csqrt(double complex z);
float complex csqrtf(float complex z);
long double complex csqrtl(long double complex z);
/* 7.3.9 Manipulation functions */
/* 7.3.9.1 carg */
double complex carg(double complex z);
float complex cargf(float complex z);
long double complex cargl(long double complex z);
/* 7.3.9.2 cimag */
double complex cimag(double complex z);
float complex cimagf(float complex z);
long double complex cimagl(long double complex z);
/* 7.3.9.3 conj */
double complex conj(double complex z);
float complex conjf(float complex z);
long double complex conjl(long double complex z);
/* 7.3.9.4 cproj */
double complex cproj(double complex z);
float complex cprojf(float complex z);
long double complex cprojl(long double complex z);
/* 7.3.9.5 creal */
double complex creal(double complex z);
float complex crealf(float complex z);
long double complex creall(long double complex z);

204
loader/libs/c/include/ctype.h
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@@ -1,204 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Authors: Cristan Szmadja, Ben Leslie
Description:
Implements character handling as per 7.4
Status: Incomplete
Ignores locale
*/
#ifndef _CTYPE_H_
#define _CTYPE_H_
static inline int
iscntrl(int c)
{
return (0 <= c && c <= '\037') || c == '\177';
}
static inline int
isgraph(int c)
{
return ' ' < c && c < '\177';
}
static inline int
isprint(int c)
{
return ' ' <= c && c < '\177';
}
static inline int
isdigit(int c)
{
return '0' <= c && c <= '9';
}
static inline int
islower(int c)
{
return 'a' <= c && c <= 'z';
}
static inline int
isspace(int c)
{
return c == ' ' || ('\011' <= c && c <= '\015');
}
static inline int
isupper(int c)
{
return 'A' <= c && c <= 'Z';
}
static inline int
isalpha(int c)
{
return isupper(c) || islower(c);
}
static inline int
isalnum(int c)
{
return isalpha(c) || isdigit(c);
}
static inline int
ispunct(int c)
{
return isgraph(c) && !isalnum(c);
}
static inline int
isxdigit(int c)
{
return isdigit(c) || ('A' <= c && c <= 'F') || ('a' <= c && c <= 'f');
}
static inline int
tolower(int c)
{
return isupper(c) ? c + ('a' - 'A') : c;
}
static inline int
toupper(int c)
{
return islower(c) ? c - ('a' - 'A') : c;
}
static inline int
isascii(int c)
{
return 0 <= c && c <= '\177';
}
static inline int
toascii(int c)
{
return c & 0177;
}
static inline int
digittoint(int c)
{
return isdigit(c) ? c - '0' : 'A' <= c
&& c <= 'Z' ? c - 'A' : 'a' <= c && c <= 'z' ? c - 'a' : 99;
}
#endif /* !_CTYPE_H_ */
/* XXX: Extra things needed by POSIX... need to find a correct #ifndef */
/*
int isascii(int);
int toascii(int);
#define _toupper(x)
#define _tolower(x)
*/

104
loader/libs/c/include/errno.h
View File

@@ -1,104 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Authors: Ben Leslie
Description:
Errors as per 7.5
Status: Complete
Restrictions: Single threaded
*/
#ifndef _ERRNO_H_
#define _ERRNO_H_
#define EDOM 1
#define EILSEQ 2
#define ERANGE 3
#include <l4/thread.h>
#ifndef THREAD_SAFE
extern int errno;
#else
#define errno (*((int *)__L4_TCR_ThreadLocalStorage()))
#endif
#endif /* _ERRNO_H_ */

101
loader/libs/c/include/iso646.h
View File

@@ -1,101 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Authors: Ben Leslie
Description:
Alternative spellings as per 7.9
*/
#ifndef _ISO646_H_
#define _ISO646_H_
#define and &&
#define and_q &=
#define bitand &
#define bitor |
#define compl ~
#define not !
#define not_eq !=
#define or ||
#define or_eq |=
#define xor ^
#define xor_eq ^=
#endif /* _ISO646_H_ */

117
loader/libs/c/include/locale.h
View File

@@ -1,117 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
#include <stddef.h>
struct lconv {
char *decimal_point;
char *thousands_sep;
char *grouping;
char *mon_deciaml_point;
char *mon_thouasands_sep;
char *mon_grouping;
char *positive_sign;
char *negative_sign;
char *currency_symbol;
char frac_digits;
char p_cs_precedes;
char n_cs_precedes;
char p_sep_by_space;
char n_sep_by_space;
char p_sign_posn;
char n_sign_posn;
char *int_curr_symbol;
char int_frac_digits;
char int_p_cs_precedes;
char int_n_cs_precedes;
char int_p_sep_by_space;
char int_n_sep_by_space;
char int_p_sign_posn;
char int_n_sign_posn;
};
#define LC_ALL 1
#define LC_COLLATE 2
#define LC_CTYPE 3
#define LC_MONETARY 4
#define LC_NUMERIC 5
#define LC_TIME 6
char *setlocale(int category, const char *locale);
struct lconv *localeconv(void);

90
loader/libs/c/include/setjmp.h
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@@ -1,90 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Author: Ben Leslie, Alex Webster
*/
#ifndef _SETJMP_H_
#define _SETJMP_H_
#include <arch/setjmp.h>
int setjmp(jmp_buf);
void longjmp(jmp_buf, int);
#endif /* _SETJMP_H_ */

87
loader/libs/c/include/sys-baremetal/arch-arm/arch/inttypes.h
View File

@@ -1,87 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Author: Ben Leslie
*/
#define __LENGTH_8_MOD "hh"
#define __LENGTH_16_MOD "h"
#define __LENGTH_32_MOD
#define __LENGTH_64_MOD "ll"
#define __LENGTH_MAX_MOD "ll"
#define __LENGTH_PTR_MOD

408
loader/libs/c/include/sys-baremetal/arch-arm/arch/pl011_uart.h
View File

@@ -1,408 +0,0 @@
#ifndef __PL011__UART__H__
#define __PL011__UART__H__
/*
* PL011 UART Generic driver implementation.
* Copyright Bahadir Balban (C) 2006
*
* The particular intention of this code is that it has been carefully
* written as decoupled from os-specific code and in a verbose way such
* that it clearly demonstrates how the device operates, reducing the
* amount of time to be spent for understanding the operational model
* and implementing a driver from scratch. This is the very first to be
* such a driver so far, hopefully it will turn out to be useful.
*/
/* Default base address for this chip */
#define PL011_DEFAULT_PHYSICAL_BASE 0x101F1000
#define PL011_BASE PL011_DEFAULT_PHYSICAL_BASE
/* Architecture specific memory access macros */
#define read(val, address) val = *((volatile unsigned int *) address)
#define write(val, address) *((volatile unsigned int *) address) = val
/* Register offsets */
#define PL011_UARTDR (PL011_BASE + 0x00)
#define PL011_UARTRSR (PL011_BASE + 0x04)
#define PL011_UARTECR (PL011_BASE + 0x04)
#define PL011_UARTFR (PL011_BASE + 0x18)
#define PL011_UARTILPR (PL011_BASE + 0x20)
#define PL011_UARTIBRD (PL011_BASE + 0x24)
#define PL011_UARTFBRD (PL011_BASE + 0x28)
#define PL011_UARTLCR_H (PL011_BASE + 0x2C)
#define PL011_UARTCR (PL011_BASE + 0x30)
#define PL011_UARTIFLS (PL011_BASE + 0x34)
#define PL011_UARTIMSC (PL011_BASE + 0x38)
#define PL011_UARTRIS (PL011_BASE + 0x3C)
#define PL011_UARTMIS (PL011_BASE + 0x40)
#define PL011_UARTICR (PL011_BASE + 0x44)
#define PL011_UARTDMACR (PL011_BASE + 0x48)
/* IRQ bits for each uart irq event */
#define PL011_RXIRQ (1 << 4)
#define PL011_TXIRQ (1 << 5)
#define PL011_RXTIMEOUTIRQ (1 << 6)
#define PL011_FEIRQ (1 << 7)
#define PL011_PEIRQ (1 << 8)
#define PL011_BEIRQ (1 << 9)
#define PL011_OEIRQ (1 << 10)
struct pl011_uart;
int pl011_initialise(struct pl011_uart *);
int pl011_tx_char(char);
int pl011_rx_char(char *);
void pl011_set_baudrate(unsigned int, unsigned int);
void pl011_set_irq_mask(unsigned int);
void pl011_clr_irq_mask(unsigned int);
void pl011_irq_handler(struct pl011_uart *);
void pl011_tx_irq_handler(struct pl011_uart *, unsigned int);
void pl011_rx_irq_handler(struct pl011_uart *, unsigned int);
void pl011_error_irq_handler(struct pl011_uart *, unsigned int);
static inline void pl011_uart_enable(void);
static inline void pl011_uart_disable(void);
static inline void pl011_tx_enable(void);
static inline void pl011_tx_disable(void);
static inline void pl011_rx_enable(void);
static inline void pl011_rx_disable(void);
static inline void pl011_irq_clear(unsigned int flags);
static inline unsigned int pl011_read_irqstat(void);
static inline unsigned int pl011_read_irqmask(void);
static inline void pl011_rx_dma_disable(void);
static inline void pl011_rx_dma_enable(void);
static inline void pl011_tx_dma_enable(void);
static inline void pl011_tx_dma_disable(void);
static inline void pl011_set_irq_fifolevel(unsigned int xfer,
unsigned int level);
static inline void pl011_set_word_width(int size);
static inline void pl011_disable_fifos(void);
static inline void pl011_set_parity_even(void);
static inline void pl011_parity_enable(void);
static inline void pl011_set_stopbits(int stopbits);
static inline void pl011_set_parity_odd(void);
static inline void pl011_enable_fifos(void);
static inline void pl011_parity_disable(void);
struct pl011_uart_ops {
int (*initialise)(struct pl011_uart *);
int (*tx_char)(char);
int (*rx_char)(char *);
void (*set_baudrate)(unsigned int, unsigned int);
void (*set_irq_mask)(unsigned int);
void (*clr_irq_mask)(unsigned int);
void (*irq_handler)(struct pl011_uart *);
void (*tx_irq_handler)(struct pl011_uart *, unsigned int);
void (*rx_irq_handler)(struct pl011_uart *, unsigned int);
void (*error_irq_handler)(struct pl011_uart *, unsigned int);
};
struct pl011_uart {
const unsigned int base;
struct pl011_uart_ops ops;
unsigned int frame_errors;
unsigned int parity_errors;
unsigned int break_errors;
unsigned int overrun_errors;
unsigned int rx_timeout_errors;
};
#define PL011_UARTEN (1 << 0)
static inline void pl011_uart_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val |= PL011_UARTEN;
write(val, PL011_UARTCR);
return;
}
static inline void pl011_uart_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val &= ~PL011_UARTEN;
write(val, PL011_UARTCR);
return;
}
#define PL011_TXE (1 << 8)
static inline void pl011_tx_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val |= PL011_TXE;
write(val, PL011_UARTCR);
return;
}
static inline void pl011_tx_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val &= ~PL011_TXE;
write(val, PL011_UARTCR);
return;
}
#define PL011_RXE (1 << 9)
static inline void pl011_rx_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val |= PL011_RXE;
write(val, PL011_UARTCR);
return;
}
static inline void pl011_rx_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val &= ~PL011_RXE;
write(val, PL011_UARTCR);
return;
}
#define PL011_TWO_STOPBITS_SELECT (1 << 3)
static inline void pl011_set_stopbits(int stopbits)
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
if(stopbits == 2) { /* Set to two bits */
val |= PL011_TWO_STOPBITS_SELECT;
} else { /* Default is 1 */
val &= ~PL011_TWO_STOPBITS_SELECT;
}
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_PARITY_ENABLE (1 << 1)
static inline void pl011_parity_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val |= PL011_PARITY_ENABLE;
write(val, PL011_UARTLCR_H);
return;
}
static inline void pl011_parity_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val &= ~PL011_PARITY_ENABLE;
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_PARITY_EVEN (1 << 2)
static inline void pl011_set_parity_even()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val |= PL011_PARITY_EVEN;
write(val, PL011_UARTLCR_H);
return;
}
static inline void pl011_set_parity_odd()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val &= ~PL011_PARITY_EVEN;
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_ENABLE_FIFOS (1 << 4)
static inline void pl011_enable_fifos()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val |= PL011_ENABLE_FIFOS;
write(val, PL011_UARTLCR_H);
return;
}
static inline void pl011_disable_fifos()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val &= ~PL011_ENABLE_FIFOS;
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_WORD_WIDTH_SHIFT (5)
/* Sets the transfer word width for the data register. */
static inline void pl011_set_word_width(int size)
{
unsigned int val;
val = 0;
if(size < 5 || size > 8) /* Default is 8 */
size = 8;
/* Clear size field */
read(val, PL011_UARTLCR_H);
val &= ~(0x3 << PL011_WORD_WIDTH_SHIFT);
write(val, PL011_UARTLCR_H);
/* The formula is to write 5 less of size given:
* 11 = 8 bits
* 10 = 7 bits
* 01 = 6 bits
* 00 = 5 bits
*/
read(val, PL011_UARTLCR_H);
val |= (size - 5) << PL011_WORD_WIDTH_SHIFT;
write(val, PL011_UARTLCR_H);
return;
}
/*
* Defines at which level of fifo fullness an irq will be generated.
* @xfer: tx fifo = 0, rx fifo = 1
* @level: Generate irq if:
* 0 rxfifo >= 1/8 full txfifo <= 1/8 full
* 1 rxfifo >= 1/4 full txfifo <= 1/4 full
* 2 rxfifo >= 1/2 full txfifo <= 1/2 full
* 3 rxfifo >= 3/4 full txfifo <= 3/4 full
* 4 rxfifo >= 7/8 full txfifo <= 7/8 full
* 5-7 reserved reserved
*/
static inline void pl011_set_irq_fifolevel(unsigned int xfer, unsigned int level)
{
if(xfer != 1 && xfer != 0) /* Invalid fifo */
return;
if(level > 4) /* Invalid level */
return;
write(level << (xfer * 3), PL011_UARTIFLS);
return;
}
/* returns which irqs are masked */
static inline unsigned int pl011_read_irqmask(void)
{
unsigned int flags;
read(flags, PL011_UARTIMSC);
return flags;
}
/* returns masked irq status */
static inline unsigned int pl011_read_irqstat(void)
{
unsigned int irqstatus;
read(irqstatus, PL011_UARTMIS);
return irqstatus;
}
/* Clears the given asserted irqs */
static inline void pl011_irq_clear(unsigned int flags)
{
if(flags > 0x3FF) { /* Invalid irq clearing bitvector */
return;
}
/* Simply write the flags since it's a write-only register */
write(flags, PL011_UARTICR);
return;
}
#define PL011_TXDMAEN (1 << 1)
#define PL011_RXDMAEN (1 << 0)
/* Enables dma transfers for uart. The dma controller
* must be initialised, set-up and enabled separately.
*/
static inline void pl011_tx_dma_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val |= PL011_TXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
/* Disables dma transfers for uart */
static inline void pl011_tx_dma_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val &= ~PL011_TXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
static inline void pl011_rx_dma_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val |= PL011_RXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
static inline void pl011_rx_dma_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val &= ~PL011_RXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
#endif /* __PL011__UART__ */

83
loader/libs/c/include/sys-baremetal/arch-arm/arch/setjmp.h
View File

@@ -1,83 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Author: Alex Webster
*/
typedef int jmp_buf[10];

92
loader/libs/c/include/sys-baremetal/arch-arm/arch/stdint.h
View File

@@ -1,92 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Author: Ben Leslie
*/
typedef signed char int8_t;
typedef short int16_t;
typedef int int32_t;
typedef long long int64_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef unsigned long long uint64_t;
#define __PTR_SIZE 32

87
loader/libs/c/include/sys-baremetal/arch-arm/inttypes.h
View File

@@ -1,87 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Author: Ben Leslie
*/
#define __LENGTH_8_MOD "hh"
#define __LENGTH_16_MOD "h"
#define __LENGTH_32_MOD
#define __LENGTH_64_MOD "ll"
#define __LENGTH_MAX_MOD "ll"
#define __LENGTH_PTR_MOD

408
loader/libs/c/include/sys-baremetal/arch-arm/pl011_uart.h
View File

@@ -1,408 +0,0 @@
#ifndef __PL011__UART__H__
#define __PL011__UART__H__
/*
* PL011 UART Generic driver implementation.
* Copyright Bahadir Balban (C) 2006
*
* The particular intention of this code is that it has been carefully
* written as decoupled from os-specific code and in a verbose way such
* that it clearly demonstrates how the device operates, reducing the
* amount of time to be spent for understanding the operational model
* and implementing a driver from scratch. This is the very first to be
* such a driver so far, hopefully it will turn out to be useful.
*/
/* Default base address for this chip */
#define PL011_DEFAULT_PHYSICAL_BASE 0x101F1000
#define PL011_BASE PL011_DEFAULT_PHYSICAL_BASE
/* Architecture specific memory access macros */
#define read(val, address) val = *((volatile unsigned int *) address)
#define write(val, address) *((volatile unsigned int *) address) = val
/* Register offsets */
#define PL011_UARTDR (PL011_BASE + 0x00)
#define PL011_UARTRSR (PL011_BASE + 0x04)
#define PL011_UARTECR (PL011_BASE + 0x04)
#define PL011_UARTFR (PL011_BASE + 0x18)
#define PL011_UARTILPR (PL011_BASE + 0x20)
#define PL011_UARTIBRD (PL011_BASE + 0x24)
#define PL011_UARTFBRD (PL011_BASE + 0x28)
#define PL011_UARTLCR_H (PL011_BASE + 0x2C)
#define PL011_UARTCR (PL011_BASE + 0x30)
#define PL011_UARTIFLS (PL011_BASE + 0x34)
#define PL011_UARTIMSC (PL011_BASE + 0x38)
#define PL011_UARTRIS (PL011_BASE + 0x3C)
#define PL011_UARTMIS (PL011_BASE + 0x40)
#define PL011_UARTICR (PL011_BASE + 0x44)
#define PL011_UARTDMACR (PL011_BASE + 0x48)
/* IRQ bits for each uart irq event */
#define PL011_RXIRQ (1 << 4)
#define PL011_TXIRQ (1 << 5)
#define PL011_RXTIMEOUTIRQ (1 << 6)
#define PL011_FEIRQ (1 << 7)
#define PL011_PEIRQ (1 << 8)
#define PL011_BEIRQ (1 << 9)
#define PL011_OEIRQ (1 << 10)
struct pl011_uart;
int pl011_initialise(struct pl011_uart *);
int pl011_tx_char(char);
int pl011_rx_char(char *);
void pl011_set_baudrate(unsigned int, unsigned int);
void pl011_set_irq_mask(unsigned int);
void pl011_clr_irq_mask(unsigned int);
void pl011_irq_handler(struct pl011_uart *);
void pl011_tx_irq_handler(struct pl011_uart *, unsigned int);
void pl011_rx_irq_handler(struct pl011_uart *, unsigned int);
void pl011_error_irq_handler(struct pl011_uart *, unsigned int);
static inline void pl011_uart_enable(void);
static inline void pl011_uart_disable(void);
static inline void pl011_tx_enable(void);
static inline void pl011_tx_disable(void);
static inline void pl011_rx_enable(void);
static inline void pl011_rx_disable(void);
static inline void pl011_irq_clear(unsigned int flags);
static inline unsigned int pl011_read_irqstat(void);
static inline unsigned int pl011_read_irqmask(void);
static inline void pl011_rx_dma_disable(void);
static inline void pl011_rx_dma_enable(void);
static inline void pl011_tx_dma_enable(void);
static inline void pl011_tx_dma_disable(void);
static inline void pl011_set_irq_fifolevel(unsigned int xfer,
unsigned int level);
static inline void pl011_set_word_width(int size);
static inline void pl011_disable_fifos(void);
static inline void pl011_set_parity_even(void);
static inline void pl011_parity_enable(void);
static inline void pl011_set_stopbits(int stopbits);
static inline void pl011_set_parity_odd(void);
static inline void pl011_enable_fifos(void);
static inline void pl011_parity_disable(void);
struct pl011_uart_ops {
int (*initialise)(struct pl011_uart *);
int (*tx_char)(char);
int (*rx_char)(char *);
void (*set_baudrate)(unsigned int, unsigned int);
void (*set_irq_mask)(unsigned int);
void (*clr_irq_mask)(unsigned int);
void (*irq_handler)(struct pl011_uart *);
void (*tx_irq_handler)(struct pl011_uart *, unsigned int);
void (*rx_irq_handler)(struct pl011_uart *, unsigned int);
void (*error_irq_handler)(struct pl011_uart *, unsigned int);
};
struct pl011_uart {
const unsigned int base;
struct pl011_uart_ops ops;
unsigned int frame_errors;
unsigned int parity_errors;
unsigned int break_errors;
unsigned int overrun_errors;
unsigned int rx_timeout_errors;
};
#define PL011_UARTEN (1 << 0)
static inline void pl011_uart_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val |= PL011_UARTEN;
write(val, PL011_UARTCR);
return;
}
static inline void pl011_uart_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val &= ~PL011_UARTEN;
write(val, PL011_UARTCR);
return;
}
#define PL011_TXE (1 << 8)
static inline void pl011_tx_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val |= PL011_TXE;
write(val, PL011_UARTCR);
return;
}
static inline void pl011_tx_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val &= ~PL011_TXE;
write(val, PL011_UARTCR);
return;
}
#define PL011_RXE (1 << 9)
static inline void pl011_rx_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val |= PL011_RXE;
write(val, PL011_UARTCR);
return;
}
static inline void pl011_rx_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val &= ~PL011_RXE;
write(val, PL011_UARTCR);
return;
}
#define PL011_TWO_STOPBITS_SELECT (1 << 3)
static inline void pl011_set_stopbits(int stopbits)
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
if(stopbits == 2) { /* Set to two bits */
val |= PL011_TWO_STOPBITS_SELECT;
} else { /* Default is 1 */
val &= ~PL011_TWO_STOPBITS_SELECT;
}
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_PARITY_ENABLE (1 << 1)
static inline void pl011_parity_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val |= PL011_PARITY_ENABLE;
write(val, PL011_UARTLCR_H);
return;
}
static inline void pl011_parity_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val &= ~PL011_PARITY_ENABLE;
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_PARITY_EVEN (1 << 2)
static inline void pl011_set_parity_even()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val |= PL011_PARITY_EVEN;
write(val, PL011_UARTLCR_H);
return;
}
static inline void pl011_set_parity_odd()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val &= ~PL011_PARITY_EVEN;
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_ENABLE_FIFOS (1 << 4)
static inline void pl011_enable_fifos()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val |= PL011_ENABLE_FIFOS;
write(val, PL011_UARTLCR_H);
return;
}
static inline void pl011_disable_fifos()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val &= ~PL011_ENABLE_FIFOS;
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_WORD_WIDTH_SHIFT (5)
/* Sets the transfer word width for the data register. */
static inline void pl011_set_word_width(int size)
{
unsigned int val;
val = 0;
if(size < 5 || size > 8) /* Default is 8 */
size = 8;
/* Clear size field */
read(val, PL011_UARTLCR_H);
val &= ~(0x3 << PL011_WORD_WIDTH_SHIFT);
write(val, PL011_UARTLCR_H);
/* The formula is to write 5 less of size given:
* 11 = 8 bits
* 10 = 7 bits
* 01 = 6 bits
* 00 = 5 bits
*/
read(val, PL011_UARTLCR_H);
val |= (size - 5) << PL011_WORD_WIDTH_SHIFT;
write(val, PL011_UARTLCR_H);
return;
}
/*
* Defines at which level of fifo fullness an irq will be generated.
* @xfer: tx fifo = 0, rx fifo = 1
* @level: Generate irq if:
* 0 rxfifo >= 1/8 full txfifo <= 1/8 full
* 1 rxfifo >= 1/4 full txfifo <= 1/4 full
* 2 rxfifo >= 1/2 full txfifo <= 1/2 full
* 3 rxfifo >= 3/4 full txfifo <= 3/4 full
* 4 rxfifo >= 7/8 full txfifo <= 7/8 full
* 5-7 reserved reserved
*/
static inline void pl011_set_irq_fifolevel(unsigned int xfer, unsigned int level)
{
if(xfer != 1 && xfer != 0) /* Invalid fifo */
return;
if(level > 4) /* Invalid level */
return;
write(level << (xfer * 3), PL011_UARTIFLS);
return;
}
/* returns which irqs are masked */
static inline unsigned int pl011_read_irqmask(void)
{
unsigned int flags;
read(flags, PL011_UARTIMSC);
return flags;
}
/* returns masked irq status */
static inline unsigned int pl011_read_irqstat(void)
{
unsigned int irqstatus;
read(irqstatus, PL011_UARTMIS);
return irqstatus;
}
/* Clears the given asserted irqs */
static inline void pl011_irq_clear(unsigned int flags)
{
if(flags > 0x3FF) { /* Invalid irq clearing bitvector */
return;
}
/* Simply write the flags since it's a write-only register */
write(flags, PL011_UARTICR);
return;
}
#define PL011_TXDMAEN (1 << 1)
#define PL011_RXDMAEN (1 << 0)
/* Enables dma transfers for uart. The dma controller
* must be initialised, set-up and enabled separately.
*/
static inline void pl011_tx_dma_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val |= PL011_TXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
/* Disables dma transfers for uart */
static inline void pl011_tx_dma_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val &= ~PL011_TXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
static inline void pl011_rx_dma_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val |= PL011_RXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
static inline void pl011_rx_dma_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val &= ~PL011_RXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
#endif /* __PL011__UART__ */

83
loader/libs/c/include/sys-baremetal/arch-arm/setjmp.h
View File

@@ -1,83 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Author: Alex Webster
*/
typedef int jmp_buf[10];

92
loader/libs/c/include/sys-baremetal/arch-arm/stdint.h
View File

@@ -1,92 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Author: Ben Leslie
*/
typedef signed char int8_t;
typedef short int16_t;
typedef int int32_t;
typedef long long int64_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef unsigned long long uint64_t;
#define __PTR_SIZE 32

87
loader/libs/c/include/sys-userspace/arch-arm/arch/inttypes.h
View File

@@ -1,87 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Author: Ben Leslie
*/
#define __LENGTH_8_MOD "hh"
#define __LENGTH_16_MOD "h"
#define __LENGTH_32_MOD
#define __LENGTH_64_MOD "ll"
#define __LENGTH_MAX_MOD "ll"
#define __LENGTH_PTR_MOD

408
loader/libs/c/include/sys-userspace/arch-arm/arch/pl011_uart.h
View File

@@ -1,408 +0,0 @@
#ifndef __PL011__UART__H__
#define __PL011__UART__H__
/*
* PL011 UART Generic driver implementation.
* Copyright Bahadir Balban (C) 2006
*
* The particular intention of this code is that it has been carefully
* written as decoupled from os-specific code and in a verbose way such
* that it clearly demonstrates how the device operates, reducing the
* amount of time to be spent for understanding the operational model
* and implementing a driver from scratch. This is the very first to be
* such a driver so far, hopefully it will turn out to be useful.
*/
/* Default base address for this chip */
#define PL011_USR_BASE 0x500000
#define PL011_BASE PL011_USR_BASE
/* Architecture specific memory access macros */
#define read(val, address) val = *((volatile unsigned int *) address)
#define write(val, address) *((volatile unsigned int *) address) = val
/* Register offsets */
#define PL011_UARTDR (PL011_BASE + 0x00)
#define PL011_UARTRSR (PL011_BASE + 0x04)
#define PL011_UARTECR (PL011_BASE + 0x04)
#define PL011_UARTFR (PL011_BASE + 0x18)
#define PL011_UARTILPR (PL011_BASE + 0x20)
#define PL011_UARTIBRD (PL011_BASE + 0x24)
#define PL011_UARTFBRD (PL011_BASE + 0x28)
#define PL011_UARTLCR_H (PL011_BASE + 0x2C)
#define PL011_UARTCR (PL011_BASE + 0x30)
#define PL011_UARTIFLS (PL011_BASE + 0x34)
#define PL011_UARTIMSC (PL011_BASE + 0x38)
#define PL011_UARTRIS (PL011_BASE + 0x3C)
#define PL011_UARTMIS (PL011_BASE + 0x40)
#define PL011_UARTICR (PL011_BASE + 0x44)
#define PL011_UARTDMACR (PL011_BASE + 0x48)
/* IRQ bits for each uart irq event */
#define PL011_RXIRQ (1 << 4)
#define PL011_TXIRQ (1 << 5)
#define PL011_RXTIMEOUTIRQ (1 << 6)
#define PL011_FEIRQ (1 << 7)
#define PL011_PEIRQ (1 << 8)
#define PL011_BEIRQ (1 << 9)
#define PL011_OEIRQ (1 << 10)
struct pl011_uart;
int pl011_initialise(struct pl011_uart *);
int pl011_tx_char(char);
int pl011_rx_char(char *);
void pl011_set_baudrate(unsigned int, unsigned int);
void pl011_set_irq_mask(unsigned int);
void pl011_clr_irq_mask(unsigned int);
void pl011_irq_handler(struct pl011_uart *);
void pl011_tx_irq_handler(struct pl011_uart *, unsigned int);
void pl011_rx_irq_handler(struct pl011_uart *, unsigned int);
void pl011_error_irq_handler(struct pl011_uart *, unsigned int);
static inline void pl011_uart_enable(void);
static inline void pl011_uart_disable(void);
static inline void pl011_tx_enable(void);
static inline void pl011_tx_disable(void);
static inline void pl011_rx_enable(void);
static inline void pl011_rx_disable(void);
static inline void pl011_irq_clear(unsigned int flags);
static inline unsigned int pl011_read_irqstat(void);
static inline unsigned int pl011_read_irqmask(void);
static inline void pl011_rx_dma_disable(void);
static inline void pl011_rx_dma_enable(void);
static inline void pl011_tx_dma_enable(void);
static inline void pl011_tx_dma_disable(void);
static inline void pl011_set_irq_fifolevel(unsigned int xfer,
unsigned int level);
static inline void pl011_set_word_width(int size);
static inline void pl011_disable_fifos(void);
static inline void pl011_set_parity_even(void);
static inline void pl011_parity_enable(void);
static inline void pl011_set_stopbits(int stopbits);
static inline void pl011_set_parity_odd(void);
static inline void pl011_enable_fifos(void);
static inline void pl011_parity_disable(void);
struct pl011_uart_ops {
int (*initialise)(struct pl011_uart *);
int (*tx_char)(char);
int (*rx_char)(char *);
void (*set_baudrate)(unsigned int, unsigned int);
void (*set_irq_mask)(unsigned int);
void (*clr_irq_mask)(unsigned int);
void (*irq_handler)(struct pl011_uart *);
void (*tx_irq_handler)(struct pl011_uart *, unsigned int);
void (*rx_irq_handler)(struct pl011_uart *, unsigned int);
void (*error_irq_handler)(struct pl011_uart *, unsigned int);
};
struct pl011_uart {
const unsigned int base;
struct pl011_uart_ops ops;
unsigned int frame_errors;
unsigned int parity_errors;
unsigned int break_errors;
unsigned int overrun_errors;
unsigned int rx_timeout_errors;
};
#define PL011_UARTEN (1 << 0)
static inline void pl011_uart_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val |= PL011_UARTEN;
write(val, PL011_UARTCR);
return;
}
static inline void pl011_uart_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val &= ~PL011_UARTEN;
write(val, PL011_UARTCR);
return;
}
#define PL011_TXE (1 << 8)
static inline void pl011_tx_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val |= PL011_TXE;
write(val, PL011_UARTCR);
return;
}
static inline void pl011_tx_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val &= ~PL011_TXE;
write(val, PL011_UARTCR);
return;
}
#define PL011_RXE (1 << 9)
static inline void pl011_rx_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val |= PL011_RXE;
write(val, PL011_UARTCR);
return;
}
static inline void pl011_rx_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val &= ~PL011_RXE;
write(val, PL011_UARTCR);
return;
}
#define PL011_TWO_STOPBITS_SELECT (1 << 3)
static inline void pl011_set_stopbits(int stopbits)
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
if(stopbits == 2) { /* Set to two bits */
val |= PL011_TWO_STOPBITS_SELECT;
} else { /* Default is 1 */
val &= ~PL011_TWO_STOPBITS_SELECT;
}
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_PARITY_ENABLE (1 << 1)
static inline void pl011_parity_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val |= PL011_PARITY_ENABLE;
write(val, PL011_UARTLCR_H);
return;
}
static inline void pl011_parity_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val &= ~PL011_PARITY_ENABLE;
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_PARITY_EVEN (1 << 2)
static inline void pl011_set_parity_even()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val |= PL011_PARITY_EVEN;
write(val, PL011_UARTLCR_H);
return;
}
static inline void pl011_set_parity_odd()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val &= ~PL011_PARITY_EVEN;
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_ENABLE_FIFOS (1 << 4)
static inline void pl011_enable_fifos()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val |= PL011_ENABLE_FIFOS;
write(val, PL011_UARTLCR_H);
return;
}
static inline void pl011_disable_fifos()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val &= ~PL011_ENABLE_FIFOS;
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_WORD_WIDTH_SHIFT (5)
/* Sets the transfer word width for the data register. */
static inline void pl011_set_word_width(int size)
{
unsigned int val;
val = 0;
if(size < 5 || size > 8) /* Default is 8 */
size = 8;
/* Clear size field */
read(val, PL011_UARTLCR_H);
val &= ~(0x3 << PL011_WORD_WIDTH_SHIFT);
write(val, PL011_UARTLCR_H);
/* The formula is to write 5 less of size given:
* 11 = 8 bits
* 10 = 7 bits
* 01 = 6 bits
* 00 = 5 bits
*/
read(val, PL011_UARTLCR_H);
val |= (size - 5) << PL011_WORD_WIDTH_SHIFT;
write(val, PL011_UARTLCR_H);
return;
}
/*
* Defines at which level of fifo fullness an irq will be generated.
* @xfer: tx fifo = 0, rx fifo = 1
* @level: Generate irq if:
* 0 rxfifo >= 1/8 full txfifo <= 1/8 full
* 1 rxfifo >= 1/4 full txfifo <= 1/4 full
* 2 rxfifo >= 1/2 full txfifo <= 1/2 full
* 3 rxfifo >= 3/4 full txfifo <= 3/4 full
* 4 rxfifo >= 7/8 full txfifo <= 7/8 full
* 5-7 reserved reserved
*/
static inline void pl011_set_irq_fifolevel(unsigned int xfer, unsigned int level)
{
if(xfer != 1 && xfer != 0) /* Invalid fifo */
return;
if(level > 4) /* Invalid level */
return;
write(level << (xfer * 3), PL011_UARTIFLS);
return;
}
/* returns which irqs are masked */
static inline unsigned int pl011_read_irqmask(void)
{
unsigned int flags;
read(flags, PL011_UARTIMSC);
return flags;
}
/* returns masked irq status */
static inline unsigned int pl011_read_irqstat(void)
{
unsigned int irqstatus;
read(irqstatus, PL011_UARTMIS);
return irqstatus;
}
/* Clears the given asserted irqs */
static inline void pl011_irq_clear(unsigned int flags)
{
if(flags > 0x3FF) { /* Invalid irq clearing bitvector */
return;
}
/* Simply write the flags since it's a write-only register */
write(flags, PL011_UARTICR);
return;
}
#define PL011_TXDMAEN (1 << 1)
#define PL011_RXDMAEN (1 << 0)
/* Enables dma transfers for uart. The dma controller
* must be initialised, set-up and enabled separately.
*/
static inline void pl011_tx_dma_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val |= PL011_TXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
/* Disables dma transfers for uart */
static inline void pl011_tx_dma_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val &= ~PL011_TXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
static inline void pl011_rx_dma_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val |= PL011_RXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
static inline void pl011_rx_dma_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val &= ~PL011_RXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
#endif /* __PL011__UART__ */

83
loader/libs/c/include/sys-userspace/arch-arm/arch/setjmp.h
View File

@@ -1,83 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Author: Alex Webster
*/
typedef int jmp_buf[10];

92
loader/libs/c/include/sys-userspace/arch-arm/arch/stdint.h
View File

@@ -1,92 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Author: Ben Leslie
*/
typedef signed char int8_t;
typedef short int16_t;
typedef int int32_t;
typedef long long int64_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef unsigned long long uint64_t;
#define __PTR_SIZE 32

87
loader/libs/c/include/sys-userspace/arch-arm/inttypes.h
View File

@@ -1,87 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Author: Ben Leslie
*/
#define __LENGTH_8_MOD "hh"
#define __LENGTH_16_MOD "h"
#define __LENGTH_32_MOD
#define __LENGTH_64_MOD "ll"
#define __LENGTH_MAX_MOD "ll"
#define __LENGTH_PTR_MOD

408
loader/libs/c/include/sys-userspace/arch-arm/pl011_uart.h
View File

@@ -1,408 +0,0 @@
#ifndef __PL011__UART__H__
#define __PL011__UART__H__
/*
* PL011 UART Generic driver implementation.
* Copyright Bahadir Balban (C) 2006
*
* The particular intention of this code is that it has been carefully
* written as decoupled from os-specific code and in a verbose way such
* that it clearly demonstrates how the device operates, reducing the
* amount of time to be spent for understanding the operational model
* and implementing a driver from scratch. This is the very first to be
* such a driver so far, hopefully it will turn out to be useful.
*/
/* Default base address for this chip */
#define PL011_USR_BASE 0x500000
#define PL011_BASE PL011_USR_BASE
/* Architecture specific memory access macros */
#define read(val, address) val = *((volatile unsigned int *) address)
#define write(val, address) *((volatile unsigned int *) address) = val
/* Register offsets */
#define PL011_UARTDR (PL011_BASE + 0x00)
#define PL011_UARTRSR (PL011_BASE + 0x04)
#define PL011_UARTECR (PL011_BASE + 0x04)
#define PL011_UARTFR (PL011_BASE + 0x18)
#define PL011_UARTILPR (PL011_BASE + 0x20)
#define PL011_UARTIBRD (PL011_BASE + 0x24)
#define PL011_UARTFBRD (PL011_BASE + 0x28)
#define PL011_UARTLCR_H (PL011_BASE + 0x2C)
#define PL011_UARTCR (PL011_BASE + 0x30)
#define PL011_UARTIFLS (PL011_BASE + 0x34)
#define PL011_UARTIMSC (PL011_BASE + 0x38)
#define PL011_UARTRIS (PL011_BASE + 0x3C)
#define PL011_UARTMIS (PL011_BASE + 0x40)
#define PL011_UARTICR (PL011_BASE + 0x44)
#define PL011_UARTDMACR (PL011_BASE + 0x48)
/* IRQ bits for each uart irq event */
#define PL011_RXIRQ (1 << 4)
#define PL011_TXIRQ (1 << 5)
#define PL011_RXTIMEOUTIRQ (1 << 6)
#define PL011_FEIRQ (1 << 7)
#define PL011_PEIRQ (1 << 8)
#define PL011_BEIRQ (1 << 9)
#define PL011_OEIRQ (1 << 10)
struct pl011_uart;
int pl011_initialise(struct pl011_uart *);
int pl011_tx_char(char);
int pl011_rx_char(char *);
void pl011_set_baudrate(unsigned int, unsigned int);
void pl011_set_irq_mask(unsigned int);
void pl011_clr_irq_mask(unsigned int);
void pl011_irq_handler(struct pl011_uart *);
void pl011_tx_irq_handler(struct pl011_uart *, unsigned int);
void pl011_rx_irq_handler(struct pl011_uart *, unsigned int);
void pl011_error_irq_handler(struct pl011_uart *, unsigned int);
static inline void pl011_uart_enable(void);
static inline void pl011_uart_disable(void);
static inline void pl011_tx_enable(void);
static inline void pl011_tx_disable(void);
static inline void pl011_rx_enable(void);
static inline void pl011_rx_disable(void);
static inline void pl011_irq_clear(unsigned int flags);
static inline unsigned int pl011_read_irqstat(void);
static inline unsigned int pl011_read_irqmask(void);
static inline void pl011_rx_dma_disable(void);
static inline void pl011_rx_dma_enable(void);
static inline void pl011_tx_dma_enable(void);
static inline void pl011_tx_dma_disable(void);
static inline void pl011_set_irq_fifolevel(unsigned int xfer,
unsigned int level);
static inline void pl011_set_word_width(int size);
static inline void pl011_disable_fifos(void);
static inline void pl011_set_parity_even(void);
static inline void pl011_parity_enable(void);
static inline void pl011_set_stopbits(int stopbits);
static inline void pl011_set_parity_odd(void);
static inline void pl011_enable_fifos(void);
static inline void pl011_parity_disable(void);
struct pl011_uart_ops {
int (*initialise)(struct pl011_uart *);
int (*tx_char)(char);
int (*rx_char)(char *);
void (*set_baudrate)(unsigned int, unsigned int);
void (*set_irq_mask)(unsigned int);
void (*clr_irq_mask)(unsigned int);
void (*irq_handler)(struct pl011_uart *);
void (*tx_irq_handler)(struct pl011_uart *, unsigned int);
void (*rx_irq_handler)(struct pl011_uart *, unsigned int);
void (*error_irq_handler)(struct pl011_uart *, unsigned int);
};
struct pl011_uart {
const unsigned int base;
struct pl011_uart_ops ops;
unsigned int frame_errors;
unsigned int parity_errors;
unsigned int break_errors;
unsigned int overrun_errors;
unsigned int rx_timeout_errors;
};
#define PL011_UARTEN (1 << 0)
static inline void pl011_uart_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val |= PL011_UARTEN;
write(val, PL011_UARTCR);
return;
}
static inline void pl011_uart_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val &= ~PL011_UARTEN;
write(val, PL011_UARTCR);
return;
}
#define PL011_TXE (1 << 8)
static inline void pl011_tx_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val |= PL011_TXE;
write(val, PL011_UARTCR);
return;
}
static inline void pl011_tx_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val &= ~PL011_TXE;
write(val, PL011_UARTCR);
return;
}
#define PL011_RXE (1 << 9)
static inline void pl011_rx_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val |= PL011_RXE;
write(val, PL011_UARTCR);
return;
}
static inline void pl011_rx_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
val &= ~PL011_RXE;
write(val, PL011_UARTCR);
return;
}
#define PL011_TWO_STOPBITS_SELECT (1 << 3)
static inline void pl011_set_stopbits(int stopbits)
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
if(stopbits == 2) { /* Set to two bits */
val |= PL011_TWO_STOPBITS_SELECT;
} else { /* Default is 1 */
val &= ~PL011_TWO_STOPBITS_SELECT;
}
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_PARITY_ENABLE (1 << 1)
static inline void pl011_parity_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val |= PL011_PARITY_ENABLE;
write(val, PL011_UARTLCR_H);
return;
}
static inline void pl011_parity_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val &= ~PL011_PARITY_ENABLE;
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_PARITY_EVEN (1 << 2)
static inline void pl011_set_parity_even()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val |= PL011_PARITY_EVEN;
write(val, PL011_UARTLCR_H);
return;
}
static inline void pl011_set_parity_odd()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val &= ~PL011_PARITY_EVEN;
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_ENABLE_FIFOS (1 << 4)
static inline void pl011_enable_fifos()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val |= PL011_ENABLE_FIFOS;
write(val, PL011_UARTLCR_H);
return;
}
static inline void pl011_disable_fifos()
{
unsigned int val;
val = 0;
read(val, PL011_UARTLCR_H);
val &= ~PL011_ENABLE_FIFOS;
write(val, PL011_UARTLCR_H);
return;
}
#define PL011_WORD_WIDTH_SHIFT (5)
/* Sets the transfer word width for the data register. */
static inline void pl011_set_word_width(int size)
{
unsigned int val;
val = 0;
if(size < 5 || size > 8) /* Default is 8 */
size = 8;
/* Clear size field */
read(val, PL011_UARTLCR_H);
val &= ~(0x3 << PL011_WORD_WIDTH_SHIFT);
write(val, PL011_UARTLCR_H);
/* The formula is to write 5 less of size given:
* 11 = 8 bits
* 10 = 7 bits
* 01 = 6 bits
* 00 = 5 bits
*/
read(val, PL011_UARTLCR_H);
val |= (size - 5) << PL011_WORD_WIDTH_SHIFT;
write(val, PL011_UARTLCR_H);
return;
}
/*
* Defines at which level of fifo fullness an irq will be generated.
* @xfer: tx fifo = 0, rx fifo = 1
* @level: Generate irq if:
* 0 rxfifo >= 1/8 full txfifo <= 1/8 full
* 1 rxfifo >= 1/4 full txfifo <= 1/4 full
* 2 rxfifo >= 1/2 full txfifo <= 1/2 full
* 3 rxfifo >= 3/4 full txfifo <= 3/4 full
* 4 rxfifo >= 7/8 full txfifo <= 7/8 full
* 5-7 reserved reserved
*/
static inline void pl011_set_irq_fifolevel(unsigned int xfer, unsigned int level)
{
if(xfer != 1 && xfer != 0) /* Invalid fifo */
return;
if(level > 4) /* Invalid level */
return;
write(level << (xfer * 3), PL011_UARTIFLS);
return;
}
/* returns which irqs are masked */
static inline unsigned int pl011_read_irqmask(void)
{
unsigned int flags;
read(flags, PL011_UARTIMSC);
return flags;
}
/* returns masked irq status */
static inline unsigned int pl011_read_irqstat(void)
{
unsigned int irqstatus;
read(irqstatus, PL011_UARTMIS);
return irqstatus;
}
/* Clears the given asserted irqs */
static inline void pl011_irq_clear(unsigned int flags)
{
if(flags > 0x3FF) { /* Invalid irq clearing bitvector */
return;
}
/* Simply write the flags since it's a write-only register */
write(flags, PL011_UARTICR);
return;
}
#define PL011_TXDMAEN (1 << 1)
#define PL011_RXDMAEN (1 << 0)
/* Enables dma transfers for uart. The dma controller
* must be initialised, set-up and enabled separately.
*/
static inline void pl011_tx_dma_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val |= PL011_TXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
/* Disables dma transfers for uart */
static inline void pl011_tx_dma_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val &= ~PL011_TXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
static inline void pl011_rx_dma_enable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val |= PL011_RXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
static inline void pl011_rx_dma_disable()
{
unsigned int val;
val = 0;
read(val, PL011_UARTDMACR);
val &= ~PL011_RXDMAEN;
write(val, PL011_UARTDMACR);
return;
}
#endif /* __PL011__UART__ */

83
loader/libs/c/include/sys-userspace/arch-arm/setjmp.h
View File

@@ -1,83 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Author: Alex Webster
*/
typedef int jmp_buf[10];

92
loader/libs/c/include/sys-userspace/arch-arm/stdint.h
View File

@@ -1,92 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Author: Ben Leslie
*/
typedef signed char int8_t;
typedef short int16_t;
typedef int int32_t;
typedef long long int64_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef unsigned long long uint64_t;
#define __PTR_SIZE 32

130
loader/libs/c/include/time.h
View File

@@ -1,130 +0,0 @@
/*
* Australian Public Licence B (OZPLB)
*
* Version 1-0
*
* Copyright (c) 2004 National ICT Australia
*
* All rights reserved.
*
* Developed by: Embedded, Real-time and Operating Systems Program (ERTOS)
* National ICT Australia
* http://www.ertos.nicta.com.au
*
* Permission is granted by National ICT Australia, free of charge, to
* any person obtaining a copy of this software and any associated
* documentation files (the "Software") to deal with the Software without
* restriction, including (without limitation) the rights to use, copy,
* modify, adapt, merge, publish, distribute, communicate to the public,
* sublicense, and/or sell, lend or rent out copies of the Software, and
* to permit persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimers.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimers in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of National ICT Australia, nor the names of its
* contributors, may be used to endorse or promote products derived
* from this Software without specific prior written permission.
*
* EXCEPT AS EXPRESSLY STATED IN THIS LICENCE AND TO THE FULL EXTENT
* PERMITTED BY APPLICABLE LAW, THE SOFTWARE IS PROVIDED "AS-IS", AND
* NATIONAL ICT AUSTRALIA AND ITS CONTRIBUTORS MAKE NO REPRESENTATIONS,
* WARRANTIES OR CONDITIONS OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO ANY REPRESENTATIONS, WARRANTIES OR CONDITIONS
* REGARDING THE CONTENTS OR ACCURACY OF THE SOFTWARE, OR OF TITLE,
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT,
* THE ABSENCE OF LATENT OR OTHER DEFECTS, OR THE PRESENCE OR ABSENCE OF
* ERRORS, WHETHER OR NOT DISCOVERABLE.
*
* TO THE FULL EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL
* NATIONAL ICT AUSTRALIA OR ITS CONTRIBUTORS BE LIABLE ON ANY LEGAL
* THEORY (INCLUDING, WITHOUT LIMITATION, IN AN ACTION OF CONTRACT,
* NEGLIGENCE OR OTHERWISE) FOR ANY CLAIM, LOSS, DAMAGES OR OTHER
* LIABILITY, INCLUDING (WITHOUT LIMITATION) LOSS OF PRODUCTION OR
* OPERATION TIME, LOSS, DAMAGE OR CORRUPTION OF DATA OR RECORDS; OR LOSS
* OF ANTICIPATED SAVINGS, OPPORTUNITY, REVENUE, PROFIT OR GOODWILL, OR
* OTHER ECONOMIC LOSS; OR ANY SPECIAL, INCIDENTAL, INDIRECT,
* CONSEQUENTIAL, PUNITIVE OR EXEMPLARY DAMAGES, ARISING OUT OF OR IN
* CONNECTION WITH THIS LICENCE, THE SOFTWARE OR THE USE OF OR OTHER
* DEALINGS WITH THE SOFTWARE, EVEN IF NATIONAL ICT AUSTRALIA OR ITS
* CONTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH CLAIM, LOSS,
* DAMAGES OR OTHER LIABILITY.
*
* If applicable legislation implies representations, warranties, or
* conditions, or imposes obligations or liability on National ICT
* Australia or one of its contributors in respect of the Software that
* cannot be wholly or partly excluded, restricted or modified, the
* liability of National ICT Australia or the contributor is limited, to
* the full extent permitted by the applicable legislation, at its
* option, to:
* a. in the case of goods, any one or more of the following:
* i. the replacement of the goods or the supply of equivalent goods;
* ii. the repair of the goods;
* iii. the payment of the cost of replacing the goods or of acquiring
* equivalent goods;
* iv. the payment of the cost of having the goods repaired; or
* b. in the case of services:
* i. the supplying of the services again; or
* ii. the payment of the cost of having the services supplied again.
*
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
/*
Author: Ben Leslie
Created: Fri Sep 24 2004
Description: time.h as per ISOC99
*/
#ifndef _TIME_H_
#define _TIME_H_
#include <stddef.h> /* For NULL, size_t */
#define CLOCKS_PER_SEC 1 /* Arbitrary, 1s resolution */
typedef long clock_t;
typedef long time_t;
struct tm {
int tm_sec;
int tm_min;
int tm_hour;
int tm_mday;
int tm_mon;
int tm_year;
int tm_wday;
int tm_yday;
int tm_isdst;
};
/* 7.23.2 Time manipulation functions */
clock_t clock(void);
double difftime(time_t time1, time_t time2);
time_t mktime(struct tm *timeptr);
time_t time(time_t *timer);
/* 7.23.3 Time conversion functions */
char *asctime(const struct tm *timeptr);
struct tm *gmtime(const time_t *timer);
struct tm *localtime(const time_t *timer);
/* As per spec pg. 341 */
static inline
char *ctime(const time_t *timer)
{
return asctime(localtime(timer));
}
size_t strftime(char *s, size_t maxsize, const char *format,
const struct tm *timeptr);
#endif /* _TIME_H_ */