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Cleaned the libc uart driver

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This commit is contained in:
Amit Mahajan
2009-10-28 20:27:24 +05:30
parent 5b3d11ed55
commit b8829118e0
3 changed files with 253 additions and 365 deletions
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43
conts/libc/src/sys-userspace/arch-arm/plat-pb926/platform_init.c
View File

@@ -1,50 +1,53 @@
#include <arch/pl011_uart.h>
/* TODO: May need to remove this */
struct pl011_uart uart;
void platform_init(void);
void platform_init(void)
{
uart.base = PL011_USR_BASE;
pl011_initialise(&uart);
}
/* Initialises the uart class data structures, and the device.
* Terminal-like operation is assumed for default settings.
/*
* Initialises the uart class data structures, and the device.
* Terminal-like operation is assumed for default settings.
*/
int pl011_initialise(struct pl011_uart * uart)
{
uart->frame_errors = 0;
uart->parity_errors = 0;
uart->break_errors = 0;
uart->overrun_errors = 0;
/* Initialise data register for 8 bit data read/writes */
pl011_set_word_width(8);
/* Fifos are disabled because by default it is assumed the port
* will be used as a user terminal, and in that case the typed
pl011_set_word_width(uart->base, 8);
/*
* Fifos are disabled because by default it is assumed the port
* will be used as a user terminal, and in that case the typed
* characters will only show up when fifos are flushed, rather than
* when each character is typed. We avoid this by not using fifos.
*/
pl011_disable_fifos();
pl011_disable_fifos(uart->base);
/* Set default baud rate of 38400 */
pl011_set_baudrate(38400, 24000000);
pl011_set_baudrate(uart->base, 38400, 24000000);
/* Set default settings of 1 stop bit, no parity, no hw flow ctrl */
pl011_set_stopbits(1);
pl011_parity_disable();
pl011_set_stopbits(uart->base, 1);
pl011_parity_disable(uart->base);
/* Disable all irqs */
pl011_set_irq_mask(0x3FF);
pl011_set_irq_mask(uart->base, 0x3FF);
/* Enable rx, tx, and uart chip */
pl011_tx_enable();
pl011_rx_enable();
pl011_uart_enable();
pl011_tx_enable(uart->base);
pl011_rx_enable(uart->base);
pl011_uart_enable(uart->base);
return 0;
}

174
conts/libc/src/sys-userspace/arch-arm/plat-pb926/sys_fputc.c
View File

@@ -76,86 +76,11 @@
* The construction, validity and performance of this licence is governed
* by the laws in force in New South Wales, Australia.
*/
#define MACHINE_PB926
#include <stdio.h>
#include <stdint.h>
#include <arch/pl011_uart.h>
//#define iPAQ /* FIXME: this is ugly */
//#undef XSCALE
//#define XSCALE
// #undef iPAQ
// #define XSCALE
extern int __fputc(int c, FILE *stream);
/* Put character for elf-loader */
int
__fputc(int c, FILE *stream)
{
/* ---------------------------------- iPAQ & PLEB1 (SA-1100)--------------------------- */
#ifdef MACHINE_IPAQ_H3800 //iPAQ // SA-1100
volatile char *base = (char *)0x80050000; // base serial interface address
/* volatile int *base2 = (int *)0x80030000; // the other serial Arm serial i/f */
/*
UTSR1 32 @ 0x20:
tby <0> # Transmitter busy
rne <1> # Refeive FIFO not empty
tnf <2> # Transmitter not full
pre <3> # Parity error
fre <4> # Framing error
ror <5> # Receive FIFO overrun
*/
#define UTDR 0x14 // data register
#define UTSR1 0x20 // status register 1 offset
#define UTSR1_TNF (1 << 2) // tx FIFO not full (status bit)
while ( ! ( * ( (volatile long *) (base + UTSR1)) & UTSR1_TNF ))
; // busy wait while TX FIFO is full
*(volatile unsigned char *) (base + UTDR) = c;
// *base2 = c;
#endif
/* ---------------------------------- PLEB2 (XSCALE PXA-255) --------------------------- */
#ifdef MACHINE_PLEB2 //XSCALE /* PXA 255 on PLEB2 */
/* Console port -- taken from kernel/include/platform/pleb2/console.h */
#define CONSOLE_OFFSET 0x100000
/* IO Base -- taken from kernel/include/arch/arm/xscale/cpu.h */
#define XSCALE_PXA255_IO_BASE 0x40000000
#define DATAR 0x00000000
#define STATUSR 0x00000014
/* TX empty bit -- uboot/include/asm/arch/hardware.h */
#define LSR_TEMT (1 << 6) /* Transmitter Empty */
volatile char *base = (char *) (XSCALE_PXA255_IO_BASE + CONSOLE_OFFSET);
/* wait for room in the tx FIFO on FFUART */
while ( ! ( * ( (volatile long *) (base + STATUSR)) & LSR_TEMT ))
; // busy wait while TX FIFO is full
*(volatile unsigned char *) (base + DATAR) = c;
#endif /* XSCALE */
#ifdef MACHINE_PB926
{
int res;
do {
res = pl011_tx_char(c);
} while( res < 0);
}
#endif /* MACHINE_PB926 */
return(0);
}
/* --------------------------------- PB926 UART Driver -------------------------------- */
#ifdef MACHINE_PB926
extern struct pl011_uart uart;
/* UART-specific internal error codes */
@@ -178,56 +103,47 @@ extern struct pl011_uart uart;
#define PL011_DSR (1 << 1)
#define PL011_CTS (1 << 0)
int pl011_tx_char(char c)
int pl011_tx_char(unsigned int base, char c)
{
unsigned int val;
val = 0;
read(val, PL011_UARTFR);
unsigned int val = 0;
read(val, (base + PL011_UARTFR));
if(val & PL011_TXFF) { /* TX FIFO Full */
return -PL011_EAGAIN;
}
write(c, PL011_UARTDR);
write(c, (base + PL011_UARTDR));
return 0;
}
int pl011_rx_char(char * c)
int pl011_rx_char(unsigned int base, char * c)
{
unsigned int data;
unsigned int val;
val = 0;
read(val, PL011_UARTFR);
unsigned int val = 0;
read(val, (base + PL011_UARTFR));
if(val & PL011_RXFE) { /* RX FIFO Empty */
return -PL011_EAGAIN;
}
read(data, PL011_UARTDR);
read(data, (base + PL011_UARTDR));
*c = (char) data;
if((data >> 8) & 0xF) { /* There were errors */
return -1; /* Signal error in xfer */
}
return 0; /* No error return */
}
/*
* Sets the baud rate in kbps. It is recommended to use
* standard rates such as: 1200, 2400, 3600, 4800, 7200,
/*
* Sets the baud rate in kbps. It is recommended to use
* standard rates such as: 1200, 2400, 3600, 4800, 7200,
* 9600, 14400, 19200, 28800, 38400, 57600 76800, 115200.
*/
void pl011_set_baudrate(unsigned int baud, unsigned int clkrate)
void pl011_set_baudrate(unsigned int base, unsigned int baud,
unsigned int clkrate)
{
const unsigned int uartclk = 24000000; /* 24Mhz clock fixed on pb926 */
unsigned int val;
unsigned int ipart, fpart;
unsigned int remainder;
remainder = 0;
ipart = 0;
fpart = 0;
val = 0;
unsigned int val = 0, ipart = 0, fpart = 0;
/* Use default pb926 rate if no rate is supplied */
if(clkrate == 0) {
@@ -239,52 +155,58 @@ void pl011_set_baudrate(unsigned int baud, unsigned int clkrate)
/* 24000000 / (38400 * 16) */
ipart = 39;
write(ipart, PL011_UARTIBRD);
write(fpart, PL011_UARTFBRD);
write(ipart, (base + PL011_UARTIBRD));
write(fpart, (base + PL011_UARTFBRD));
/* For the IBAUD and FBAUD to update, we need to
/*
* For the IBAUD and FBAUD to update, we need to
* write to UARTLCR_H because the 3 registers are
* actually part of a single register in hardware
* which only updates by a write to UARTLCR_H */
read(val, PL011_UARTLCR_H);
write(val, PL011_UARTLCR_H);
* which only updates by a write to UARTLCR_H
*/
read(val, (base + PL011_UARTLCR_H));
write(val, (base + PL011_UARTLCR_H));
return;
}
/* Masks the irqs given in the flags bitvector. */
void pl011_set_irq_mask(unsigned int flags)
void pl011_set_irq_mask(unsigned int base, unsigned int flags)
{
unsigned int val;
val = 0;
unsigned int val = 0;
if(flags > 0x3FF) { /* Invalid irqmask bitvector */
return;
}
read(val, PL011_UARTIMSC);
read(val, (base + PL011_UARTIMSC));
val |= flags;
write(val, PL011_UARTIMSC);
write(val, (base + PL011_UARTIMSC));
return;
}
/* Clears the irqs given in flags from masking */
void pl011_clr_irq_mask(unsigned int flags)
void pl011_clr_irq_mask(unsigned int base, unsigned int flags)
{
unsigned int val;
val = 0;
if(flags > 0x3FF) { /* Invalid irqmask bitvector */
unsigned int val = 0;
if(flags > 0x3FF) {
/* Invalid irqmask bitvector */
return;
}
read(val, PL011_UARTIMSC);
read(val, (base + PL011_UARTIMSC));
val &= ~flags;
write(val, PL011_UARTIMSC);
write(val, (base + PL011_UARTIMSC));
return;
}
int __fputc(int c, FILE *stream)
{
int res;
do {
res = pl011_tx_char(uart.base, c);
} while( res < 0);
#endif
return(0);
}