Added new subarch, platform, cpu, driver variants for configuration testing.

New files are an exact copy of pb926 files, but will help in testing different
configurations and compilations.

include/l4/arch/arm/v6/arm1136/cpu.h

@@ -0,0 +1,13 @@
+/*
+ *
+ * Copyright (C) 2005 Bahadir Balban
+ *
+ */
+#ifndef __ARM926EJS__H__
+#define __ARM926EJS__H__
+
+
+
+
+
+#endif /* __ARM926EJS__H__ */

include/l4/arch/arm/v6/arm11mpcore/cpu.h

@@ -0,0 +1,13 @@
+/*
+ *
+ * Copyright (C) 2005 Bahadir Balban
+ *
+ */
+#ifndef __ARM926EJS__H__
+#define __ARM926EJS__H__
+
+
+
+
+
+#endif /* __ARM926EJS__H__ */

include/l4/arch/arm/v6/mm.h

@@ -0,0 +1,160 @@
+/*
+ * ARM v5-specific virtual memory details
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ */
+#ifndef __V5_MM_H__
+#define __V5_MM_H__
+
+/* ARM specific definitions */
+#define VIRT_MEM_START			0
+#define VIRT_MEM_END			0xFFFFFFFF
+#define ARM_SECTION_SIZE		SZ_1MB
+#define ARM_SECTION_MASK		(ARM_SECTION_SIZE - 1)
+#define ARM_SECTION_BITS		20
+#define ARM_PAGE_SIZE			SZ_4K
+#define ARM_PAGE_MASK			0xFFF
+#define ARM_PAGE_BITS			12
+
+#define	PGD_SIZE				SZ_4K * 4
+#define PGD_ENTRY_TOTAL				SZ_4K
+#define	PGD_TYPE_MASK				0x3
+#define	PGD_COARSE_ALIGN_MASK			0xFFFFFC00
+#define	PGD_SECTION_ALIGN_MASK			0xFFF00000
+#define	PGD_FINE_ALIGN_MASK			0xFFFFF000
+#define	PGD_TYPE_FAULT				0
+#define	PGD_TYPE_COARSE				1
+#define	PGD_TYPE_SECTION			2
+#define	PGD_TYPE_FINE				3
+
+#define PMD_TYPE_MASK				0x3
+#define PMD_TYPE_FAULT				0
+#define PMD_TYPE_LARGE				1
+#define PMD_TYPE_SMALL				2
+#define PMD_TYPE_TINY				3
+
+/* Permission field offsets */
+#define SECTION_AP0				10
+
+#define PMD_SIZE				SZ_1K
+#define PMD_ENTRY_TOTAL				256
+#define PMD_MAP_SIZE				SZ_1MB
+
+/* Type-checkable page table elements */
+typedef u32 pgd_t;
+typedef u32 pmd_t;
+typedef u32 pte_t;
+
+/* Page global directory made up of pgd_t entries */
+typedef struct pgd_table {
+	pgd_t entry[PGD_ENTRY_TOTAL];
+} pgd_table_t;
+
+/* Page middle directory made up of pmd_t entries */
+typedef struct pmd_table {
+	pmd_t entry[PMD_ENTRY_TOTAL];
+} pmd_table_t;
+
+/* Applies for both small and large pages */
+#define PAGE_AP0				4
+#define PAGE_AP1				6
+#define	PAGE_AP2				8
+#define PAGE_AP3				10
+
+/* Permission values with rom and sys bits ignored */
+#define SVC_RW_USR_NONE				1
+#define SVC_RW_USR_RO				2
+#define SVC_RW_USR_RW				3
+
+#define PTE_PROT_MASK				(0xFF << 4)
+
+#define CACHEABILITY				3
+#define BUFFERABILITY				2
+#define cacheable				(1 << CACHEABILITY)
+#define bufferable				(1 << BUFFERABILITY)
+#define uncacheable				0
+#define unbufferable				0
+
+/* Helper macros for common cases */
+#define __MAP_USR_RW_FLAGS	(cacheable | bufferable | (SVC_RW_USR_RW << PAGE_AP0)		\
+				| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2)	\
+				| (SVC_RW_USR_RW << PAGE_AP3))
+#define __MAP_USR_RO_FLAGS	(cacheable | bufferable | (SVC_RW_USR_RO << PAGE_AP0)		\
+				| (SVC_RW_USR_RO << PAGE_AP1) | (SVC_RW_USR_RO << PAGE_AP2)	\
+				| (SVC_RW_USR_RO << PAGE_AP3))
+#define __MAP_SVC_RW_FLAGS	(cacheable | bufferable | (SVC_RW_USR_NONE << PAGE_AP0) 	\
+				| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2)	\
+				| (SVC_RW_USR_NONE << PAGE_AP3))
+#define __MAP_SVC_IO_FLAGS	(uncacheable | unbufferable | (SVC_RW_USR_NONE << PAGE_AP0)	\
+				| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2)	\
+				| (SVC_RW_USR_NONE << PAGE_AP3))
+#define __MAP_USR_IO_FLAGS	(uncacheable | unbufferable | (SVC_RW_USR_RW << PAGE_AP0)	\
+				| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2)	\
+				| (SVC_RW_USR_RW << PAGE_AP3))
+
+/* Abort information */
+
+/*FIXME: Carry all these definitions to an abort.h, Also carry all abort code to abort.c. Much neater!!! */
+
+/* Abort type */
+#define ARM_PABT		1
+#define ARM_DABT		0
+/* The kernel makes use of bit 8 (Always Zero) of FSR to define which type of abort */
+#define set_abort_type(fsr, x)	{ fsr &= ~(1 << 8); fsr |= ((x & 1) << 8); }
+#define ARM_FSR_MASK		0xF
+#define is_prefetch_abort(fsr)	((fsr >> 8) & 0x1)
+#define is_data_abort(fsr)	(!is_prefetch_abort(fsr))
+
+/*
+ * v5 Architecture-defined data abort values for FSR ordered
+ * in highest to lowest priority.
+ */
+#define DABT_TERMINAL				0x2
+#define DABT_VECTOR				0x0	/* Obsolete */
+#define DABT_ALIGN				0x1
+#define DABT_EXT_XLATE_LEVEL1			0xC
+#define DABT_EXT_XLATE_LEVEL2			0xE
+#define DABT_XLATE_SECT				0x5
+#define DABT_XLATE_PAGE				0x7
+#define DABT_DOMAIN_SECT			0x9
+#define DABT_DOMAIN_PAGE			0xB
+#define DABT_PERM_SECT				0xD
+#define DABT_PERM_PAGE				0xF
+#define DABT_EXT_LFETCH_SECT			0x4
+#define DABT_EXT_LFETCH_PAGE			0x6
+#define DABT_EXT_NON_LFETCH_SECT		0x8
+#define DABT_EXT_NON_LFETCH_PAGE		0xA
+
+#define TASK_PGD(x)		(x)->space->pgd
+
+#define STACK_ALIGNMENT				8
+
+/* Kernel's data about the fault */
+typedef struct fault_kdata {
+	u32 faulty_pc;
+	u32 fsr;
+	u32 far;
+	pte_t pte;
+} __attribute__ ((__packed__)) fault_kdata_t;
+
+void arch_hardware_flush(pgd_table_t *pgd);
+void add_section_mapping_init(unsigned int paddr, unsigned int vaddr,
+			      unsigned int size, unsigned int flags);
+
+void add_boot_mapping(unsigned int paddr, unsigned int vaddr,
+		      unsigned int size, unsigned int flags);
+
+struct address_space;
+int delete_page_tables(struct address_space *space);
+int copy_user_tables(struct address_space *new, struct address_space *orig);
+pgd_table_t *copy_page_tables(pgd_table_t *from);
+void remap_as_pages(void *vstart, void *vend);
+
+int pgd_count_pmds(pgd_table_t *pgd);
+pgd_table_t *realloc_page_tables(void);
+void remove_section_mapping(unsigned long vaddr);
+
+void copy_pgds_by_vrange(pgd_table_t *to, pgd_table_t *from,
+			 unsigned long start, unsigned long end);
+
+#endif /* __V5_MM_H__ */

include/l4/arch/arm/v6/mmu_ops.h

@@ -0,0 +1,34 @@
+#ifndef __MMU__OPS__H__
+#define __MMU__OPS__H__
+/*
+ * Prototypes for low level mmu operations
+ *
+ * Copyright (C) 2005 Bahadir Balban
+ *
+ */
+
+void arm_set_ttb(unsigned int);
+void arm_set_domain(unsigned int);
+unsigned int arm_get_domain(void);
+void arm_enable_mmu(void);
+void arm_enable_icache(void);
+void arm_enable_dcache(void);
+void arm_enable_wbuffer(void);
+void arm_enable_high_vectors(void);
+void arm_invalidate_cache(void);
+void arm_invalidate_icache(void);
+void arm_invalidate_dcache(void);
+void arm_clean_invalidate_dcache(void);
+void arm_clean_invalidate_cache(void);
+void arm_drain_writebuffer(void);
+void arm_invalidate_tlb(void);
+void arm_invalidate_itlb(void);
+void arm_invalidate_dtlb(void);
+
+static inline void arm_enable_caches(void)
+{
+	arm_enable_icache();
+	arm_enable_dcache();
+}
+
+#endif /* __MMU__OPS__H__ */

include/l4/arch/arm/v7/cortexa8/cpu.h

@@ -0,0 +1,13 @@
+/*
+ *
+ * Copyright (C) 2005 Bahadir Balban
+ *
+ */
+#ifndef __ARM926EJS__H__
+#define __ARM926EJS__H__
+
+
+
+
+
+#endif /* __ARM926EJS__H__ */

include/l4/arch/arm/v7/mm.h

@@ -0,0 +1,160 @@
+/*
+ * ARM v5-specific virtual memory details
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ */
+#ifndef __V5_MM_H__
+#define __V5_MM_H__
+
+/* ARM specific definitions */
+#define VIRT_MEM_START			0
+#define VIRT_MEM_END			0xFFFFFFFF
+#define ARM_SECTION_SIZE		SZ_1MB
+#define ARM_SECTION_MASK		(ARM_SECTION_SIZE - 1)
+#define ARM_SECTION_BITS		20
+#define ARM_PAGE_SIZE			SZ_4K
+#define ARM_PAGE_MASK			0xFFF
+#define ARM_PAGE_BITS			12
+
+#define	PGD_SIZE				SZ_4K * 4
+#define PGD_ENTRY_TOTAL				SZ_4K
+#define	PGD_TYPE_MASK				0x3
+#define	PGD_COARSE_ALIGN_MASK			0xFFFFFC00
+#define	PGD_SECTION_ALIGN_MASK			0xFFF00000
+#define	PGD_FINE_ALIGN_MASK			0xFFFFF000
+#define	PGD_TYPE_FAULT				0
+#define	PGD_TYPE_COARSE				1
+#define	PGD_TYPE_SECTION			2
+#define	PGD_TYPE_FINE				3
+
+#define PMD_TYPE_MASK				0x3
+#define PMD_TYPE_FAULT				0
+#define PMD_TYPE_LARGE				1
+#define PMD_TYPE_SMALL				2
+#define PMD_TYPE_TINY				3
+
+/* Permission field offsets */
+#define SECTION_AP0				10
+
+#define PMD_SIZE				SZ_1K
+#define PMD_ENTRY_TOTAL				256
+#define PMD_MAP_SIZE				SZ_1MB
+
+/* Type-checkable page table elements */
+typedef u32 pgd_t;
+typedef u32 pmd_t;
+typedef u32 pte_t;
+
+/* Page global directory made up of pgd_t entries */
+typedef struct pgd_table {
+	pgd_t entry[PGD_ENTRY_TOTAL];
+} pgd_table_t;
+
+/* Page middle directory made up of pmd_t entries */
+typedef struct pmd_table {
+	pmd_t entry[PMD_ENTRY_TOTAL];
+} pmd_table_t;
+
+/* Applies for both small and large pages */
+#define PAGE_AP0				4
+#define PAGE_AP1				6
+#define	PAGE_AP2				8
+#define PAGE_AP3				10
+
+/* Permission values with rom and sys bits ignored */
+#define SVC_RW_USR_NONE				1
+#define SVC_RW_USR_RO				2
+#define SVC_RW_USR_RW				3
+
+#define PTE_PROT_MASK				(0xFF << 4)
+
+#define CACHEABILITY				3
+#define BUFFERABILITY				2
+#define cacheable				(1 << CACHEABILITY)
+#define bufferable				(1 << BUFFERABILITY)
+#define uncacheable				0
+#define unbufferable				0
+
+/* Helper macros for common cases */
+#define __MAP_USR_RW_FLAGS	(cacheable | bufferable | (SVC_RW_USR_RW << PAGE_AP0)		\
+				| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2)	\
+				| (SVC_RW_USR_RW << PAGE_AP3))
+#define __MAP_USR_RO_FLAGS	(cacheable | bufferable | (SVC_RW_USR_RO << PAGE_AP0)		\
+				| (SVC_RW_USR_RO << PAGE_AP1) | (SVC_RW_USR_RO << PAGE_AP2)	\
+				| (SVC_RW_USR_RO << PAGE_AP3))
+#define __MAP_SVC_RW_FLAGS	(cacheable | bufferable | (SVC_RW_USR_NONE << PAGE_AP0) 	\
+				| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2)	\
+				| (SVC_RW_USR_NONE << PAGE_AP3))
+#define __MAP_SVC_IO_FLAGS	(uncacheable | unbufferable | (SVC_RW_USR_NONE << PAGE_AP0)	\
+				| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2)	\
+				| (SVC_RW_USR_NONE << PAGE_AP3))
+#define __MAP_USR_IO_FLAGS	(uncacheable | unbufferable | (SVC_RW_USR_RW << PAGE_AP0)	\
+				| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2)	\
+				| (SVC_RW_USR_RW << PAGE_AP3))
+
+/* Abort information */
+
+/*FIXME: Carry all these definitions to an abort.h, Also carry all abort code to abort.c. Much neater!!! */
+
+/* Abort type */
+#define ARM_PABT		1
+#define ARM_DABT		0
+/* The kernel makes use of bit 8 (Always Zero) of FSR to define which type of abort */
+#define set_abort_type(fsr, x)	{ fsr &= ~(1 << 8); fsr |= ((x & 1) << 8); }
+#define ARM_FSR_MASK		0xF
+#define is_prefetch_abort(fsr)	((fsr >> 8) & 0x1)
+#define is_data_abort(fsr)	(!is_prefetch_abort(fsr))
+
+/*
+ * v5 Architecture-defined data abort values for FSR ordered
+ * in highest to lowest priority.
+ */
+#define DABT_TERMINAL				0x2
+#define DABT_VECTOR				0x0	/* Obsolete */
+#define DABT_ALIGN				0x1
+#define DABT_EXT_XLATE_LEVEL1			0xC
+#define DABT_EXT_XLATE_LEVEL2			0xE
+#define DABT_XLATE_SECT				0x5
+#define DABT_XLATE_PAGE				0x7
+#define DABT_DOMAIN_SECT			0x9
+#define DABT_DOMAIN_PAGE			0xB
+#define DABT_PERM_SECT				0xD
+#define DABT_PERM_PAGE				0xF
+#define DABT_EXT_LFETCH_SECT			0x4
+#define DABT_EXT_LFETCH_PAGE			0x6
+#define DABT_EXT_NON_LFETCH_SECT		0x8
+#define DABT_EXT_NON_LFETCH_PAGE		0xA
+
+#define TASK_PGD(x)		(x)->space->pgd
+
+#define STACK_ALIGNMENT				8
+
+/* Kernel's data about the fault */
+typedef struct fault_kdata {
+	u32 faulty_pc;
+	u32 fsr;
+	u32 far;
+	pte_t pte;
+} __attribute__ ((__packed__)) fault_kdata_t;
+
+void arch_hardware_flush(pgd_table_t *pgd);
+void add_section_mapping_init(unsigned int paddr, unsigned int vaddr,
+			      unsigned int size, unsigned int flags);
+
+void add_boot_mapping(unsigned int paddr, unsigned int vaddr,
+		      unsigned int size, unsigned int flags);
+
+struct address_space;
+int delete_page_tables(struct address_space *space);
+int copy_user_tables(struct address_space *new, struct address_space *orig);
+pgd_table_t *copy_page_tables(pgd_table_t *from);
+void remap_as_pages(void *vstart, void *vend);
+
+int pgd_count_pmds(pgd_table_t *pgd);
+pgd_table_t *realloc_page_tables(void);
+void remove_section_mapping(unsigned long vaddr);
+
+void copy_pgds_by_vrange(pgd_table_t *to, pgd_table_t *from,
+			 unsigned long start, unsigned long end);
+
+#endif /* __V5_MM_H__ */

include/l4/arch/arm/v7/mmu_ops.h

@@ -0,0 +1,34 @@
+#ifndef __MMU__OPS__H__
+#define __MMU__OPS__H__
+/*
+ * Prototypes for low level mmu operations
+ *
+ * Copyright (C) 2005 Bahadir Balban
+ *
+ */
+
+void arm_set_ttb(unsigned int);
+void arm_set_domain(unsigned int);
+unsigned int arm_get_domain(void);
+void arm_enable_mmu(void);
+void arm_enable_icache(void);
+void arm_enable_dcache(void);
+void arm_enable_wbuffer(void);
+void arm_enable_high_vectors(void);
+void arm_invalidate_cache(void);
+void arm_invalidate_icache(void);
+void arm_invalidate_dcache(void);
+void arm_clean_invalidate_dcache(void);
+void arm_clean_invalidate_cache(void);
+void arm_drain_writebuffer(void);
+void arm_invalidate_tlb(void);
+void arm_invalidate_itlb(void);
+void arm_invalidate_dtlb(void);
+
+static inline void arm_enable_caches(void)
+{
+	arm_enable_icache();
+	arm_enable_dcache();
+}
+
+#endif /* __MMU__OPS__H__ */

include/l4/drivers/irq/gic.h

@@ -1,13 +0,0 @@
-/*
- *
- * Copyright (C) 2007 Bahadir Balban
- *
- */
-#ifndef __GIC_H__
-#define __GIC_H__
-
-
-
-
-
-#endif /* __GIC_H__ */

include/l4/drivers/irq/gic/gic.h

@@ -0,0 +1,56 @@
+/*
+ * PL190 Primecell Vectored Interrupt Controller offsets
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ *
+ */
+
+#ifndef __PL190_VIC_H__
+#define __PL190_VIC_H__
+
+#include INC_PLAT(platform.h)
+
+#define PL190_BASE				PLATFORM_IRQCTRL_BASE
+#define PL190_SIC_BASE				PLATFORM_SIRQCTRL_BASE
+
+/* VIC register offsets */
+#define PL190_VIC_IRQSTATUS			(PL190_BASE + 0x00)
+#define PL190_VIC_FIQSTATUS			(PL190_BASE + 0x04)
+#define PL190_VIC_RAWINTR			(PL190_BASE + 0x08)
+#define PL190_VIC_INTSELECT			(PL190_BASE + 0x0C)
+#define PL190_VIC_INTENABLE			(PL190_BASE + 0x10)
+#define PL190_VIC_INTENCLEAR			(PL190_BASE + 0x14)
+#define PL190_VIC_SOFTINT			(PL190_BASE + 0x18)
+#define PL190_VIC_SOFTINTCLEAR			(PL190_BASE + 0x1C)
+#define PL190_VIC_PROTECTION			(PL190_BASE + 0x20)
+#define PL190_VIC_VECTADDR			(PL190_BASE + 0x30)
+#define PL190_VIC_DEFVECTADDR			(PL190_BASE + 0x34)
+#define PL190_VIC_VECTADDR0			(PL190_BASE + 0x100)
+/* 15 PIC_VECTADDR registers up to	0x13C */
+#define PL190_VIC_VECTCNTL0			(PL190_BASE + 0x200)
+/* 15 PIC_VECTCNTL registers up to	0x23C */
+
+#define PL190_SIC_STATUS			(PL190_SIC_BASE + 0x0)
+#define PL190_SIC_RAWSTAT			(PL190_SIC_BASE + 0x04)
+#define PL190_SIC_ENABLE			(PL190_SIC_BASE + 0x08)
+#define PL190_SIC_ENSET				(PL190_SIC_BASE + 0x08)
+#define PL190_SIC_ENCLR				(PL190_SIC_BASE + 0x0C)
+#define PL190_SIC_SOFTINTSET			(PL190_SIC_BASE + 0x10)
+#define PL190_SIC_SOFTINTCLR			(PL190_SIC_BASE + 0x14)
+#define PL190_SIC_PICENABLE			(PL190_SIC_BASE + 0x20)
+#define PL190_SIC_PICENSET			(PL190_SIC_BASE + 0x20)
+#define PL190_SIC_PICENCLR			(PL190_SIC_BASE + 0x24)
+
+void pl190_vic_init(void);
+void pl190_ack_irq(int irq);
+void pl190_mask_irq(int irq);
+void pl190_unmask_irq(int irq);
+int pl190_read_irq(void);
+
+int pl190_sic_read_irq(void);
+void pl190_sic_mask_irq(int irq);
+void pl190_sic_mask_irq(int irq);
+void pl190_sic_ack_irq(int irq);
+void pl190_sic_unmask_irq(int irq);
+void pl190_sic_init(void);
+#endif /* __PL190_VIC_H__ */

include/l4/platform/ab926/irq.h

@@ -0,0 +1,27 @@
+#ifndef __PLATFORM_IRQ_H__
+#define __PLATFORM_IRQ_H__
+
+#define IRQ_CHIPS_MAX				2
+#define IRQS_MAX				64
+
+/* IRQ indices. */
+#define IRQ_TIMER01			4
+#define IRQ_TIMER23			5
+#define IRQ_RTC				10
+#define IRQ_UART0			12
+#define IRQ_UART1			13
+#define IRQ_UART2			14
+#define IRQ_SIC				31
+
+/* Cascading definitions */
+
+#define PIC_IRQS_MAX			31 /* Total irqs on PIC */
+/* The local irq line of the dummy peripheral on this chip */
+#define LOCALIRQ_DUMMY			15
+/* The irq index offset of this chip, is the maximum of previous chip + 1 */
+#define SIRQ_CHIP_OFFSET		(PIC_IRQS_MAX + 1)
+/* The global irq number of dummy is the local irq line + it's chip offset */
+#define IRQ_DUMMY			(LOCALIRQ_DUMMY + SIRQ_CHIP_OFFSET)
+
+
+#endif /* __PLATFORM_IRQ_H__ */

include/l4/platform/ab926/offsets.h

@@ -0,0 +1,60 @@
+/*
+ * Describes physical memory layout of pb926 platform.
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ */
+
+#ifndef __PLATFORM_PB926_OFFSETS_H__
+#define __PLATFORM_PB926_OFFSETS_H__
+
+/* Physical memory base */
+#define	PHYS_MEM_START			0x00000000 /* inclusive */
+#define	PHYS_MEM_END			0x08000000 /* 128 MB, exclusive */
+
+/*
+ * These bases taken from where kernel is `physically' linked at,
+ * also used to calculate virtual-to-physical translation offset.
+ * See the linker script for their sources. PHYS_ADDR_BASE can't
+ * use a linker variable because it's referred from assembler.
+ */
+#define	PHYS_ADDR_BASE			0x100000
+
+/* Device memory base */
+#define	PB926_DEV_PHYS			0x10000000
+
+/* Device offsets in physical memory */
+#define	PB926_SYSTEM_REGISTERS		0x10000000 /* System registers */
+#define	PB926_SYSCTRL_BASE		0x101E0000 /* System controller */
+#define	PB926_WATCHDOG_BASE		0x101E1000 /* Watchdog */
+#define	PB926_TIMER01_BASE		0x101E2000 /* Timers 0 and 1 */
+#define	PB926_TIMER23_BASE		0x101E3000 /* Timers 2 and 3 */
+#define	PB926_RTC_BASE			0x101E8000 /* Real Time Clock */
+#define	PB926_VIC_BASE			0x10140000 /* Primary Vectored IC */
+#define	PB926_SIC_BASE			0x10003000 /* Secondary IC */
+#define	PB926_UART0_BASE		0x101F1000 /* Console port (UART0) */
+
+/*
+ * Uart virtual address until a file-based console access
+ * is available for userspace
+ */
+#define	USERSPACE_UART_BASE		0x500000
+
+/*
+ * Device offsets in virtual memory. They offset to some virtual
+ * device base address. Each page on this virtual base is consecutively
+ * allocated to devices. Nice and smooth.
+ */
+#define PB926_TIMER01_VOFFSET			0x00000000
+#define PB926_UART0_VOFFSET			0x00001000
+#define	PB926_VIC_VOFFSET			0x00002000
+#define	PB926_SIC_VOFFSET			0x00003000
+#define PB926_SYSREGS_VOFFSET			0x00005000
+#define PB926_SYSCTRL_VOFFSET			0x00006000
+
+#define PB926_UART0_VBASE			(IO_AREA0_VADDR + PB926_UART0_VOFFSET)
+#define PB926_TIMER01_VBASE			(IO_AREA0_VADDR + PB926_TIMER01_VOFFSET)
+#define PB926_SYSCTRL_VBASE			(IO_AREA0_VADDR + PB926_SYSCTRL_VOFFSET)
+#define PB926_VIC_VBASE				(IO_AREA0_VADDR + PB926_VIC_VOFFSET)
+#define PB926_SIC_VBASE				(IO_AREA0_VADDR + PB926_SIC_VOFFSET)
+#endif /* __PLATFORM_PB926_OFFSETS_H__ */
+

include/l4/platform/ab926/platform.h

@@ -0,0 +1,22 @@
+#ifndef __PLATFORM_PB926_PLATFORM_H__
+#define __PLATFORM_PB926_PLATFORM_H__
+/*
+ * Platform specific ties between drivers and generic APIs used by the kernel.
+ * E.g. system timer and console.
+ *
+ * Copyright (C) Bahadir Balban 2007
+ */
+
+#include INC_PLAT(offsets.h)
+#include INC_GLUE(memlayout.h)
+
+#define PLATFORM_CONSOLE_BASE			PB926_UART0_VBASE
+#define PLATFORM_TIMER_BASE			PB926_TIMER01_VBASE
+#define PLATFORM_SP810_BASE			PB926_SYSCTRL_VBASE
+#define PLATFORM_IRQCTRL_BASE			PB926_VIC_VBASE
+#define PLATFORM_SIRQCTRL_BASE			PB926_SIC_VBASE
+
+void platform_irq_enable(int irq);
+void platform_irq_disable(int irq);
+void timer_start(void);
+#endif /* __PLATFORM_PB926_PLATFORM_H__ */

include/l4/platform/ab926/printascii.h

@@ -0,0 +1,15 @@
+#ifndef __PLATFORM__PB926__PRINTASCII__H__
+#define __PLATFORM__PB926__PRINTASCII__H__
+
+#define	dprintk(str, val)		\
+{					\
+	printascii(str);		\
+	printascii("0x");		\
+	printhex8((val));		\
+	printascii("\n");		\
+}
+
+void printascii(char *str);
+void printhex8(unsigned int);
+
+#endif /* __PLATFORM__PB926__PRINTASCII__H__ */

include/l4/platform/ab926/uart.h

@@ -0,0 +1,20 @@
+/*
+ * Platform specific ties to generic uart functions that putc expects.
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ *
+ */
+
+#ifndef __PLATFORM_PB926_UART_H__
+#define __PLATFORM_PB926_UART_H__
+
+#include INC_PLAT(offsets.h)
+#include INC_GLUE(memlayout.h)
+
+#define PLATFORM_CONSOLE_BASE			PB926_UART0_VBASE
+#include <l4/drivers/uart/pl011/pl011_uart.h>
+
+void uart_init(void);
+void uart_putc(char c);
+
+#endif /* __PLATFORM_PB926_UART_H__ */

include/l4/platform/eb/irq.h

@@ -0,0 +1,27 @@
+#ifndef __PLATFORM_IRQ_H__
+#define __PLATFORM_IRQ_H__
+
+#define IRQ_CHIPS_MAX				2
+#define IRQS_MAX				64
+
+/* IRQ indices. */
+#define IRQ_TIMER01			4
+#define IRQ_TIMER23			5
+#define IRQ_RTC				10
+#define IRQ_UART0			12
+#define IRQ_UART1			13
+#define IRQ_UART2			14
+#define IRQ_SIC				31
+
+/* Cascading definitions */
+
+#define PIC_IRQS_MAX			31 /* Total irqs on PIC */
+/* The local irq line of the dummy peripheral on this chip */
+#define LOCALIRQ_DUMMY			15
+/* The irq index offset of this chip, is the maximum of previous chip + 1 */
+#define SIRQ_CHIP_OFFSET		(PIC_IRQS_MAX + 1)
+/* The global irq number of dummy is the local irq line + it's chip offset */
+#define IRQ_DUMMY			(LOCALIRQ_DUMMY + SIRQ_CHIP_OFFSET)
+
+
+#endif /* __PLATFORM_IRQ_H__ */

include/l4/platform/eb/offsets.h

@@ -0,0 +1,60 @@
+/*
+ * Describes physical memory layout of pb926 platform.
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ */
+
+#ifndef __PLATFORM_PB926_OFFSETS_H__
+#define __PLATFORM_PB926_OFFSETS_H__
+
+/* Physical memory base */
+#define	PHYS_MEM_START			0x00000000 /* inclusive */
+#define	PHYS_MEM_END			0x08000000 /* 128 MB, exclusive */
+
+/*
+ * These bases taken from where kernel is `physically' linked at,
+ * also used to calculate virtual-to-physical translation offset.
+ * See the linker script for their sources. PHYS_ADDR_BASE can't
+ * use a linker variable because it's referred from assembler.
+ */
+#define	PHYS_ADDR_BASE			0x100000
+
+/* Device memory base */
+#define	PB926_DEV_PHYS			0x10000000
+
+/* Device offsets in physical memory */
+#define	PB926_SYSTEM_REGISTERS		0x10000000 /* System registers */
+#define	PB926_SYSCTRL_BASE		0x101E0000 /* System controller */
+#define	PB926_WATCHDOG_BASE		0x101E1000 /* Watchdog */
+#define	PB926_TIMER01_BASE		0x101E2000 /* Timers 0 and 1 */
+#define	PB926_TIMER23_BASE		0x101E3000 /* Timers 2 and 3 */
+#define	PB926_RTC_BASE			0x101E8000 /* Real Time Clock */
+#define	PB926_VIC_BASE			0x10140000 /* Primary Vectored IC */
+#define	PB926_SIC_BASE			0x10003000 /* Secondary IC */
+#define	PB926_UART0_BASE		0x101F1000 /* Console port (UART0) */
+
+/*
+ * Uart virtual address until a file-based console access
+ * is available for userspace
+ */
+#define	USERSPACE_UART_BASE		0x500000
+
+/*
+ * Device offsets in virtual memory. They offset to some virtual
+ * device base address. Each page on this virtual base is consecutively
+ * allocated to devices. Nice and smooth.
+ */
+#define PB926_TIMER01_VOFFSET			0x00000000
+#define PB926_UART0_VOFFSET			0x00001000
+#define	PB926_VIC_VOFFSET			0x00002000
+#define	PB926_SIC_VOFFSET			0x00003000
+#define PB926_SYSREGS_VOFFSET			0x00005000
+#define PB926_SYSCTRL_VOFFSET			0x00006000
+
+#define PB926_UART0_VBASE			(IO_AREA0_VADDR + PB926_UART0_VOFFSET)
+#define PB926_TIMER01_VBASE			(IO_AREA0_VADDR + PB926_TIMER01_VOFFSET)
+#define PB926_SYSCTRL_VBASE			(IO_AREA0_VADDR + PB926_SYSCTRL_VOFFSET)
+#define PB926_VIC_VBASE				(IO_AREA0_VADDR + PB926_VIC_VOFFSET)
+#define PB926_SIC_VBASE				(IO_AREA0_VADDR + PB926_SIC_VOFFSET)
+#endif /* __PLATFORM_PB926_OFFSETS_H__ */
+

include/l4/platform/eb/platform.h

@@ -0,0 +1,22 @@
+#ifndef __PLATFORM_PB926_PLATFORM_H__
+#define __PLATFORM_PB926_PLATFORM_H__
+/*
+ * Platform specific ties between drivers and generic APIs used by the kernel.
+ * E.g. system timer and console.
+ *
+ * Copyright (C) Bahadir Balban 2007
+ */
+
+#include INC_PLAT(offsets.h)
+#include INC_GLUE(memlayout.h)
+
+#define PLATFORM_CONSOLE_BASE			PB926_UART0_VBASE
+#define PLATFORM_TIMER_BASE			PB926_TIMER01_VBASE
+#define PLATFORM_SP810_BASE			PB926_SYSCTRL_VBASE
+#define PLATFORM_IRQCTRL_BASE			PB926_VIC_VBASE
+#define PLATFORM_SIRQCTRL_BASE			PB926_SIC_VBASE
+
+void platform_irq_enable(int irq);
+void platform_irq_disable(int irq);
+void timer_start(void);
+#endif /* __PLATFORM_PB926_PLATFORM_H__ */

include/l4/platform/eb/printascii.h

@@ -0,0 +1,15 @@
+#ifndef __PLATFORM__PB926__PRINTASCII__H__
+#define __PLATFORM__PB926__PRINTASCII__H__
+
+#define	dprintk(str, val)		\
+{					\
+	printascii(str);		\
+	printascii("0x");		\
+	printhex8((val));		\
+	printascii("\n");		\
+}
+
+void printascii(char *str);
+void printhex8(unsigned int);
+
+#endif /* __PLATFORM__PB926__PRINTASCII__H__ */

include/l4/platform/eb/uart.h

@@ -0,0 +1,20 @@
+/*
+ * Platform specific ties to generic uart functions that putc expects.
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ *
+ */
+
+#ifndef __PLATFORM_PB926_UART_H__
+#define __PLATFORM_PB926_UART_H__
+
+#include INC_PLAT(offsets.h)
+#include INC_GLUE(memlayout.h)
+
+#define PLATFORM_CONSOLE_BASE			PB926_UART0_VBASE
+#include <l4/drivers/uart/pl011/pl011_uart.h>
+
+void uart_init(void);
+void uart_putc(char c);
+
+#endif /* __PLATFORM_PB926_UART_H__ */

include/l4/platform/pb11mpcore/irq.h

@@ -0,0 +1,27 @@
+#ifndef __PLATFORM_IRQ_H__
+#define __PLATFORM_IRQ_H__
+
+#define IRQ_CHIPS_MAX				2
+#define IRQS_MAX				64
+
+/* IRQ indices. */
+#define IRQ_TIMER01			4
+#define IRQ_TIMER23			5
+#define IRQ_RTC				10
+#define IRQ_UART0			12
+#define IRQ_UART1			13
+#define IRQ_UART2			14
+#define IRQ_SIC				31
+
+/* Cascading definitions */
+
+#define PIC_IRQS_MAX			31 /* Total irqs on PIC */
+/* The local irq line of the dummy peripheral on this chip */
+#define LOCALIRQ_DUMMY			15
+/* The irq index offset of this chip, is the maximum of previous chip + 1 */
+#define SIRQ_CHIP_OFFSET		(PIC_IRQS_MAX + 1)
+/* The global irq number of dummy is the local irq line + it's chip offset */
+#define IRQ_DUMMY			(LOCALIRQ_DUMMY + SIRQ_CHIP_OFFSET)
+
+
+#endif /* __PLATFORM_IRQ_H__ */

include/l4/platform/pb11mpcore/offsets.h

@@ -0,0 +1,60 @@
+/*
+ * Describes physical memory layout of pb926 platform.
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ */
+
+#ifndef __PLATFORM_PB926_OFFSETS_H__
+#define __PLATFORM_PB926_OFFSETS_H__
+
+/* Physical memory base */
+#define	PHYS_MEM_START			0x00000000 /* inclusive */
+#define	PHYS_MEM_END			0x08000000 /* 128 MB, exclusive */
+
+/*
+ * These bases taken from where kernel is `physically' linked at,
+ * also used to calculate virtual-to-physical translation offset.
+ * See the linker script for their sources. PHYS_ADDR_BASE can't
+ * use a linker variable because it's referred from assembler.
+ */
+#define	PHYS_ADDR_BASE			0x100000
+
+/* Device memory base */
+#define	PB926_DEV_PHYS			0x10000000
+
+/* Device offsets in physical memory */
+#define	PB926_SYSTEM_REGISTERS		0x10000000 /* System registers */
+#define	PB926_SYSCTRL_BASE		0x101E0000 /* System controller */
+#define	PB926_WATCHDOG_BASE		0x101E1000 /* Watchdog */
+#define	PB926_TIMER01_BASE		0x101E2000 /* Timers 0 and 1 */
+#define	PB926_TIMER23_BASE		0x101E3000 /* Timers 2 and 3 */
+#define	PB926_RTC_BASE			0x101E8000 /* Real Time Clock */
+#define	PB926_VIC_BASE			0x10140000 /* Primary Vectored IC */
+#define	PB926_SIC_BASE			0x10003000 /* Secondary IC */
+#define	PB926_UART0_BASE		0x101F1000 /* Console port (UART0) */
+
+/*
+ * Uart virtual address until a file-based console access
+ * is available for userspace
+ */
+#define	USERSPACE_UART_BASE		0x500000
+
+/*
+ * Device offsets in virtual memory. They offset to some virtual
+ * device base address. Each page on this virtual base is consecutively
+ * allocated to devices. Nice and smooth.
+ */
+#define PB926_TIMER01_VOFFSET			0x00000000
+#define PB926_UART0_VOFFSET			0x00001000
+#define	PB926_VIC_VOFFSET			0x00002000
+#define	PB926_SIC_VOFFSET			0x00003000
+#define PB926_SYSREGS_VOFFSET			0x00005000
+#define PB926_SYSCTRL_VOFFSET			0x00006000
+
+#define PB926_UART0_VBASE			(IO_AREA0_VADDR + PB926_UART0_VOFFSET)
+#define PB926_TIMER01_VBASE			(IO_AREA0_VADDR + PB926_TIMER01_VOFFSET)
+#define PB926_SYSCTRL_VBASE			(IO_AREA0_VADDR + PB926_SYSCTRL_VOFFSET)
+#define PB926_VIC_VBASE				(IO_AREA0_VADDR + PB926_VIC_VOFFSET)
+#define PB926_SIC_VBASE				(IO_AREA0_VADDR + PB926_SIC_VOFFSET)
+#endif /* __PLATFORM_PB926_OFFSETS_H__ */
+

include/l4/platform/pb11mpcore/platform.h

@@ -0,0 +1,22 @@
+#ifndef __PLATFORM_PB926_PLATFORM_H__
+#define __PLATFORM_PB926_PLATFORM_H__
+/*
+ * Platform specific ties between drivers and generic APIs used by the kernel.
+ * E.g. system timer and console.
+ *
+ * Copyright (C) Bahadir Balban 2007
+ */
+
+#include INC_PLAT(offsets.h)
+#include INC_GLUE(memlayout.h)
+
+#define PLATFORM_CONSOLE_BASE			PB926_UART0_VBASE
+#define PLATFORM_TIMER_BASE			PB926_TIMER01_VBASE
+#define PLATFORM_SP810_BASE			PB926_SYSCTRL_VBASE
+#define PLATFORM_IRQCTRL_BASE			PB926_VIC_VBASE
+#define PLATFORM_SIRQCTRL_BASE			PB926_SIC_VBASE
+
+void platform_irq_enable(int irq);
+void platform_irq_disable(int irq);
+void timer_start(void);
+#endif /* __PLATFORM_PB926_PLATFORM_H__ */

include/l4/platform/pb11mpcore/printascii.h

@@ -0,0 +1,15 @@
+#ifndef __PLATFORM__PB926__PRINTASCII__H__
+#define __PLATFORM__PB926__PRINTASCII__H__
+
+#define	dprintk(str, val)		\
+{					\
+	printascii(str);		\
+	printascii("0x");		\
+	printhex8((val));		\
+	printascii("\n");		\
+}
+
+void printascii(char *str);
+void printhex8(unsigned int);
+
+#endif /* __PLATFORM__PB926__PRINTASCII__H__ */

include/l4/platform/pb11mpcore/uart.h

@@ -0,0 +1,20 @@
+/*
+ * Platform specific ties to generic uart functions that putc expects.
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ *
+ */
+
+#ifndef __PLATFORM_PB926_UART_H__
+#define __PLATFORM_PB926_UART_H__
+
+#include INC_PLAT(offsets.h)
+#include INC_GLUE(memlayout.h)
+
+#define PLATFORM_CONSOLE_BASE			PB926_UART0_VBASE
+#include <l4/drivers/uart/pl011/pl011_uart.h>
+
+void uart_init(void);
+void uart_putc(char c);
+
+#endif /* __PLATFORM_PB926_UART_H__ */

include/l4/platform/pba8/irq.h

@@ -0,0 +1,27 @@
+#ifndef __PLATFORM_IRQ_H__
+#define __PLATFORM_IRQ_H__
+
+#define IRQ_CHIPS_MAX				2
+#define IRQS_MAX				64
+
+/* IRQ indices. */
+#define IRQ_TIMER01			4
+#define IRQ_TIMER23			5
+#define IRQ_RTC				10
+#define IRQ_UART0			12
+#define IRQ_UART1			13
+#define IRQ_UART2			14
+#define IRQ_SIC				31
+
+/* Cascading definitions */
+
+#define PIC_IRQS_MAX			31 /* Total irqs on PIC */
+/* The local irq line of the dummy peripheral on this chip */
+#define LOCALIRQ_DUMMY			15
+/* The irq index offset of this chip, is the maximum of previous chip + 1 */
+#define SIRQ_CHIP_OFFSET		(PIC_IRQS_MAX + 1)
+/* The global irq number of dummy is the local irq line + it's chip offset */
+#define IRQ_DUMMY			(LOCALIRQ_DUMMY + SIRQ_CHIP_OFFSET)
+
+
+#endif /* __PLATFORM_IRQ_H__ */

include/l4/platform/pba8/offsets.h

@@ -0,0 +1,60 @@
+/*
+ * Describes physical memory layout of pb926 platform.
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ */
+
+#ifndef __PLATFORM_PB926_OFFSETS_H__
+#define __PLATFORM_PB926_OFFSETS_H__
+
+/* Physical memory base */
+#define	PHYS_MEM_START			0x00000000 /* inclusive */
+#define	PHYS_MEM_END			0x08000000 /* 128 MB, exclusive */
+
+/*
+ * These bases taken from where kernel is `physically' linked at,
+ * also used to calculate virtual-to-physical translation offset.
+ * See the linker script for their sources. PHYS_ADDR_BASE can't
+ * use a linker variable because it's referred from assembler.
+ */
+#define	PHYS_ADDR_BASE			0x100000
+
+/* Device memory base */
+#define	PB926_DEV_PHYS			0x10000000
+
+/* Device offsets in physical memory */
+#define	PB926_SYSTEM_REGISTERS		0x10000000 /* System registers */
+#define	PB926_SYSCTRL_BASE		0x101E0000 /* System controller */
+#define	PB926_WATCHDOG_BASE		0x101E1000 /* Watchdog */
+#define	PB926_TIMER01_BASE		0x101E2000 /* Timers 0 and 1 */
+#define	PB926_TIMER23_BASE		0x101E3000 /* Timers 2 and 3 */
+#define	PB926_RTC_BASE			0x101E8000 /* Real Time Clock */
+#define	PB926_VIC_BASE			0x10140000 /* Primary Vectored IC */
+#define	PB926_SIC_BASE			0x10003000 /* Secondary IC */
+#define	PB926_UART0_BASE		0x101F1000 /* Console port (UART0) */
+
+/*
+ * Uart virtual address until a file-based console access
+ * is available for userspace
+ */
+#define	USERSPACE_UART_BASE		0x500000
+
+/*
+ * Device offsets in virtual memory. They offset to some virtual
+ * device base address. Each page on this virtual base is consecutively
+ * allocated to devices. Nice and smooth.
+ */
+#define PB926_TIMER01_VOFFSET			0x00000000
+#define PB926_UART0_VOFFSET			0x00001000
+#define	PB926_VIC_VOFFSET			0x00002000
+#define	PB926_SIC_VOFFSET			0x00003000
+#define PB926_SYSREGS_VOFFSET			0x00005000
+#define PB926_SYSCTRL_VOFFSET			0x00006000
+
+#define PB926_UART0_VBASE			(IO_AREA0_VADDR + PB926_UART0_VOFFSET)
+#define PB926_TIMER01_VBASE			(IO_AREA0_VADDR + PB926_TIMER01_VOFFSET)
+#define PB926_SYSCTRL_VBASE			(IO_AREA0_VADDR + PB926_SYSCTRL_VOFFSET)
+#define PB926_VIC_VBASE				(IO_AREA0_VADDR + PB926_VIC_VOFFSET)
+#define PB926_SIC_VBASE				(IO_AREA0_VADDR + PB926_SIC_VOFFSET)
+#endif /* __PLATFORM_PB926_OFFSETS_H__ */
+

include/l4/platform/pba8/platform.h

@@ -0,0 +1,22 @@
+#ifndef __PLATFORM_PB926_PLATFORM_H__
+#define __PLATFORM_PB926_PLATFORM_H__
+/*
+ * Platform specific ties between drivers and generic APIs used by the kernel.
+ * E.g. system timer and console.
+ *
+ * Copyright (C) Bahadir Balban 2007
+ */
+
+#include INC_PLAT(offsets.h)
+#include INC_GLUE(memlayout.h)
+
+#define PLATFORM_CONSOLE_BASE			PB926_UART0_VBASE
+#define PLATFORM_TIMER_BASE			PB926_TIMER01_VBASE
+#define PLATFORM_SP810_BASE			PB926_SYSCTRL_VBASE
+#define PLATFORM_IRQCTRL_BASE			PB926_VIC_VBASE
+#define PLATFORM_SIRQCTRL_BASE			PB926_SIC_VBASE
+
+void platform_irq_enable(int irq);
+void platform_irq_disable(int irq);
+void timer_start(void);
+#endif /* __PLATFORM_PB926_PLATFORM_H__ */

include/l4/platform/pba8/printascii.h

@@ -0,0 +1,15 @@
+#ifndef __PLATFORM__PB926__PRINTASCII__H__
+#define __PLATFORM__PB926__PRINTASCII__H__
+
+#define	dprintk(str, val)		\
+{					\
+	printascii(str);		\
+	printascii("0x");		\
+	printhex8((val));		\
+	printascii("\n");		\
+}
+
+void printascii(char *str);
+void printhex8(unsigned int);
+
+#endif /* __PLATFORM__PB926__PRINTASCII__H__ */

include/l4/platform/pba8/uart.h

@@ -0,0 +1,20 @@
+/*
+ * Platform specific ties to generic uart functions that putc expects.
+ *
+ * Copyright (C) 2007 Bahadir Balban
+ *
+ */
+
+#ifndef __PLATFORM_PB926_UART_H__
+#define __PLATFORM_PB926_UART_H__
+
+#include INC_PLAT(offsets.h)
+#include INC_GLUE(memlayout.h)
+
+#define PLATFORM_CONSOLE_BASE			PB926_UART0_VBASE
+#include <l4/drivers/uart/pl011/pl011_uart.h>
+
+void uart_init(void);
+void uart_putc(char c);
+
+#endif /* __PLATFORM_PB926_UART_H__ */