diff --git a/conts/libl4/include/l4lib/arch-arm/syslib.h b/conts/libl4/include/l4lib/arch-arm/syslib.h index b8b2245..e062a47 100644 --- a/conts/libl4/include/l4lib/arch-arm/syslib.h +++ b/conts/libl4/include/l4lib/arch-arm/syslib.h @@ -128,9 +128,14 @@ static inline int l4_get_retval(void) } /* - * If we're about to do another ipc, this saves the last ipc's - * parameters such as the sender and tag information. - * Any previously saved data in save slots are destroyed. + * This is useful for stacked IPC. A stacked IPC happens + * when a new IPC is initiated before concluding the current + * one. + * + * This saves the last ipc's parameters such as the sender + * and tag information. Any previously saved data in save + * slots are destroyed. This is fine as IPC stacking is only + * useful if done once. */ static inline void l4_save_ipcregs(void) { diff --git a/include/l4/api/ipc.h b/include/l4/api/ipc.h index 4b291e1..0f66684 100644 --- a/include/l4/api/ipc.h +++ b/include/l4/api/ipc.h @@ -9,15 +9,18 @@ /* Pagefault */ #define L4_IPC_TAG_PFAULT 0 +#define L4_IPC_FLAGS_TYPE_MASK 0x0000000F #define L4_IPC_FLAGS_SHORT 0x00000000 /* Short IPC involves just primary message registers */ #define L4_IPC_FLAGS_FULL 0x00000001 /* Full IPC involves full UTCB copy */ #define L4_IPC_FLAGS_EXTENDED 0x00000002 /* Extended IPC can page-fault and copy up to 2KB */ + +/* Extended IPC extra fields */ #define L4_IPC_FLAGS_MSG_INDEX_MASK 0x00000FF0 /* Index of message register with buffer pointer */ -#define L4_IPC_FLAGS_TYPE_MASK 0x0000000F #define L4_IPC_FLAGS_SIZE_MASK 0x0FFF0000 #define L4_IPC_FLAGS_SIZE_SHIFT 16 #define L4_IPC_FLAGS_MSG_INDEX_SHIFT 4 + #define L4_IPC_EXTENDED_MAX_SIZE (SZ_1K*2) #if defined (__KERNEL__) diff --git a/include/l4/glue/arm/message.h b/include/l4/glue/arm/message.h index 0d9a8c8..ab859bb 100644 --- a/include/l4/glue/arm/message.h +++ b/include/l4/glue/arm/message.h @@ -14,7 +14,7 @@ * the microkernel will read and they have system-wide meaning. * * Primary message registers: - * r3 - r8: These 6 registers are the primary message registers MR0-MR6 + * r3 - r8: These 6 registers are the primary message registers MR0-MR6. * Their format is application-specific, i.e. the microkernel imposes no * format restrictions on them. *