mirror of
https://github.com/drasko/codezero.git
synced 2026-01-12 02:43:15 +01:00
Added offsets for MPCORE, EB and CORTEX-A8
This commit is contained in:
Amit Mahajan
@@ -40,6 +40,9 @@
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#define PMD_ENTRY_TOTAL 256
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#define PMD_MAP_SIZE SZ_1MB
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/* We need this as printascii.S is including this file */
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#ifndef __ASSEMBLY__
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/* Type-checkable page table elements */
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typedef u32 pgd_t;
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typedef u32 pmd_t;
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@@ -157,4 +160,5 @@ void remove_section_mapping(unsigned long vaddr);
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void copy_pgds_by_vrange(pgd_table_t *to, pgd_table_t *from,
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unsigned long start, unsigned long end);
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#endif /* __ASSEMBLY__ */
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#endif /* __V5_MM_H__ */
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@@ -1,56 +1,35 @@
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/*
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* PL190 Primecell Vectored Interrupt Controller offsets
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* Generic Interrupt Controller offsets
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*
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* Copyright (C) 2007 Bahadir Balban
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*
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*/
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#ifndef __PL190_VIC_H__
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#define __PL190_VIC_H__
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#ifndef __ARM_GIC_H__
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#define __ARM_GIC_H__
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#include INC_PLAT(platform.h)
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#define PL190_BASE PLATFORM_IRQCTRL_BASE
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#define PL190_SIC_BASE PLATFORM_SIRQCTRL_BASE
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/* GIC CPU register offsets */
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#define ARM_GIC_CPU_ICR 0x00 /* Interface Control */
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#define ARM_GIC_CPUPMR 0x04 /* Interrupt Priority Mask */
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#define ARM_GIC_CPU_BPR 0x08 /* Binary Point */
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#define ARM_GIC_CPU_IAR 0x0c /* Interrupt Acknowledge */
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#define ARM_GIC_CPU_EOIR 0x10 /* End of Interrupt */
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#define ARM_GIC_CPU_RRI 0x14 /* Running Priority */
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#define ARM_GIC_CPU_HPIR 0x18 /* Highest Priority Interrupt*/
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/* VIC register offsets */
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#define PL190_VIC_IRQSTATUS (PL190_BASE + 0x00)
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#define PL190_VIC_FIQSTATUS (PL190_BASE + 0x04)
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#define PL190_VIC_RAWINTR (PL190_BASE + 0x08)
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#define PL190_VIC_INTSELECT (PL190_BASE + 0x0C)
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#define PL190_VIC_INTENABLE (PL190_BASE + 0x10)
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#define PL190_VIC_INTENCLEAR (PL190_BASE + 0x14)
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#define PL190_VIC_SOFTINT (PL190_BASE + 0x18)
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#define PL190_VIC_SOFTINTCLEAR (PL190_BASE + 0x1C)
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#define PL190_VIC_PROTECTION (PL190_BASE + 0x20)
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#define PL190_VIC_VECTADDR (PL190_BASE + 0x30)
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#define PL190_VIC_DEFVECTADDR (PL190_BASE + 0x34)
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#define PL190_VIC_VECTADDR0 (PL190_BASE + 0x100)
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/* 15 PIC_VECTADDR registers up to 0x13C */
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#define PL190_VIC_VECTCNTL0 (PL190_BASE + 0x200)
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/* 15 PIC_VECTCNTL registers up to 0x23C */
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/* Distributor register map */
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#define ARM_GIC_DIST_CR 0x000 /* Control Register */
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#define ARM_GIC_DIST_ICTR 0x004 /* Interface Controller Type */
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#define ARM_GIC_DIST_ISER 0x100 /* Interrupt Set Enable */
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#define ARM_GIC_DIST_ICER 0x180 /* Interrupt Clear Enable */
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#define ARM_GIC_DIST_ISPR 0x200 /* Interrupt Set Pending */
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#define ARM_GIC_DIST_ICPR 0x280 /* Interrupt Clear Pending*/
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#define ARM_GIC_DIST_ABR 0x300 /* Active Bit */
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#define ARM_GIC_DIST_IPR 0x400 /* Interrupt Priority */
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#define ARM_GIC_DIST_IPTR 0x800 /* Interrupt Processor Target */
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#define ARM_GIC_DIST_ICR 0xc00 /* Interrupt Configuration */
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#define ARM_GIC_DIST_SGIR 0xf00 /* Software Generated Interrupt */
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#define PL190_SIC_STATUS (PL190_SIC_BASE + 0x0)
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#define PL190_SIC_RAWSTAT (PL190_SIC_BASE + 0x04)
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#define PL190_SIC_ENABLE (PL190_SIC_BASE + 0x08)
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#define PL190_SIC_ENSET (PL190_SIC_BASE + 0x08)
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#define PL190_SIC_ENCLR (PL190_SIC_BASE + 0x0C)
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#define PL190_SIC_SOFTINTSET (PL190_SIC_BASE + 0x10)
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#define PL190_SIC_SOFTINTCLR (PL190_SIC_BASE + 0x14)
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#define PL190_SIC_PICENABLE (PL190_SIC_BASE + 0x20)
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#define PL190_SIC_PICENSET (PL190_SIC_BASE + 0x20)
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#define PL190_SIC_PICENCLR (PL190_SIC_BASE + 0x24)
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void pl190_vic_init(void);
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void pl190_ack_irq(int irq);
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void pl190_mask_irq(int irq);
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void pl190_unmask_irq(int irq);
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int pl190_read_irq(void);
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int pl190_sic_read_irq(void);
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void pl190_sic_mask_irq(int irq);
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void pl190_sic_mask_irq(int irq);
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void pl190_sic_ack_irq(int irq);
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void pl190_sic_unmask_irq(int irq);
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void pl190_sic_init(void);
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#endif /* __PL190_VIC_H__ */
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#endif /* __ARM_GIC_H__ */
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@@ -1,27 +1,31 @@
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#ifndef __PLATFORM_IRQ_H__
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#define __PLATFORM_IRQ_H__
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#define IRQ_CHIPS_MAX 2
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#define IRQS_MAX 64
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/* TODO: Not sure about this, need to check */
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#define IRQ_CHIPS_MAX 4
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#define IRQS_MAX 96
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/* IRQ indices. */
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/*
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* IRQ indices,
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* GIC 0 and 1 are for logic tile 1
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* GIC 2 and 3 are for logic tile 2
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*/
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#define IRQ_TIMER01 4
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#define IRQ_TIMER23 5
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#define IRQ_RTC 10
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#define IRQ_UART0 12
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#define IRQ_UART1 13
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#define IRQ_UART2 14
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#define IRQ_SIC 31
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/* Cascading definitions */
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#define PIC_IRQS_MAX 31 /* Total irqs on PIC */
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/* The local irq line of the dummy peripheral on this chip */
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#define LOCALIRQ_DUMMY 15
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/* The irq index offset of this chip, is the maximum of previous chip + 1 */
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#define SIRQ_CHIP_OFFSET (PIC_IRQS_MAX + 1)
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/* The global irq number of dummy is the local irq line + it's chip offset */
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#define IRQ_DUMMY (LOCALIRQ_DUMMY + SIRQ_CHIP_OFFSET)
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#define IRQ_UART3 15
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/*
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* TODO: Seems like GIC0 and GIC1 are cascaded for logic tile1
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* and GIC2 and GIC3 are cascaded for logic tile 2.
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* Interrupt Distribution:
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* 0-31: Used as SI provided by distributed interrupt controller
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* 32-63: Externel Peripheral Interrupts
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* 64-71: Interrupts from tile site 1
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* 72-79: Interrupts from tile site 2
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* 80-95: PCI and reserved Interrupts
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*/
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#endif /* __PLATFORM_IRQ_H__ */
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@@ -1,15 +1,15 @@
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/*
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* Describes physical memory layout of pb926 platform.
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* Describes physical memory layout of EB platform.
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*
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* Copyright (C) 2007 Bahadir Balban
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*/
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#ifndef __PLATFORM_PB926_OFFSETS_H__
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#define __PLATFORM_PB926_OFFSETS_H__
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#ifndef __PLATFORM_EB_OFFSETS_H__
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#define __PLATFORM_EB_OFFSETS_H__
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/* Physical memory base */
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#define PHYS_MEM_START 0x00000000 /* inclusive */
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#define PHYS_MEM_END 0x08000000 /* 128 MB, exclusive */
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#define PHYS_MEM_END 0x10000000 /* 256 MB, exclusive */
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/*
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* These bases taken from where kernel is `physically' linked at,
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@@ -20,18 +20,23 @@
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#define PHYS_ADDR_BASE 0x100000
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/* Device memory base */
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#define PB926_DEV_PHYS 0x10000000
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#define EB_DEV_PHYS 0x10000000
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/* Device offsets in physical memory */
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#define PB926_SYSTEM_REGISTERS 0x10000000 /* System registers */
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#define PB926_SYSCTRL_BASE 0x101E0000 /* System controller */
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#define PB926_WATCHDOG_BASE 0x101E1000 /* Watchdog */
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#define PB926_TIMER01_BASE 0x101E2000 /* Timers 0 and 1 */
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#define PB926_TIMER23_BASE 0x101E3000 /* Timers 2 and 3 */
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#define PB926_RTC_BASE 0x101E8000 /* Real Time Clock */
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#define PB926_VIC_BASE 0x10140000 /* Primary Vectored IC */
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#define PB926_SIC_BASE 0x10003000 /* Secondary IC */
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#define PB926_UART0_BASE 0x101F1000 /* Console port (UART0) */
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#define EB_SYSTEM_REGISTERS 0x10000000 /* System registers */
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#define EB_SYSCTRL_BASE 0x10001000 /* System controller */
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#define EB_UART0_BASE 0x10009000 /* UART 0 */
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#define EB_UART1_BASE 0x1000A000 /* UART 1 */
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#define EB_UART2_BASE 0x1000B000 /* UART 2 */
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#define EB_UART3_BASE 0x1000C000 /* UART 3 */
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#define EB_WATCHDOG0_BASE 0x10010000 /* WATCHDOG */
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#define EB_TIMER01_BASE 0x10011000 /* TIMER 0-1 */
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#define EB_TIMER23_BASE 0x10012000 /* TIMER 2-3 */
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#define EB_RTC_BASE 0x10017000 /* RTC interface */
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#define EB_GIC0_BASE 0x10040000 /* GIC 0 */
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#define EB_GIC1_BASE 0x10050000 /* GIC 1 */
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#define EB_GIC2_BASE 0x10060000 /* GIC 2 */
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#define EB_GIC3_BASE 0x10070000 /* GIC 3 */
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/*
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* Uart virtual address until a file-based console access
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@@ -44,17 +49,23 @@
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* device base address. Each page on this virtual base is consecutively
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* allocated to devices. Nice and smooth.
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*/
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#define PB926_TIMER01_VOFFSET 0x00000000
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#define PB926_UART0_VOFFSET 0x00001000
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#define PB926_VIC_VOFFSET 0x00002000
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#define PB926_SIC_VOFFSET 0x00003000
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#define PB926_SYSREGS_VOFFSET 0x00005000
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#define PB926_SYSCTRL_VOFFSET 0x00006000
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#define EB_SYSREGS_VOFFSET 0x00000000
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#define EB_SYSCTRL_VOFFSET 0x00001000
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#define EB_UART0_VOFFSET 0x00002000
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#define EB_TIMER01_VOFFSET 0x00003000
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#define EB_GIC0_VOFFSET 0x00004000
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#define EB_GIC1_VOFFSET 0x00005000
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#define EB_GIC2_VOFFSET 0x00006000
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#define EB_GIC3_VOFFSET 0x00007000
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#define PB926_UART0_VBASE (IO_AREA0_VADDR + PB926_UART0_VOFFSET)
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#define PB926_TIMER01_VBASE (IO_AREA0_VADDR + PB926_TIMER01_VOFFSET)
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#define PB926_SYSCTRL_VBASE (IO_AREA0_VADDR + PB926_SYSCTRL_VOFFSET)
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#define PB926_VIC_VBASE (IO_AREA0_VADDR + PB926_VIC_VOFFSET)
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#define PB926_SIC_VBASE (IO_AREA0_VADDR + PB926_SIC_VOFFSET)
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#endif /* __PLATFORM_PB926_OFFSETS_H__ */
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#define EB_SYSREGS_VBASE (IO_AREA0_VADDR + EB_SYSREGS_VOFFSET)
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#define EB_SYSCTRL_VBASE (IO_AREA0_VADDR + EB_SYSCTRL0_VOFFSET)
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#define EB_UART0_VBASE (IO_AREA0_VADDR + EB_UART0_VOFFSET)
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#define EB_TIMER01_VBASE (IO_AREA0_VADDR + EB_TIMER01_VOFFSET)
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#define EB_GIC0_VBASE (IO_AREA0_VADDR + EB_GIC0_VOFFSET)
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#define EB_GIC1_VBASE (IO_AREA0_VADDR + EB_GIC1_VOFFSET)
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#define EB_GIC2_VBASE (IO_AREA0_VADDR + EB_GIC2_VOFFSET)
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#define EB_GIC3_VBASE (IO_AREA0_VADDR + EB_GIC3_VOFFSET)
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#endif /* __PLATFORM_EB_OFFSETS_H__ */
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@@ -1,5 +1,5 @@
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#ifndef __PLATFORM_PB926_PLATFORM_H__
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#define __PLATFORM_PB926_PLATFORM_H__
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#ifndef __PLATFORM_EB_PLATFORM_H__
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#define __PLATFORM_EB_PLATFORM_H__
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/*
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* Platform specific ties between drivers and generic APIs used by the kernel.
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* E.g. system timer and console.
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@@ -10,13 +10,19 @@
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#include INC_PLAT(offsets.h)
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#include INC_GLUE(memlayout.h)
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#define PLATFORM_CONSOLE_BASE PB926_UART0_VBASE
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#define PLATFORM_TIMER_BASE PB926_TIMER01_VBASE
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#define PLATFORM_SP810_BASE PB926_SYSCTRL_VBASE
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#define PLATFORM_IRQCTRL_BASE PB926_VIC_VBASE
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#define PLATFORM_SIRQCTRL_BASE PB926_SIC_VBASE
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#define PLATFORM_CONSOLE0_BASE EB_UART0_VBASE
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#define PLATFORM_TIMER0_BASE EB_TIMER01_VBASE
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#define PLATFORM_SP810_BASE EB_SYSCTRL_VBASE
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/* Total number of timers present in this platform */
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#define TOTAL_TIMERS 4
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#define PLATFORM_TIMER0 0
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#define PLATFORM_TIMER1 1
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#define PLATFORM_TIMER2 2
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#define PLATFORM_TIMER3 3
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void platform_irq_enable(int irq);
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void platform_irq_disable(int irq);
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void timer_start(void);
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#endif /* __PLATFORM_PB926_PLATFORM_H__ */
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#endif /* __PLATFORM_EB_PLATFORM_H__ */
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@@ -1,5 +1,5 @@
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#ifndef __PLATFORM__PB926__PRINTASCII__H__
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#define __PLATFORM__PB926__PRINTASCII__H__
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#ifndef __PLATFORM__EB__PRINTASCII__H__
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#define __PLATFORM__EB__PRINTASCII__H__
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#define dprintk(str, val) \
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{ \
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@@ -12,4 +12,4 @@
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void printascii(char *str);
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void printhex8(unsigned int);
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#endif /* __PLATFORM__PB926__PRINTASCII__H__ */
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#endif /* __PLATFORM__EB__PRINTASCII__H__ */
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@@ -5,16 +5,16 @@
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*
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*/
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#ifndef __PLATFORM_PB926_UART_H__
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#define __PLATFORM_PB926_UART_H__
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#ifndef __PLATFORM_EB_UART_H__
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#define __PLATFORM_EB_UART_H__
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#include INC_PLAT(offsets.h)
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#include INC_GLUE(memlayout.h)
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#define PLATFORM_CONSOLE_BASE PB926_UART0_VBASE
|
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#define PLATFORM_CONSOLE_BASE EB_UART0_VBASE
|
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#include <l4/drivers/uart/pl011/pl011_uart.h>
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void uart_init(void);
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void uart_putc(char c);
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#endif /* __PLATFORM_PB926_UART_H__ */
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#endif /* __PLATFORM_EB_UART_H__ */
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@@ -1,27 +1,27 @@
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#ifndef __PLATFORM_IRQ_H__
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#define __PLATFORM_IRQ_H__
|
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|
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#define IRQ_CHIPS_MAX 2
|
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#define IRQS_MAX 64
|
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/* TODO: Not sure about this, need to check */
|
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#define IRQ_CHIPS_MAX 4
|
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#define IRQS_MAX 96
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/* IRQ indices. */
|
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#define IRQ_TIMER01 4
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#define IRQ_TIMER23 5
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#define IRQ_RTC 10
|
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#define IRQ_UART0 12
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#define IRQ_UART1 13
|
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#define IRQ_UART2 14
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#define IRQ_SIC 31
|
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|
||||
/* Cascading definitions */
|
||||
|
||||
#define PIC_IRQS_MAX 31 /* Total irqs on PIC */
|
||||
/* The local irq line of the dummy peripheral on this chip */
|
||||
#define LOCALIRQ_DUMMY 15
|
||||
/* The irq index offset of this chip, is the maximum of previous chip + 1 */
|
||||
#define SIRQ_CHIP_OFFSET (PIC_IRQS_MAX + 1)
|
||||
/* The global irq number of dummy is the local irq line + it's chip offset */
|
||||
#define IRQ_DUMMY (LOCALIRQ_DUMMY + SIRQ_CHIP_OFFSET)
|
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#define IRQ_TIMER01 36
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||||
#define IRQ_TIMER23 37
|
||||
#define IRQ_TIMER45 73
|
||||
#define IRQ_TIMER67 74
|
||||
#define IRQ_RTC 42
|
||||
#define IRQ_UART0 44
|
||||
#define IRQ_UART1 45
|
||||
#define IRQ_UART2 46
|
||||
#define IRQ_UART3 47
|
||||
|
||||
/*
|
||||
* Interrupt Distribution:
|
||||
* 0-31: SI, provided by distributed interrupt controller
|
||||
* 32-63: Externel peripheral interrupts
|
||||
* 64-71: Tile site interrupt
|
||||
* 72-95: Externel peripheral interrupts
|
||||
*/
|
||||
|
||||
#endif /* __PLATFORM_IRQ_H__ */
|
||||
|
||||
@@ -1,15 +1,15 @@
|
||||
/*
|
||||
* Describes physical memory layout of pb926 platform.
|
||||
* Describes physical memory layout of PB11MPCORE platform.
|
||||
*
|
||||
* Copyright (C) 2007 Bahadir Balban
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_PB926_OFFSETS_H__
|
||||
#define __PLATFORM_PB926_OFFSETS_H__
|
||||
#ifndef __PLATFORM_PB11MPCORE_OFFSETS_H__
|
||||
#define __PLATFORM_PB11MPCORE_OFFSETS_H__
|
||||
|
||||
/* Physical memory base */
|
||||
#define PHYS_MEM_START 0x00000000 /* inclusive */
|
||||
#define PHYS_MEM_END 0x08000000 /* 128 MB, exclusive */
|
||||
#define PHYS_MEM_END 0x10000000 /* 256 MB, exclusive */
|
||||
|
||||
/*
|
||||
* These bases taken from where kernel is `physically' linked at,
|
||||
@@ -20,18 +20,27 @@
|
||||
#define PHYS_ADDR_BASE 0x100000
|
||||
|
||||
/* Device memory base */
|
||||
#define PB926_DEV_PHYS 0x10000000
|
||||
#define PB11MPCORE_DEV_PHYS 0x10000000
|
||||
|
||||
/* Device offsets in physical memory */
|
||||
#define PB926_SYSTEM_REGISTERS 0x10000000 /* System registers */
|
||||
#define PB926_SYSCTRL_BASE 0x101E0000 /* System controller */
|
||||
#define PB926_WATCHDOG_BASE 0x101E1000 /* Watchdog */
|
||||
#define PB926_TIMER01_BASE 0x101E2000 /* Timers 0 and 1 */
|
||||
#define PB926_TIMER23_BASE 0x101E3000 /* Timers 2 and 3 */
|
||||
#define PB926_RTC_BASE 0x101E8000 /* Real Time Clock */
|
||||
#define PB926_VIC_BASE 0x10140000 /* Primary Vectored IC */
|
||||
#define PB926_SIC_BASE 0x10003000 /* Secondary IC */
|
||||
#define PB926_UART0_BASE 0x101F1000 /* Console port (UART0) */
|
||||
#define PB11MPCORE_SYSTEM_REGISTERS 0x10000000 /* System registers */
|
||||
#define PB11MPCORE_SYSCTRL0_BASE 0x10001000 /* System controller 0 */
|
||||
#define PB11MPCORE_UART0_BASE 0x10009000 /* UART 0 */
|
||||
#define PB11MPCORE_UART1_BASE 0x1000A000 /* UART 1 */
|
||||
#define PB11MPCORE_UART2_BASE 0x1000B000 /* UART 2 */
|
||||
#define PB11MPCORE_UART3_BASE 0x1000C000 /* UART 3 */
|
||||
#define PB11MPCORE_WATCHDOG0_BASE 0x1000F000 /* WATCHDOG 0 */
|
||||
#define PB11MPCORE_WATCHDOG1_BASE 0x10010000 /* WATCHDOG 1 */
|
||||
#define PB11MPCORE_TIMER01_BASE 0x10011000 /* TIMER 0-1 */
|
||||
#define PB11MPCORE_TIMER23_BASE 0x10012000 /* TIMER 2-3 */
|
||||
#define PB11MPCORE_RTC_BASE 0x10017000 /* RTC interface */
|
||||
#define PB11MPCORE_TIMER45_BASE 0x10018000 /* TIMER 4-5 */
|
||||
#define PB11MPCORE_TIMER67_BASE 0x10019000 /* TIMER 6-7 */
|
||||
#define PB11MPCORE_SYSCTRL1_BASE 0x1001A000 /* System controller 1 */
|
||||
#define PB11MPCORE_GIC0_BASE 0x1E000000 /* GIC 0 */
|
||||
#define PB11MPCORE_GIC1_BASE 0x1E010000 /* GIC 1 */
|
||||
#define PB11MPCORE_GIC2_BASE 0x1E020000 /* GIC 2 */
|
||||
#define PB11MPCORE_GIC3_BASE 0x1E030000 /* GIC 3 */
|
||||
|
||||
/*
|
||||
* Uart virtual address until a file-based console access
|
||||
@@ -44,17 +53,25 @@
|
||||
* device base address. Each page on this virtual base is consecutively
|
||||
* allocated to devices. Nice and smooth.
|
||||
*/
|
||||
#define PB926_TIMER01_VOFFSET 0x00000000
|
||||
#define PB926_UART0_VOFFSET 0x00001000
|
||||
#define PB926_VIC_VOFFSET 0x00002000
|
||||
#define PB926_SIC_VOFFSET 0x00003000
|
||||
#define PB926_SYSREGS_VOFFSET 0x00005000
|
||||
#define PB926_SYSCTRL_VOFFSET 0x00006000
|
||||
#define PB11MPCORE_SYSREGS_VOFFSET 0x00000000
|
||||
#define PB11MPCORE_SYSCTRL0_VOFFSET 0x00001000
|
||||
#define PB11MPCORE_SYSCTRL1_VOFFSET 0x00002000
|
||||
#define PB11MPCORE_UART0_VOFFSET 0x00003000
|
||||
#define PB11MPCORE_TIMER01_VOFFSET 0x00004000
|
||||
|
||||
#define PB926_UART0_VBASE (IO_AREA0_VADDR + PB926_UART0_VOFFSET)
|
||||
#define PB926_TIMER01_VBASE (IO_AREA0_VADDR + PB926_TIMER01_VOFFSET)
|
||||
#define PB926_SYSCTRL_VBASE (IO_AREA0_VADDR + PB926_SYSCTRL_VOFFSET)
|
||||
#define PB926_VIC_VBASE (IO_AREA0_VADDR + PB926_VIC_VOFFSET)
|
||||
#define PB926_SIC_VBASE (IO_AREA0_VADDR + PB926_SIC_VOFFSET)
|
||||
#endif /* __PLATFORM_PB926_OFFSETS_H__ */
|
||||
#define PB11MPCORE_GIC0_VOFFSET 0x00005000
|
||||
#define PB11MPCORE_GIC1_VOFFSET 0x00006000
|
||||
#define PB11MPCORE_GIC2_VOFFSET 0x00007000
|
||||
#define PB11MPCORE_GIC3_VOFFSET 0x00008000
|
||||
#define PB11MPCORE_SYSREGS_VBASE (IO_AREA0_VADDR + PB11MPCORE_SYSREGS_VOFFSET)
|
||||
#define PB11MPCORE_SYSCTRL0_VBASE (IO_AREA0_VADDR + PB11MPCORE_SYSCTRL0_VOFFSET)
|
||||
#define PB11MPCORE_SYSCTRL1_VBASE (IO_AREA0_VADDR + PB11MPCORE_SYSCTRL1_VOFFSET)
|
||||
#define PB11MPCORE_UART0_VBASE (IO_AREA0_VADDR + PB11MPCORE_UART0_VOFFSET)
|
||||
#define PB11MPCORE_TIMER01_VBASE (IO_AREA0_VADDR + PB11MPCORE_TIMER01_VOFFSET)
|
||||
#define PB11MPCORE_GIC0_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC0_VOFFSET)
|
||||
#define PB11MPCORE_GIC1_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC1_VOFFSET)
|
||||
#define PB11MPCORE_GIC2_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC2_VOFFSET)
|
||||
#define PB11MPCORE_GIC3_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC3_VOFFSET)
|
||||
|
||||
#endif /* __PLATFORM_PB11MPCORE_OFFSETS_H__ */
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
#ifndef __PLATFORM_PB926_PLATFORM_H__
|
||||
#define __PLATFORM_PB926_PLATFORM_H__
|
||||
#ifndef __PLATFORM_PB11MPCORE_PLATFORM_H__
|
||||
#define __PLATFORM_PB11MPCORE_PLATFORM_H__
|
||||
/*
|
||||
* Platform specific ties between drivers and generic APIs used by the kernel.
|
||||
* E.g. system timer and console.
|
||||
@@ -10,13 +10,25 @@
|
||||
#include INC_PLAT(offsets.h)
|
||||
#include INC_GLUE(memlayout.h)
|
||||
|
||||
#define PLATFORM_CONSOLE_BASE PB926_UART0_VBASE
|
||||
#define PLATFORM_TIMER_BASE PB926_TIMER01_VBASE
|
||||
#define PLATFORM_SP810_BASE PB926_SYSCTRL_VBASE
|
||||
#define PLATFORM_IRQCTRL_BASE PB926_VIC_VBASE
|
||||
#define PLATFORM_SIRQCTRL_BASE PB926_SIC_VBASE
|
||||
#define PLATFORM_CONSOLE0_BASE PB11MPCORE_UART0_VBASE
|
||||
#define PLATFORM_TIMER0_BASE PB11MPCORE_TIMER01_VBASE
|
||||
/* Need to add syscntrl1 here */
|
||||
#define PLATFORM_SP810_BASE PB11MPCORE_SYSCTRL0_VBASE
|
||||
|
||||
/* Total number of timers present in this platform */
|
||||
#define TOTAL_TIMERS 8
|
||||
|
||||
#define PLATFORM_TIMER0 0
|
||||
#define PLATFORM_TIMER1 1
|
||||
#define PLATFORM_TIMER2 2
|
||||
#define PLATFORM_TIMER3 3
|
||||
#define PLATFORM_TIMER3 4
|
||||
#define PLATFORM_TIMER3 5
|
||||
#define PLATFORM_TIMER3 6
|
||||
#define PLATFORM_TIMER3 7
|
||||
|
||||
void platform_irq_enable(int irq);
|
||||
void platform_irq_disable(int irq);
|
||||
void timer_start(void);
|
||||
#endif /* __PLATFORM_PB926_PLATFORM_H__ */
|
||||
|
||||
#endif /* __PLATFORM_PB11MPCORE_PLATFORM_H__ */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
#ifndef __PLATFORM__PB926__PRINTASCII__H__
|
||||
#define __PLATFORM__PB926__PRINTASCII__H__
|
||||
#ifndef __PLATFORM__PB11MPCORE__PRINTASCII__H__
|
||||
#define __PLATFORM__PB11MPCORE__PRINTASCII__H__
|
||||
|
||||
#define dprintk(str, val) \
|
||||
{ \
|
||||
@@ -12,4 +12,4 @@
|
||||
void printascii(char *str);
|
||||
void printhex8(unsigned int);
|
||||
|
||||
#endif /* __PLATFORM__PB926__PRINTASCII__H__ */
|
||||
#endif /* __PLATFORM__PB11MPCORE__PRINTASCII__H__ */
|
||||
|
||||
@@ -5,16 +5,16 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_PB926_UART_H__
|
||||
#define __PLATFORM_PB926_UART_H__
|
||||
#ifndef __PLATFORM_PB11MPCORE_UART_H__
|
||||
#define __PLATFORM_PB11MPCORE_UART_H__
|
||||
|
||||
#include INC_PLAT(offsets.h)
|
||||
#include INC_GLUE(memlayout.h)
|
||||
|
||||
#define PLATFORM_CONSOLE_BASE PB926_UART0_VBASE
|
||||
#define PLATFORM_CONSOLE_BASE PB11MPCORE_UART0_VBASE
|
||||
#include <l4/drivers/uart/pl011/pl011_uart.h>
|
||||
|
||||
void uart_init(void);
|
||||
void uart_putc(char c);
|
||||
|
||||
#endif /* __PLATFORM_PB926_UART_H__ */
|
||||
#endif /* __PLATFORM_PB11MPCORE_UART_H__ */
|
||||
|
||||
@@ -1,27 +1,25 @@
|
||||
#ifndef __PLATFORM_IRQ_H__
|
||||
#define __PLATFORM_IRQ_H__
|
||||
|
||||
#define IRQ_CHIPS_MAX 2
|
||||
#define IRQS_MAX 64
|
||||
/* TODO: Not sure about this, need to check */
|
||||
#define IRQ_CHIPS_MAX 4
|
||||
#define IRQS_MAX 96
|
||||
|
||||
/* IRQ indices. */
|
||||
#define IRQ_TIMER01 4
|
||||
#define IRQ_TIMER23 5
|
||||
#define IRQ_RTC 10
|
||||
#define IRQ_UART0 12
|
||||
#define IRQ_UART1 13
|
||||
#define IRQ_UART2 14
|
||||
#define IRQ_SIC 31
|
||||
|
||||
/* Cascading definitions */
|
||||
|
||||
#define PIC_IRQS_MAX 31 /* Total irqs on PIC */
|
||||
/* The local irq line of the dummy peripheral on this chip */
|
||||
#define LOCALIRQ_DUMMY 15
|
||||
/* The irq index offset of this chip, is the maximum of previous chip + 1 */
|
||||
#define SIRQ_CHIP_OFFSET (PIC_IRQS_MAX + 1)
|
||||
/* The global irq number of dummy is the local irq line + it's chip offset */
|
||||
#define IRQ_DUMMY (LOCALIRQ_DUMMY + SIRQ_CHIP_OFFSET)
|
||||
/*
|
||||
* IRQ indices, 32-63 and 72-89 index
|
||||
* available for external sources
|
||||
* 0-32: used for SI, provided by
|
||||
* distributed interrupt controller
|
||||
*/
|
||||
#define IRQ_TIMER01 36
|
||||
#define IRQ_TIMER23 37
|
||||
#define IRQ_TIMER45 73
|
||||
#define IRQ_TIMER67 74
|
||||
#define IRQ_RTC 42
|
||||
#define IRQ_UART0 44
|
||||
#define IRQ_UART1 45
|
||||
#define IRQ_UART2 46
|
||||
#define IRQ_UART3 47
|
||||
|
||||
|
||||
#endif /* __PLATFORM_IRQ_H__ */
|
||||
|
||||
@@ -4,12 +4,12 @@
|
||||
* Copyright (C) 2007 Bahadir Balban
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_PB926_OFFSETS_H__
|
||||
#define __PLATFORM_PB926_OFFSETS_H__
|
||||
#ifndef __PLATFORM_PBA8_OFFSETS_H__
|
||||
#define __PLATFORM_PBA8_OFFSETS_H__
|
||||
|
||||
/* Physical memory base */
|
||||
#define PHYS_MEM_START 0x00000000 /* inclusive */
|
||||
#define PHYS_MEM_END 0x08000000 /* 128 MB, exclusive */
|
||||
#define PHYS_MEM_END 0x10000000 /* 256 MB, exclusive */
|
||||
|
||||
/*
|
||||
* These bases taken from where kernel is `physically' linked at,
|
||||
@@ -20,18 +20,27 @@
|
||||
#define PHYS_ADDR_BASE 0x100000
|
||||
|
||||
/* Device memory base */
|
||||
#define PB926_DEV_PHYS 0x10000000
|
||||
#define PBA8_DEV_PHYS 0x10000000
|
||||
|
||||
/* Device offsets in physical memory */
|
||||
#define PB926_SYSTEM_REGISTERS 0x10000000 /* System registers */
|
||||
#define PB926_SYSCTRL_BASE 0x101E0000 /* System controller */
|
||||
#define PB926_WATCHDOG_BASE 0x101E1000 /* Watchdog */
|
||||
#define PB926_TIMER01_BASE 0x101E2000 /* Timers 0 and 1 */
|
||||
#define PB926_TIMER23_BASE 0x101E3000 /* Timers 2 and 3 */
|
||||
#define PB926_RTC_BASE 0x101E8000 /* Real Time Clock */
|
||||
#define PB926_VIC_BASE 0x10140000 /* Primary Vectored IC */
|
||||
#define PB926_SIC_BASE 0x10003000 /* Secondary IC */
|
||||
#define PB926_UART0_BASE 0x101F1000 /* Console port (UART0) */
|
||||
#define PBA8_SYSTEM_REGISTERS 0x10000000 /* System registers */
|
||||
#define PBA8_SYSCTRL0_BASE 0x10001000 /* System controller 0 */
|
||||
#define PBA8_UART0_BASE 0x10009000 /* UART 0 */
|
||||
#define PBA8_UART1_BASE 0x1000A000 /* UART 1 */
|
||||
#define PBA8_UART2_BASE 0x1000B000 /* UART 2 */
|
||||
#define PBA8_UART3_BASE 0x1000C000 /* UART 3 */
|
||||
#define PBA8_WATCHDOG0_BASE 0x1000F000 /* WATCHDOG 0 */
|
||||
#define PBA8_WATCHDOG1_BASE 0x10010000 /* WATCHDOG 1 */
|
||||
#define PBA8_TIMER01_BASE 0x10011000 /* TIMER 0-1 */
|
||||
#define PBA8_TIMER23_BASE 0x10012000 /* TIMER 2-3 */
|
||||
#define PBA8_RTC_BASE 0x10017000 /* RTC interface */
|
||||
#define PBA8_TIMER45_BASE 0x10018000 /* TIMER 4-5 */
|
||||
#define PBA8_TIMER67_BASE 0x10019000 /* TIMER 6-7 */
|
||||
#define PBA8_SYSCTRL1_BASE 0x1001A000 /* System controller 1 */
|
||||
#define PBA8_GIC0_BASE 0x1E000000 /* GIC 0 */
|
||||
#define PBA8_GIC1_BASE 0x1E010000 /* GIC 1 */
|
||||
#define PBA8_GIC2_BASE 0x1E020000 /* GIC 2 */
|
||||
#define PBA8_GIC3_BASE 0x1E030000 /* GIC 3 */
|
||||
|
||||
/*
|
||||
* Uart virtual address until a file-based console access
|
||||
@@ -44,17 +53,25 @@
|
||||
* device base address. Each page on this virtual base is consecutively
|
||||
* allocated to devices. Nice and smooth.
|
||||
*/
|
||||
#define PB926_TIMER01_VOFFSET 0x00000000
|
||||
#define PB926_UART0_VOFFSET 0x00001000
|
||||
#define PB926_VIC_VOFFSET 0x00002000
|
||||
#define PB926_SIC_VOFFSET 0x00003000
|
||||
#define PB926_SYSREGS_VOFFSET 0x00005000
|
||||
#define PB926_SYSCTRL_VOFFSET 0x00006000
|
||||
#define PBA8_SYSREGS_VOFFSET 0x00000000
|
||||
#define PBA8_SYSCTRL0_VOFFSET 0x00001000
|
||||
#define PBA8_SYSCTRL1_VOFFSET 0x00002000
|
||||
#define PBA8_UART0_VOFFSET 0x00003000
|
||||
#define PBA8_TIMER01_VOFFSET 0x00004000
|
||||
#define PBA8_GIC0_VOFFSET 0x00005000
|
||||
#define PBA8_GIC1_VOFFSET 0x00006000
|
||||
#define PBA8_GIC2_VOFFSET 0x00007000
|
||||
#define PBA8_GIC3_VOFFSET 0x00008000
|
||||
|
||||
#define PB926_UART0_VBASE (IO_AREA0_VADDR + PB926_UART0_VOFFSET)
|
||||
#define PB926_TIMER01_VBASE (IO_AREA0_VADDR + PB926_TIMER01_VOFFSET)
|
||||
#define PB926_SYSCTRL_VBASE (IO_AREA0_VADDR + PB926_SYSCTRL_VOFFSET)
|
||||
#define PB926_VIC_VBASE (IO_AREA0_VADDR + PB926_VIC_VOFFSET)
|
||||
#define PB926_SIC_VBASE (IO_AREA0_VADDR + PB926_SIC_VOFFSET)
|
||||
#endif /* __PLATFORM_PB926_OFFSETS_H__ */
|
||||
#define PBA8_SYSREGS_VBASE (IO_AREA0_VADDR + PBA8_SYSREGS_VOFFSET)
|
||||
#define PBA8_SYSCTRL0_VBASE (IO_AREA0_VADDR + PBA8_SYSCTRL0_VOFFSET)
|
||||
#define PBA8_SYSCTRL1_VBASE (IO_AREA0_VADDR + PBA8_SYSCTRL1_VOFFSET)
|
||||
#define PBA8_UART0_VBASE (IO_AREA0_VADDR + PBA8_UART0_VOFFSET)
|
||||
#define PBA8_TIMER01_VBASE (IO_AREA0_VADDR + PBA8_TIMER01_VOFFSET)
|
||||
#define PBA8_GIC0_VBASE (IO_AREA0_VADDR + PBA8_GIC0_VOFFSET)
|
||||
#define PBA8_GIC1_VBASE (IO_AREA0_VADDR + PBA8_GIC1_VOFFSET)
|
||||
#define PBA8_GIC2_VBASE (IO_AREA0_VADDR + PBA8_GIC2_VOFFSET)
|
||||
#define PBA8_GIC3_VBASE (IO_AREA0_VADDR + PBA8_GIC3_VOFFSET)
|
||||
|
||||
#endif /* __PLATFORM_PBA8_OFFSETS_H__ */
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
#ifndef __PLATFORM_PB926_PLATFORM_H__
|
||||
#define __PLATFORM_PB926_PLATFORM_H__
|
||||
#ifndef __PLATFORM_PBA8_PLATFORM_H__
|
||||
#define __PLATFORM_PBA8_PLATFORM_H__
|
||||
/*
|
||||
* Platform specific ties between drivers and generic APIs used by the kernel.
|
||||
* E.g. system timer and console.
|
||||
@@ -10,13 +10,23 @@
|
||||
#include INC_PLAT(offsets.h)
|
||||
#include INC_GLUE(memlayout.h)
|
||||
|
||||
#define PLATFORM_CONSOLE_BASE PB926_UART0_VBASE
|
||||
#define PLATFORM_TIMER_BASE PB926_TIMER01_VBASE
|
||||
#define PLATFORM_SP810_BASE PB926_SYSCTRL_VBASE
|
||||
#define PLATFORM_IRQCTRL_BASE PB926_VIC_VBASE
|
||||
#define PLATFORM_SIRQCTRL_BASE PB926_SIC_VBASE
|
||||
#define PLATFORM_CONSOLE0_BASE PBA8_UART0_VBASE
|
||||
#define PLATFORM_TIMER0_BASE PBA8_TIMER01_VBASE
|
||||
#define PLATFORM_SP810_BASE PBA8_SYSCTRL0_VBASE
|
||||
|
||||
/* Total number of timers present in this platform */
|
||||
#define TOTAL_TIMERS 8
|
||||
|
||||
#define PLATFORM_TIMER0 0
|
||||
#define PLATFORM_TIMER1 1
|
||||
#define PLATFORM_TIMER2 2
|
||||
#define PLATFORM_TIMER3 3
|
||||
#define PLATFORM_TIMER3 4
|
||||
#define PLATFORM_TIMER3 5
|
||||
#define PLATFORM_TIMER3 6
|
||||
#define PLATFORM_TIMER3 7
|
||||
|
||||
void platform_irq_enable(int irq);
|
||||
void platform_irq_disable(int irq);
|
||||
void timer_start(void);
|
||||
#endif /* __PLATFORM_PB926_PLATFORM_H__ */
|
||||
#endif /* __PLATFORM_PBA8_PLATFORM_H__ */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
#ifndef __PLATFORM__PB926__PRINTASCII__H__
|
||||
#define __PLATFORM__PB926__PRINTASCII__H__
|
||||
#ifndef __PLATFORM__PBA8__PRINTASCII__H__
|
||||
#define __PLATFORM__PBA8__PRINTASCII__H__
|
||||
|
||||
#define dprintk(str, val) \
|
||||
{ \
|
||||
@@ -12,4 +12,4 @@
|
||||
void printascii(char *str);
|
||||
void printhex8(unsigned int);
|
||||
|
||||
#endif /* __PLATFORM__PB926__PRINTASCII__H__ */
|
||||
#endif /* __PLATFORM__PBA8__PRINTASCII__H__ */
|
||||
|
||||
@@ -5,13 +5,13 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_PB926_UART_H__
|
||||
#define __PLATFORM_PB926_UART_H__
|
||||
#ifndef __PLATFORM_PBA8_UART_H__
|
||||
#define __PLATFORM_PBA8_UART_H__
|
||||
|
||||
#include INC_PLAT(offsets.h)
|
||||
#include INC_GLUE(memlayout.h)
|
||||
|
||||
#define PLATFORM_CONSOLE_BASE PB926_UART0_VBASE
|
||||
#define PLATFORM_CONSOLE_BASE PBA8_UART0_VBASE
|
||||
#include <l4/drivers/uart/pl011/pl011_uart.h>
|
||||
|
||||
void uart_init(void);
|
||||
|
||||
Reference in New Issue
Block a user