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Added offsets for MPCORE, EB and CORTEX-A8

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This commit is contained in:
Amit Mahajan
2009-10-29 15:31:06 +05:30
parent e120e7c552
commit d41cac75d1
34 changed files with 382 additions and 288 deletions
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63
include/l4/platform/eb/offsets.h
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@@ -1,15 +1,15 @@
/*
* Describes physical memory layout of pb926 platform.
* Describes physical memory layout of EB platform.
*
* Copyright (C) 2007 Bahadir Balban
*/
#ifndef __PLATFORM_PB926_OFFSETS_H__
#define __PLATFORM_PB926_OFFSETS_H__
#ifndef __PLATFORM_EB_OFFSETS_H__
#define __PLATFORM_EB_OFFSETS_H__
/* Physical memory base */
#define PHYS_MEM_START 0x00000000 /* inclusive */
#define PHYS_MEM_END 0x08000000 /* 128 MB, exclusive */
#define PHYS_MEM_END 0x10000000 /* 256 MB, exclusive */
/*
* These bases taken from where kernel is `physically' linked at,
@@ -20,18 +20,23 @@
#define PHYS_ADDR_BASE 0x100000
/* Device memory base */
#define PB926_DEV_PHYS 0x10000000
#define EB_DEV_PHYS 0x10000000
/* Device offsets in physical memory */
#define PB926_SYSTEM_REGISTERS 0x10000000 /* System registers */
#define PB926_SYSCTRL_BASE 0x101E0000 /* System controller */
#define PB926_WATCHDOG_BASE 0x101E1000 /* Watchdog */
#define PB926_TIMER01_BASE 0x101E2000 /* Timers 0 and 1 */
#define PB926_TIMER23_BASE 0x101E3000 /* Timers 2 and 3 */
#define PB926_RTC_BASE 0x101E8000 /* Real Time Clock */
#define PB926_VIC_BASE 0x10140000 /* Primary Vectored IC */
#define PB926_SIC_BASE 0x10003000 /* Secondary IC */
#define PB926_UART0_BASE 0x101F1000 /* Console port (UART0) */
#define EB_SYSTEM_REGISTERS 0x10000000 /* System registers */
#define EB_SYSCTRL_BASE 0x10001000 /* System controller */
#define EB_UART0_BASE 0x10009000 /* UART 0 */
#define EB_UART1_BASE 0x1000A000 /* UART 1 */
#define EB_UART2_BASE 0x1000B000 /* UART 2 */
#define EB_UART3_BASE 0x1000C000 /* UART 3 */
#define EB_WATCHDOG0_BASE 0x10010000 /* WATCHDOG */
#define EB_TIMER01_BASE 0x10011000 /* TIMER 0-1 */
#define EB_TIMER23_BASE 0x10012000 /* TIMER 2-3 */
#define EB_RTC_BASE 0x10017000 /* RTC interface */
#define EB_GIC0_BASE 0x10040000 /* GIC 0 */
#define EB_GIC1_BASE 0x10050000 /* GIC 1 */
#define EB_GIC2_BASE 0x10060000 /* GIC 2 */
#define EB_GIC3_BASE 0x10070000 /* GIC 3 */
/*
* Uart virtual address until a file-based console access
@@ -44,17 +49,23 @@
* device base address. Each page on this virtual base is consecutively
* allocated to devices. Nice and smooth.
*/
#define PB926_TIMER01_VOFFSET 0x00000000
#define PB926_UART0_VOFFSET 0x00001000
#define PB926_VIC_VOFFSET 0x00002000
#define PB926_SIC_VOFFSET 0x00003000
#define PB926_SYSREGS_VOFFSET 0x00005000
#define PB926_SYSCTRL_VOFFSET 0x00006000
#define EB_SYSREGS_VOFFSET 0x00000000
#define EB_SYSCTRL_VOFFSET 0x00001000
#define EB_UART0_VOFFSET 0x00002000
#define EB_TIMER01_VOFFSET 0x00003000
#define EB_GIC0_VOFFSET 0x00004000
#define EB_GIC1_VOFFSET 0x00005000
#define EB_GIC2_VOFFSET 0x00006000
#define EB_GIC3_VOFFSET 0x00007000
#define PB926_UART0_VBASE (IO_AREA0_VADDR + PB926_UART0_VOFFSET)
#define PB926_TIMER01_VBASE (IO_AREA0_VADDR + PB926_TIMER01_VOFFSET)
#define PB926_SYSCTRL_VBASE (IO_AREA0_VADDR + PB926_SYSCTRL_VOFFSET)
#define PB926_VIC_VBASE (IO_AREA0_VADDR + PB926_VIC_VOFFSET)
#define PB926_SIC_VBASE (IO_AREA0_VADDR + PB926_SIC_VOFFSET)
#endif /* __PLATFORM_PB926_OFFSETS_H__ */
#define EB_SYSREGS_VBASE (IO_AREA0_VADDR + EB_SYSREGS_VOFFSET)
#define EB_SYSCTRL_VBASE (IO_AREA0_VADDR + EB_SYSCTRL0_VOFFSET)
#define EB_UART0_VBASE (IO_AREA0_VADDR + EB_UART0_VOFFSET)
#define EB_TIMER01_VBASE (IO_AREA0_VADDR + EB_TIMER01_VOFFSET)
#define EB_GIC0_VBASE (IO_AREA0_VADDR + EB_GIC0_VOFFSET)
#define EB_GIC1_VBASE (IO_AREA0_VADDR + EB_GIC1_VOFFSET)
#define EB_GIC2_VBASE (IO_AREA0_VADDR + EB_GIC2_VOFFSET)
#define EB_GIC3_VBASE (IO_AREA0_VADDR + EB_GIC3_VOFFSET)
#endif /* __PLATFORM_EB_OFFSETS_H__ */