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Added offsets for MPCORE, EB and CORTEX-A8
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@@ -1,27 +1,25 @@
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#ifndef __PLATFORM_IRQ_H__
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#define __PLATFORM_IRQ_H__
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#define IRQ_CHIPS_MAX 2
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#define IRQS_MAX 64
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/* TODO: Not sure about this, need to check */
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#define IRQ_CHIPS_MAX 4
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#define IRQS_MAX 96
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/* IRQ indices. */
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#define IRQ_TIMER01 4
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#define IRQ_TIMER23 5
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#define IRQ_RTC 10
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#define IRQ_UART0 12
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#define IRQ_UART1 13
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#define IRQ_UART2 14
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#define IRQ_SIC 31
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/* Cascading definitions */
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#define PIC_IRQS_MAX 31 /* Total irqs on PIC */
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/* The local irq line of the dummy peripheral on this chip */
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#define LOCALIRQ_DUMMY 15
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/* The irq index offset of this chip, is the maximum of previous chip + 1 */
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#define SIRQ_CHIP_OFFSET (PIC_IRQS_MAX + 1)
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/* The global irq number of dummy is the local irq line + it's chip offset */
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#define IRQ_DUMMY (LOCALIRQ_DUMMY + SIRQ_CHIP_OFFSET)
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/*
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* IRQ indices, 32-63 and 72-89 index
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* available for external sources
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* 0-32: used for SI, provided by
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* distributed interrupt controller
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*/
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#define IRQ_TIMER01 36
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#define IRQ_TIMER23 37
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#define IRQ_TIMER45 73
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#define IRQ_TIMER67 74
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#define IRQ_RTC 42
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#define IRQ_UART0 44
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#define IRQ_UART1 45
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#define IRQ_UART2 46
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#define IRQ_UART3 47
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#endif /* __PLATFORM_IRQ_H__ */
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