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Added offsets for MPCORE, EB and CORTEX-A8

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This commit is contained in:
Amit Mahajan
2009-10-29 15:31:06 +05:30
parent e120e7c552
commit d41cac75d1
34 changed files with 382 additions and 288 deletions
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2
src/platform/eb/irq.c
View File

@@ -41,7 +41,7 @@ struct irq_chip irq_chip_array[IRQ_CHIPS_MAX] = {
static int platform_timer_handler(void)
{
sp804_irq_handler();
sp804_irq_handler(PLATFORM_TIMER0_BASE);
return do_timer_irq();
}

12
src/platform/eb/platform.c
View File

@@ -1,5 +1,5 @@
/*
* PB926 platform-specific initialisation and setup
* EB platform-specific initialisation and setup
*
* Copyright (C) 2007 Bahadir Balban
*/
@@ -21,7 +21,7 @@
void init_platform_console(void)
{
add_boot_mapping(PB926_UART0_BASE, PL011_BASE, PAGE_SIZE,
add_boot_mapping(EB_UART0_BASE, PLATFORM_CONSOLE0_BASE, PAGE_SIZE,
MAP_IO_DEFAULT_FLAGS);
/*
@@ -29,7 +29,7 @@ void init_platform_console(void)
* userspace printf can work. Note, this raw mapping is to be
* removed in the future, when file-based io is implemented.
*/
add_boot_mapping(PB926_UART0_BASE, USERSPACE_UART_BASE, PAGE_SIZE,
add_boot_mapping(EB_UART0_BASE, USERSPACE_UART_BASE, PAGE_SIZE,
MAP_USR_IO_FLAGS);
uart_init();
@@ -37,20 +37,22 @@ void init_platform_console(void)
void init_platform_timer(void)
{
add_boot_mapping(PB926_TIMER01_BASE, PLATFORM_TIMER_BASE, PAGE_SIZE,
add_boot_mapping(EB_TIMER01_BASE, PLATFORM_TIMER0_BASE, PAGE_SIZE,
MAP_IO_DEFAULT_FLAGS);
add_boot_mapping(PB926_SYSCTRL_BASE, PB926_SYSCTRL_VBASE, PAGE_SIZE,
add_boot_mapping(EB_SYSCTRL_BASE, PB926_SYSCTRL_VBASE, PAGE_SIZE,
MAP_IO_DEFAULT_FLAGS);
timer_init();
}
void init_platform_irq_controller()
{
#if 0
add_boot_mapping(PB926_VIC_BASE, PLATFORM_IRQCTRL_BASE, PAGE_SIZE,
MAP_IO_DEFAULT_FLAGS);
add_boot_mapping(PB926_SIC_BASE, PLATFORM_SIRQCTRL_BASE, PAGE_SIZE,
MAP_IO_DEFAULT_FLAGS);
irq_controllers_init();
#endif
}
void platform_init(void)

19
src/platform/eb/printascii.S
View File

@@ -3,19 +3,24 @@
*/
#include INC_ARCH(asm.h)
#include INC_GLUE(memlayout.h)
#include INC_PLAT(offsets.h)
#include INC_SUBARCH(mm.h)
#define UART_DATA_OFFSET 0x0
/* Physical base address of UART0 */
uart0_phys_base_addr:
.word EB_UART0_BASE
/* Virtual base address of UART0 */
uart0_virtual_base_addr:
.word EB_UART0_VBASE
.macro uart_address rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #0x10000000
orreq \rx, \rx, #0x001F0000
orreq \rx, \rx, #0x00001000
/* FIXME: This offset is incorrect */
movne \rx, #0xf9000000 @#IO_AREA0_VADDR
addne \rx, \rx, #PB926_UART0_VOFFSET @ UART0 page offset from
@ virtual io area base.
moveq \rx, #uart0_phys_base_addr
movne \rx, #uart0_virtual_base_addr
.endm
.macro uart_send, ry, rx

9
src/platform/eb/timer.c
View File

@@ -13,16 +13,17 @@
void timer_init(void)
{
/* Set timer 0 to 1MHz */
sp810_set_timclk(0, 1);
sp810_set_timclk(PLATFORM_TIMER0, 1);
/* Initialise timer */
sp804_init();
sp804_init(PLATFORM_TIMER0_BASE, SP804_TIMER_RUNMODE_PERIODIC, \
SP804_TIMER_WRAPMODE_WRAPPING, SP804_TIMER_WIDTH32BIT, \
SP804_TIMER_IRQENABLE);
}
void timer_start(void)
{
irq_enable(IRQ_TIMER01);
sp804_set_irq(0, 1); /* Enable timer0 irq */
sp804_enable(0, 1); /* Enable timer0 */
sp804_enable(PLATFORM_TIMER0_BASE, 1); /* Enable timer0 */
}

7
src/platform/eb/uart.c
View File

@@ -12,8 +12,9 @@ extern struct pl011_uart uart;
void uart_init()
{
uart.base = PL011_BASE;
uart.ops.initialise(&uart);
/* We are using UART0 for kernel */
uart.base = PLATFORM_CONSOLE0_BASE;
pl011_initialise_device(&uart);
}
/* Generic uart function that lib/putchar.c expects to see implemented */
@@ -22,7 +23,7 @@ void uart_putc(char c)
int res;
/* Platform specific uart implementation */
do {
res = uart.ops.tx_char(c);
res = pl011_tx_char(uart.base, c);
} while (res < 0);
}

2
src/platform/pb11mpcore/irq.c
View File

@@ -41,7 +41,7 @@ struct irq_chip irq_chip_array[IRQ_CHIPS_MAX] = {
static int platform_timer_handler(void)
{
sp804_irq_handler();
sp804_irq_handler(PLATFORM_TIMER0_BASE);
return do_timer_irq();
}

13
src/platform/pb11mpcore/platform.c
View File

@@ -1,5 +1,5 @@
/*
* PB926 platform-specific initialisation and setup
* PB11MPCORE platform-specific initialisation and setup
*
* Copyright (C) 2007 Bahadir Balban
*/
@@ -21,7 +21,7 @@
void init_platform_console(void)
{
add_boot_mapping(PB926_UART0_BASE, PL011_BASE, PAGE_SIZE,
add_boot_mapping(PB11MPCORE_UART0_BASE, PLATFORM_CONSOLE0_BASE, PAGE_SIZE,
MAP_IO_DEFAULT_FLAGS);
/*
@@ -29,7 +29,7 @@ void init_platform_console(void)
* userspace printf can work. Note, this raw mapping is to be
* removed in the future, when file-based io is implemented.
*/
add_boot_mapping(PB926_UART0_BASE, USERSPACE_UART_BASE, PAGE_SIZE,
add_boot_mapping(PBMPCORE_UART0_BASE, USERSPACE_UART_BASE, PAGE_SIZE,
MAP_USR_IO_FLAGS);
uart_init();
@@ -37,20 +37,23 @@ void init_platform_console(void)
void init_platform_timer(void)
{
add_boot_mapping(PB926_TIMER01_BASE, PLATFORM_TIMER_BASE, PAGE_SIZE,
add_boot_mapping(PBMPCORE_TIMER01_BASE, PLATFORM_TIMER0_BASE, PAGE_SIZE,
MAP_IO_DEFAULT_FLAGS);
add_boot_mapping(PB926_SYSCTRL_BASE, PB926_SYSCTRL_VBASE, PAGE_SIZE,
add_boot_mapping(PB926_SYSCTRL_BASE, PB926_SYSCTRL0_VBASE, PAGE_SIZE,
MAP_IO_DEFAULT_FLAGS);
/* TODO: SYSCTRL1 mapping may be needed */
timer_init();
}
void init_platform_irq_controller()
{
#if 0
add_boot_mapping(PB926_VIC_BASE, PLATFORM_IRQCTRL_BASE, PAGE_SIZE,
MAP_IO_DEFAULT_FLAGS);
add_boot_mapping(PB926_SIC_BASE, PLATFORM_SIRQCTRL_BASE, PAGE_SIZE,
MAP_IO_DEFAULT_FLAGS);
irq_controllers_init();
#endif
}
void platform_init(void)

19
src/platform/pb11mpcore/printascii.S
View File

@@ -3,19 +3,24 @@
*/
#include INC_ARCH(asm.h)
#include INC_GLUE(memlayout.h)
#include INC_PLAT(offsets.h)
#include INC_SUBARCH(mm.h)
#define UART_DATA_OFFSET 0x0
/* Physical base address of UART0 */
uart0_phys_base_addr:
.word PB11MPCORE_UART0_BASE
/* Virtual base address of UART0 */
uart0_virtual_base_addr:
.word PB11MPCORE_UART0_VBASE
.macro uart_address rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #0x10000000
orreq \rx, \rx, #0x001F0000
orreq \rx, \rx, #0x00001000
/* FIXME: This offset is incorrect */
movne \rx, #0xf9000000 @#IO_AREA0_VADDR
addne \rx, \rx, #PB926_UART0_VOFFSET @ UART0 page offset from
@ virtual io area base.
moveq \rx, #uart0_phys_base_addr
movne \rx, #uart0_virtual_base_addr
.endm
.macro uart_send, ry, rx

10
src/platform/pb11mpcore/timer.c
View File

@@ -13,16 +13,18 @@
void timer_init(void)
{
/* Set timer 0 to 1MHz */
sp810_set_timclk(0, 1);
sp810_set_timclk(PLATFORM_TIMER0_BASE, 1);
/* Initialise timer */
sp804_init();
sp804_init(PLATFORM_TIMER0_BASE, SP804_TIMER_RUNMODE_PERIODIC, \
SP804_TIMER_WRAPMODE_WRAPPING, SP804_TIMER_WIDTH32BIT, \
SP804_TIMER_IRQENABLE);
}
void timer_start(void)
{
irq_enable(IRQ_TIMER01);
sp804_set_irq(0, 1); /* Enable timer0 irq */
sp804_enable(0, 1); /* Enable timer0 */
sp804_enable(PLATFORM_TIMER0_BASE, 1); /* Enable timer0 */
}

7
src/platform/pb11mpcore/uart.c
View File

@@ -12,8 +12,9 @@ extern struct pl011_uart uart;
void uart_init()
{
uart.base = PL011_BASE;
uart.ops.initialise(&uart);
/* We are using UART0 for kernel */
uart.base = PLATFORM_CONSOLE0_BASE;
pl011_initialise_device(&uart);
}
/* Generic uart function that lib/putchar.c expects to see implemented */
@@ -22,7 +23,7 @@ void uart_putc(char c)
int res;
/* Platform specific uart implementation */
do {
res = uart.ops.tx_char(c);
res = pl011_tx_char(uart.base, c);
} while (res < 0);
}

19
src/platform/pb926/printascii.S
View File

@@ -3,19 +3,24 @@
*/
#include INC_ARCH(asm.h)
#include INC_GLUE(memlayout.h)
#include INC_PLAT(offsets.h)
#include INC_SUBARCH(mm.h)
#define UART_DATA_OFFSET 0x0
/* Physical base address of UART0 */
uart0_phys_base_addr:
.word PB926_UART0_BASE
/* Virtual base address of UART0 */
uart0_virtual_base_addr:
.word PB926_UART0_VBASE
.macro uart_address rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #0x10000000
orreq \rx, \rx, #0x001F0000
orreq \rx, \rx, #0x00001000
/* FIXME: This offset is incorrect */
movne \rx, #0xf9000000 @#IO_AREA0_VADDR
addne \rx, \rx, #PB926_UART0_VOFFSET @ UART0 page offset from
@ virtual io area base.
moveq \rx, #uart0_phys_base_addr
movne \rx, #uart0_virtual_base_addr
.endm
.macro uart_send, ry, rx

2
src/platform/pb926/uart.c
View File

@@ -23,7 +23,7 @@ void uart_putc(char c)
int res;
/* Platform specific uart implementation */
do {
res =pl011_tx_char(uart.base, c);
res = pl011_tx_char(uart.base, c);
} while (res < 0);
}

2
src/platform/pba8/irq.c
View File

@@ -41,7 +41,7 @@ struct irq_chip irq_chip_array[IRQ_CHIPS_MAX] = {
static int platform_timer_handler(void)
{
sp804_irq_handler();
sp804_irq_handler(PLATFORM_TIMER0_BASE);
return do_timer_irq();
}

13
src/platform/pba8/platform.c
View File

@@ -1,5 +1,5 @@
/*
* PB926 platform-specific initialisation and setup
* PBA8 platform-specific initialisation and setup
*
* Copyright (C) 2007 Bahadir Balban
*/
@@ -21,7 +21,7 @@
void init_platform_console(void)
{
add_boot_mapping(PB926_UART0_BASE, PL011_BASE, PAGE_SIZE,
add_boot_mapping(PBA8_UART0_BASE, PLATFORM_CONSOLE0_BASE, PAGE_SIZE,
MAP_IO_DEFAULT_FLAGS);
/*
@@ -29,7 +29,7 @@ void init_platform_console(void)
* userspace printf can work. Note, this raw mapping is to be
* removed in the future, when file-based io is implemented.
*/
add_boot_mapping(PB926_UART0_BASE, USERSPACE_UART_BASE, PAGE_SIZE,
add_boot_mapping(PBA8_UART0_BASE, USERSPACE_UART_BASE, PAGE_SIZE,
MAP_USR_IO_FLAGS);
uart_init();
@@ -37,20 +37,23 @@ void init_platform_console(void)
void init_platform_timer(void)
{
add_boot_mapping(PB926_TIMER01_BASE, PLATFORM_TIMER_BASE, PAGE_SIZE,
add_boot_mapping(PBA8_TIMER01_BASE, PLATFORM_TIMER0_BASE, PAGE_SIZE,
MAP_IO_DEFAULT_FLAGS);
add_boot_mapping(PB926_SYSCTRL_BASE, PB926_SYSCTRL_VBASE, PAGE_SIZE,
add_boot_mapping(PBA8_SYSCTRL_BASE, PB926_SYSCTRL0_VBASE, PAGE_SIZE,
MAP_IO_DEFAULT_FLAGS);
/* TODO: May need mapping for SYSCTRL1 */
timer_init();
}
void init_platform_irq_controller()
{
#if 0
add_boot_mapping(PB926_VIC_BASE, PLATFORM_IRQCTRL_BASE, PAGE_SIZE,
MAP_IO_DEFAULT_FLAGS);
add_boot_mapping(PB926_SIC_BASE, PLATFORM_SIRQCTRL_BASE, PAGE_SIZE,
MAP_IO_DEFAULT_FLAGS);
irq_controllers_init();
#endif
}
void platform_init(void)

19
src/platform/pba8/printascii.S
View File

@@ -3,19 +3,24 @@
*/
#include INC_ARCH(asm.h)
#include INC_GLUE(memlayout.h)
#include INC_PLAT(offsets.h)
#include INC_SUBARCH(mm.h)
#define UART_DATA_OFFSET 0x0
/* Physical base address of UART0 */
uart0_phys_base_addr:
.word PBA8_UART0_BASE
/* Virtual base address of UART0 */
uart0_virtual_base_addr:
.word PBA8_UART0_VBASE
.macro uart_address rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #0x10000000
orreq \rx, \rx, #0x001F0000
orreq \rx, \rx, #0x00001000
/* FIXME: This offset is incorrect */
movne \rx, #0xf9000000 @#IO_AREA0_VADDR
addne \rx, \rx, #PB926_UART0_VOFFSET @ UART0 page offset from
@ virtual io area base.
moveq \rx, #uart0_phys_base_addr
movne \rx, #uart0_virtual_base_addr
.endm
.macro uart_send, ry, rx

10
src/platform/pba8/timer.c
View File

@@ -13,16 +13,18 @@
void timer_init(void)
{
/* Set timer 0 to 1MHz */
sp810_set_timclk(0, 1);
sp810_set_timclk(PLATFORM_TIMER0, 1);
/* Initialise timer */
sp804_init();
sp804_init(PLATFORM_TIMER0_BASE, SP804_TIMER_RUNMODE_PERIODIC, \
SP804_TIMER_WRAPMODE_WRAPPING, SP804_TIMER_WIDTH32BIT, \
SP804_TIMER_IRQENABLE);
}
void timer_start(void)
{
irq_enable(IRQ_TIMER01);
sp804_set_irq(0, 1); /* Enable timer0 irq */
sp804_enable(0, 1); /* Enable timer0 */
sp804_enable(PLATFORM_TIMER0, 1); /* Enable timer0 */
}

7
src/platform/pba8/uart.c
View File

@@ -12,8 +12,9 @@ extern struct pl011_uart uart;
void uart_init()
{
uart.base = PL011_BASE;
uart.ops.initialise(&uart);
/* We are using UART0 for kernel */
uart.base = PLATFORM_CONSOLE0_BASE;
pl011_initialise_device(&uart);
}
/* Generic uart function that lib/putchar.c expects to see implemented */
@@ -22,7 +23,7 @@ void uart_putc(char c)
int res;
/* Platform specific uart implementation */
do {
res = uart.ops.tx_char(c);
res = pl011_tx_char(uart.base, c);
} while (res < 0);
}