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Bahadir Balban
143
include/l4/arch/arm/asm.h
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143
include/l4/arch/arm/asm.h
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/*********************************************************************
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*
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* Copyright (C) 2003-2005, National ICT Australia (NICTA)
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*
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* File path: arch/arm/asm.h
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* Description: Assembler macros etc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: asm.h,v 1.4 2004/12/02 00:15:07 cvansch Exp $
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*
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********************************************************************/
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#ifndef __ARCH_ARM_ASM_H__
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#define __ARCH_ARM_ASM_H__
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/* Top nibble of the byte denotes irqs/fiqs disabled, ARM state */
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#define ARM_MODE_MASK 0x1F
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#define ARM_MODE_SVC 0x13
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#define ARM_MODE_UND 0x1B
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#define ARM_MODE_ABT 0x17
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#define ARM_MODE_IRQ 0x12
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#define ARM_MODE_FIQ 0x11
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#define ARM_MODE_USR 0x10
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#define ARM_MODE_SYS 0x1F
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#define ARM_NOIRQ_SVC 0xD3
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#define ARM_NOIRQ_UND 0xDB
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#define ARM_NOIRQ_ABT 0xD7
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#define ARM_NOIRQ_IRQ 0xD2
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#define ARM_NOIRQ_FIQ 0xD1
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#define ARM_NOIRQ_USR 0xD0
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#define ARM_NOIRQ_SYS 0xDF
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/* For enabling *clear* these bits */
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#define ARM_IRQ_BIT 0x80
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#define ARM_FIQ_BIT 0x40
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/* Notes about ARM instructions:
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*
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* TST instruction:
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*
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* Essentially TST "AND"s two values and the result affects the Z (Zero bit)
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* in CPSR, which can be used for conditions. For example in:
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*
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* TST r0, #VALUE
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*
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* If anding r0 and #VALUE results in a positive value (i.e. they have a
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* common bit set as 1) then Z bit is 0, which accounts for an NE (Not equal)
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* condition. Consequently, e.g. a BEQ instruction would be skipped and a BNE
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* would be executed.
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*
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* In the opposite case, r0 and #VALUE has no common bits, and anding them
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* results in 0. This means Z bit is 1, and any EQ instruction coming afterwards
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* would be executed.
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*
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* I have made this explanation here because I think the behaviour of the Z bit
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* is kind of hacky in TST. Normally Z bit is used for equivalence (e.g. CMP
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* instruction) but in TST case even if two values were equal the Z bit could
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* point to an NE or EQ condition depending on whether the values have non-zero
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* bits.
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*/
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#define dbg_stop_here() __asm__ __volatile__ ( "bkpt #0\n" :: )
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#define BEGIN_PROC(name) \
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.global name; \
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.type name,function; \
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.align; \
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name:
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#define END_PROC(name) \
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.fend_##name: \
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.size name,.fend_##name - name;
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/* Functions to generate symbols in the output file
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* with correct relocated address for debugging
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*/
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#define TRAPS_BEGIN_MARKER \
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.balign 4096; \
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.section .data.traps; \
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__vector_vaddr:
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#define VECTOR_WORD(name) \
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.equ vector_##name, (name - __vector_vaddr + 0xffff0000); \
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.global vector_##name; \
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.type vector_##name,object; \
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.size vector_##name,4; \
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name:
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/* NOTE: These are fairly useless vector relocation macros. Why? Because
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* ARM branch instructions are *relative* anyway. */
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#define BEGIN_PROC_TRAPS(name) \
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.global name; \
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.type name,function; \
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.equ vector_##name, (name - __vector_vaddr + 0xffff0000); \
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.global vector_##name; \
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.type vector_##name,function; \
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.align; \
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name:
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#define END_PROC_TRAPS(name) \
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.fend_##name: \
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.equ .fend_vector_##name, (.fend_##name - __vector_vaddr + 0xffff0000); \
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.size name,.fend_##name - name; \
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.size vector_##name,.fend_vector_##name - vector_##name;
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#define BEGIN_PROC_KIP(name) \
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.global name; \
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.type name,function; \
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.align; \
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name:
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#define END_PROC_KIP(name) \
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.fend_##name: \
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.size name,.fend_##name - name;
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#define CHECK_ARG(a, b) \
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" .ifnc " a ", " b " \n" \
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" .err \n" \
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" .endif \n" \
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#endif /* __ARCH_ARM_ASM_H__ */
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