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Pl011 uart driver made generic

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This commit is contained in:
Amit Mahajan
2009-10-24 20:24:17 +05:30
parent 8a586860b3
commit e9dba944e6
6 changed files with 193 additions and 238 deletions
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262
include/l4/drivers/uart/pl011/pl011_uart.h
View File

@@ -17,24 +17,22 @@
#include INC_PLAT(uart.h)
#include INC_ARCH(io.h)
#define PL011_BASE PLATFORM_CONSOLE_BASE
/* Register offsets */
#define PL011_UARTDR (PL011_BASE + 0x00)
#define PL011_UARTRSR (PL011_BASE + 0x04)
#define PL011_UARTECR (PL011_BASE + 0x04)
#define PL011_UARTFR (PL011_BASE + 0x18)
#define PL011_UARTILPR (PL011_BASE + 0x20)
#define PL011_UARTIBRD (PL011_BASE + 0x24)
#define PL011_UARTFBRD (PL011_BASE + 0x28)
#define PL011_UARTLCR_H (PL011_BASE + 0x2C)
#define PL011_UARTCR (PL011_BASE + 0x30)
#define PL011_UARTIFLS (PL011_BASE + 0x34)
#define PL011_UARTIMSC (PL011_BASE + 0x38)
#define PL011_UARTRIS (PL011_BASE + 0x3C)
#define PL011_UARTMIS (PL011_BASE + 0x40)
#define PL011_UARTICR (PL011_BASE + 0x44)
#define PL011_UARTDMACR (PL011_BASE + 0x48)
#define PL011_UARTDR 0x00
#define PL011_UARTRSR 0x04
#define PL011_UARTECR 0x04
#define PL011_UARTFR 0x18
#define PL011_UARTILPR 0x20
#define PL011_UARTIBRD 0x24
#define PL011_UARTFBRD 0x28
#define PL011_UARTLCR_H 0x2C
#define PL011_UARTCR 0x30
#define PL011_UARTIFLS 0x34
#define PL011_UARTIMSC 0x38
#define PL011_UARTRIS 0x3C
#define PL011_UARTMIS 0x40
#define PL011_UARTICR 0x44
#define PL011_UARTDMACR 0x48
/* IRQ bits for each uart irq event */
#define PL011_RXIRQ (1 << 4)
@@ -49,39 +47,23 @@ struct pl011_uart;
void pl011_initialise_driver();
int pl011_initialise_device(struct pl011_uart *);
int pl011_initialise_device(struct pl011_uart * uart);
int pl011_tx_char(char);
int pl011_rx_char(char *);
int pl011_tx_char(unsigned int base, char c);
int pl011_rx_char(unsigned int base, char *c);
void pl011_set_baudrate(unsigned int, unsigned int);
void pl011_set_irq_mask(unsigned int);
void pl011_clr_irq_mask(unsigned int);
void pl011_set_baudrate(unsigned int base, unsigned int baud, \
unsigned int clkrate);
void pl011_set_irq_mask(unsigned int base, unsigned int flags);
void pl011_clr_irq_mask(unsigned int base, unsigned int flags);
void pl011_irq_handler(struct pl011_uart *);
void pl011_tx_irq_handler(struct pl011_uart *, unsigned int);
void pl011_rx_irq_handler(struct pl011_uart *, unsigned int);
void pl011_error_irq_handler(struct pl011_uart *, unsigned int);
struct pl011_uart_ops {
int (*initialise)(struct pl011_uart *);
int (*tx_char)(char);
int (*rx_char)(char *);
void (*set_baudrate)(unsigned int, unsigned int);
void (*set_irq_mask)(unsigned int);
void (*clr_irq_mask)(unsigned int);
void (*irq_handler)(struct pl011_uart *);
void (*tx_irq_handler)(struct pl011_uart *, unsigned int);
void (*rx_irq_handler)(struct pl011_uart *, unsigned int);
void (*error_irq_handler)(struct pl011_uart *, unsigned int);
};
void pl011_irq_handler(struct pl011_uart * uart);
void pl011_tx_irq_handler(struct pl011_uart * uart, unsigned int flags);
void pl011_rx_irq_handler(struct pl011_uart *uart, unsigned int flags);
void pl011_error_irq_handler(struct pl011_uart *uart, unsigned int flags);
struct pl011_uart {
unsigned int base;
struct pl011_uart_ops ops;
unsigned int frame_errors;
unsigned int parity_errors;
unsigned int break_errors;
@@ -90,177 +72,166 @@ struct pl011_uart {
};
#define PL011_UARTEN (1 << 0)
static inline void pl011_uart_enable()
static inline void pl011_uart_enable(unsigned int uart_base)
{
unsigned int val;
val = 0;
read(val, PL011_UARTCR);
read(val, (uart_base + PL011_UARTCR));
val |= PL011_UARTEN;
write(val, PL011_UARTCR);
write(val, (uart_base + PL011_UARTCR));
return;
}
static inline void pl011_uart_disable()
static inline void pl011_uart_disable(unsigned int uart_base)
{
unsigned int val;
val = 0;
unsigned int val = 0;
read(val, PL011_UARTCR);
read(val, (uart_base + PL011_UARTCR));
val &= ~PL011_UARTEN;
write(val, PL011_UARTCR);
write(val, (uart_base + PL011_UARTCR));
return;
}
#define PL011_TXE (1 << 8)
static inline void pl011_tx_enable()
static inline void pl011_tx_enable(unsigned int uart_base)
{
unsigned int val;
val = 0;
unsigned int val = 0;
read(val, PL011_UARTCR);
read(val, (uart_base + PL011_UARTCR));
val |= PL011_TXE;
write(val, PL011_UARTCR);
write(val, (uart_base + PL011_UARTCR));
return;
}
static inline void pl011_tx_disable()
static inline void pl011_tx_disable(unsigned int uart_base)
{
unsigned int val;
val = 0;
unsigned int val = 0;
read(val, PL011_UARTCR);
read(val, (uart_base + PL011_UARTCR));
val &= ~PL011_TXE;
write(val, PL011_UARTCR);
write(val, (uart_base + PL011_UARTCR));
return;
}
#define PL011_RXE (1 << 9)
static inline void pl011_rx_enable()
static inline void pl011_rx_enable(unsigned int uart_base)
{
unsigned int val;
val = 0;
unsigned int val = 0;
read(val, PL011_UARTCR);
read(val, (uart_base + PL011_UARTCR));
val |= PL011_RXE;
write(val, PL011_UARTCR);
write(val, (uart_base + PL011_UARTCR));
return;
}
static inline void pl011_rx_disable()
static inline void pl011_rx_disable(unsigned int uart_base)
{
unsigned int val;
val = 0;
unsigned int val = 0;
read(val, PL011_UARTCR);
read(val, (uart_base + PL011_UARTCR));
val &= ~PL011_RXE;
write(val, PL011_UARTCR);
write(val, (uart_base + PL011_UARTCR));
return;
}
#define PL011_TWO_STOPBITS_SELECT (1 << 3)
static inline void pl011_set_stopbits(int stopbits)
static inline void pl011_set_stopbits(unsigned int uart_base, int stopbits)
{
unsigned int val;
val = 0;
unsigned int val = 0;
read(val, PL011_UARTLCR_H);
read(val, (uart_base + PL011_UARTLCR_H));
if(stopbits == 2) { /* Set to two bits */
if(stopbits == 2) {
/* Set to two bits */
val |= PL011_TWO_STOPBITS_SELECT;
} else { /* Default is 1 */
} else {
/* Default is 1 */
val &= ~PL011_TWO_STOPBITS_SELECT;
}
write(val, PL011_UARTLCR_H);
write(val, (uart_base + PL011_UARTLCR_H));
return;
}
#define PL011_PARITY_ENABLE (1 << 1)
static inline void pl011_parity_enable()
static inline void pl011_parity_enable(unsigned int uart_base)
{
unsigned int val;
val = 0;
unsigned int val = 0;
read(val, PL011_UARTLCR_H);
read(val, (uart_base + PL011_UARTLCR_H));
val |= PL011_PARITY_ENABLE;
write(val, PL011_UARTLCR_H);
write(val, (uart_base + PL011_UARTLCR_H));
return;
}
static inline void pl011_parity_disable()
static inline void pl011_parity_disable(unsigned int uart_base)
{
unsigned int val;
val = 0;
unsigned int val = 0;
read(val, PL011_UARTLCR_H);
read(val, (uart_base + PL011_UARTLCR_H));
val &= ~PL011_PARITY_ENABLE;
write(val, PL011_UARTLCR_H);
write(val, (uart_base + PL011_UARTLCR_H));
return;
}
#define PL011_PARITY_EVEN (1 << 2)
static inline void pl011_set_parity_even()
static inline void pl011_set_parity_even(unsigned int uart_base)
{
unsigned int val;
val = 0;
unsigned int val = 0;
read(val, PL011_UARTLCR_H);
read(val, (uart_base + PL011_UARTLCR_H));
val |= PL011_PARITY_EVEN;
write(val, PL011_UARTLCR_H);
write(val, (uart_base + PL011_UARTLCR_H));
return;
}
static inline void pl011_set_parity_odd()
static inline void pl011_set_parity_odd(unsigned int uart_base)
{
unsigned int val;
val = 0;
unsigned int val = 0;
read(val, PL011_UARTLCR_H);
read(val, (uart_base + PL011_UARTLCR_H));
val &= ~PL011_PARITY_EVEN;
write(val, PL011_UARTLCR_H);
write(val, (uart_base + PL011_UARTLCR_H));
return;
}
#define PL011_ENABLE_FIFOS (1 << 4)
static inline void pl011_enable_fifos()
static inline void pl011_enable_fifos(unsigned int uart_base)
{
unsigned int val;
val = 0;
unsigned int val = 0;
read(val, PL011_UARTLCR_H);
read(val, (uart_base + PL011_UARTLCR_H));
val |= PL011_ENABLE_FIFOS;
write(val, PL011_UARTLCR_H);
write(val, (uart_base + PL011_UARTLCR_H));
return;
}
static inline void pl011_disable_fifos()
static inline void pl011_disable_fifos(unsigned int uart_base)
{
unsigned int val;
val = 0;
unsigned int val = 0;
read(val, PL011_UARTLCR_H);
read(val, (uart_base + PL011_UARTLCR_H));
val &= ~PL011_ENABLE_FIFOS;
write(val, PL011_UARTLCR_H);
write(val, (uart_base + PL011_UARTLCR_H));
return;
}
#define PL011_WORD_WIDTH_SHIFT (5)
/* Sets the transfer word width for the data register. */
static inline void pl011_set_word_width(int size)
static inline void pl011_set_word_width(unsigned int uart_base, int size)
{
unsigned int val;
val = 0;
unsigned int val = 0;
if(size < 5 || size > 8) /* Default is 8 */
size = 8;
/* Clear size field */
read(val, PL011_UARTLCR_H);
read(val, (uart_base + PL011_UARTLCR_H));
val &= ~(0x3 << PL011_WORD_WIDTH_SHIFT);
write(val, PL011_UARTLCR_H);
write(val, (uart_base + PL011_UARTLCR_H));
/* The formula is to write 5 less of size given:
* 11 = 8 bits
@@ -268,9 +239,9 @@ static inline void pl011_set_word_width(int size)
* 01 = 6 bits
* 00 = 5 bits
*/
read(val, PL011_UARTLCR_H);
read(val, (uart_base + PL011_UARTLCR_H));
val |= (size - 5) << PL011_WORD_WIDTH_SHIFT;
write(val, PL011_UARTLCR_H);
write(val, (uart_base + PL011_UARTLCR_H));
return;
}
@@ -286,41 +257,40 @@ static inline void pl011_set_word_width(int size)
* 4 rxfifo >= 7/8 full txfifo <= 7/8 full
* 5-7 reserved reserved
*/
static inline void pl011_set_irq_fifolevel(unsigned int xfer, unsigned int level)
static inline void pl011_set_irq_fifolevel(unsigned int uart_base, \
unsigned int xfer, unsigned int level)
{
if(xfer != 1 && xfer != 0) /* Invalid fifo */
return;
if(level > 4) /* Invalid level */
return;
write(level << (xfer * 3), PL011_UARTIFLS);
write(level << (xfer * 3), (uart_base + PL011_UARTIFLS));
return;
}
/* returns which irqs are masked */
static inline unsigned int pl011_read_irqmask(void)
static inline unsigned int pl011_read_irqmask(unsigned int uart_base)
{
unsigned int flags;
read(flags, PL011_UARTIMSC);
read(flags, (uart_base + PL011_UARTIMSC));
return flags;
}
/* returns masked irq status */
static inline unsigned int pl011_read_irqstat(void)
static inline unsigned int pl011_read_irqstat(unsigned int uart_base)
{
unsigned int irqstatus;
read(irqstatus, PL011_UARTMIS);
read(irqstatus, (uart_base + PL011_UARTMIS));
return irqstatus;
}
/* Clears the given asserted irqs */
static inline void pl011_irq_clear(unsigned int flags)
static inline void pl011_irq_clear(unsigned int uart_base, unsigned int flags)
{
if(flags > 0x3FF) { /* Invalid irq clearing bitvector */
return;
}
/* Simply write the flags since it's a write-only register */
write(flags, PL011_UARTICR);
write(flags, (uart_base + PL011_UARTICR));
return;
}
@@ -330,51 +300,45 @@ static inline void pl011_irq_clear(unsigned int flags)
/* Enables dma transfers for uart. The dma controller
* must be initialised, set-up and enabled separately.
*/
static inline void pl011_tx_dma_enable()
static inline void pl011_tx_dma_enable(unsigned int uart_base)
{
unsigned int val;
val = 0;
unsigned int val = 0;
read(val, PL011_UARTDMACR);
read(val, (uart_base + PL011_UARTDMACR));
val |= PL011_TXDMAEN;
write(val, PL011_UARTDMACR);
write(val, (uart_base + PL011_UARTDMACR));
return;
}
/* Disables dma transfers for uart */
static inline void pl011_tx_dma_disable()
static inline void pl011_tx_dma_disable(unsigned int uart_base)
{
unsigned int val;
val = 0;
unsigned int val = 0;
read(val, PL011_UARTDMACR);
read(val, (uart_base + PL011_UARTDMACR));
val &= ~PL011_TXDMAEN;
write(val, PL011_UARTDMACR);
write(val, (uart_base + PL011_UARTDMACR));
return;
}
static inline void pl011_rx_dma_enable()
static inline void pl011_rx_dma_enable(unsigned int uart_base)
{
unsigned int val;
val = 0;
unsigned int val = 0;
read(val, PL011_UARTDMACR);
read(val, (uart_base + PL011_UARTDMACR));
val |= PL011_RXDMAEN;
write(val, PL011_UARTDMACR);
write(val, (uart_base + PL011_UARTDMACR));
return;
}
static inline void pl011_rx_dma_disable()
static inline void pl011_rx_dma_disable(unsigned int uart_base)
{
unsigned int val;
val = 0;
unsigned int val = 0;
read(val, PL011_UARTDMACR);
read(val, (uart_base + PL011_UARTDMACR));
val &= ~PL011_RXDMAEN;
write(val, PL011_UARTDMACR);
write(val, (uart_base + PL011_UARTDMACR));
return;
}
#endif /* __PL011_UART__ */

3
include/l4/platform/pb926/offsets.h
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@@ -32,6 +32,9 @@
#define PB926_VIC_BASE 0x10140000 /* Primary Vectored IC */
#define PB926_SIC_BASE 0x10003000 /* Secondary IC */
#define PB926_UART0_BASE 0x101F1000 /* Console port (UART0) */
#define PB926_UART1_BASE 0x101F2000 /* Console port (UART1) */
#define PB926_UART2_BASE 0x101F3000 /* Console port (UART2) */
#define PB926_UART3_BASE 0x10009000 /* Console port (UART3) */
/*
* Uart virtual address until a file-based console access

2
include/l4/platform/pb926/platform.h
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@@ -10,7 +10,7 @@
#include INC_PLAT(offsets.h)
#include INC_GLUE(memlayout.h)
#define PLATFORM_CONSOLE_BASE PB926_UART0_VBASE
#define PLATFORM_CONSOLE0_BASE PB926_UART0_VBASE
/* SP804 timer has TIMER1 at TIMER0 + 0x20 address */
#define PLATFORM_TIMER0_BASE PB926_TIMER01_VBASE