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Pl011 uart driver made generic

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This commit is contained in:
Amit Mahajan
2009-10-24 20:24:17 +05:30
parent 8a586860b3
commit e9dba944e6
6 changed files with 193 additions and 238 deletions
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262
include/l4/drivers/uart/pl011/pl011_uart.h
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@@ -17,24 +17,22 @@
#include INC_PLAT(uart.h) #include INC_PLAT(uart.h)
#include INC_ARCH(io.h) #include INC_ARCH(io.h)
#define PL011_BASE PLATFORM_CONSOLE_BASE
/* Register offsets */ /* Register offsets */
#define PL011_UARTDR (PL011_BASE + 0x00) #define PL011_UARTDR 0x00
#define PL011_UARTRSR (PL011_BASE + 0x04) #define PL011_UARTRSR 0x04
#define PL011_UARTECR (PL011_BASE + 0x04) #define PL011_UARTECR 0x04
#define PL011_UARTFR (PL011_BASE + 0x18) #define PL011_UARTFR 0x18
#define PL011_UARTILPR (PL011_BASE + 0x20) #define PL011_UARTILPR 0x20
#define PL011_UARTIBRD (PL011_BASE + 0x24) #define PL011_UARTIBRD 0x24
#define PL011_UARTFBRD (PL011_BASE + 0x28) #define PL011_UARTFBRD 0x28
#define PL011_UARTLCR_H (PL011_BASE + 0x2C) #define PL011_UARTLCR_H 0x2C
#define PL011_UARTCR (PL011_BASE + 0x30) #define PL011_UARTCR 0x30
#define PL011_UARTIFLS (PL011_BASE + 0x34) #define PL011_UARTIFLS 0x34
#define PL011_UARTIMSC (PL011_BASE + 0x38) #define PL011_UARTIMSC 0x38
#define PL011_UARTRIS (PL011_BASE + 0x3C) #define PL011_UARTRIS 0x3C
#define PL011_UARTMIS (PL011_BASE + 0x40) #define PL011_UARTMIS 0x40
#define PL011_UARTICR (PL011_BASE + 0x44) #define PL011_UARTICR 0x44
#define PL011_UARTDMACR (PL011_BASE + 0x48) #define PL011_UARTDMACR 0x48
/* IRQ bits for each uart irq event */ /* IRQ bits for each uart irq event */
#define PL011_RXIRQ (1 << 4) #define PL011_RXIRQ (1 << 4)
@@ -49,39 +47,23 @@ struct pl011_uart;
void pl011_initialise_driver(); void pl011_initialise_driver();
int pl011_initialise_device(struct pl011_uart *); int pl011_initialise_device(struct pl011_uart * uart);
int pl011_tx_char(char); int pl011_tx_char(unsigned int base, char c);
int pl011_rx_char(char *); int pl011_rx_char(unsigned int base, char *c);
void pl011_set_baudrate(unsigned int, unsigned int); void pl011_set_baudrate(unsigned int base, unsigned int baud, \
void pl011_set_irq_mask(unsigned int); unsigned int clkrate);
void pl011_clr_irq_mask(unsigned int); void pl011_set_irq_mask(unsigned int base, unsigned int flags);
void pl011_clr_irq_mask(unsigned int base, unsigned int flags);
void pl011_irq_handler(struct pl011_uart *); void pl011_irq_handler(struct pl011_uart * uart);
void pl011_tx_irq_handler(struct pl011_uart *, unsigned int); void pl011_tx_irq_handler(struct pl011_uart * uart, unsigned int flags);
void pl011_rx_irq_handler(struct pl011_uart *, unsigned int); void pl011_rx_irq_handler(struct pl011_uart *uart, unsigned int flags);
void pl011_error_irq_handler(struct pl011_uart *, unsigned int); void pl011_error_irq_handler(struct pl011_uart *uart, unsigned int flags);
struct pl011_uart_ops {
int (*initialise)(struct pl011_uart *);
int (*tx_char)(char);
int (*rx_char)(char *);
void (*set_baudrate)(unsigned int, unsigned int);
void (*set_irq_mask)(unsigned int);
void (*clr_irq_mask)(unsigned int);
void (*irq_handler)(struct pl011_uart *);
void (*tx_irq_handler)(struct pl011_uart *, unsigned int);
void (*rx_irq_handler)(struct pl011_uart *, unsigned int);
void (*error_irq_handler)(struct pl011_uart *, unsigned int);
};
struct pl011_uart { struct pl011_uart {
unsigned int base; unsigned int base;
struct pl011_uart_ops ops;
unsigned int frame_errors; unsigned int frame_errors;
unsigned int parity_errors; unsigned int parity_errors;
unsigned int break_errors; unsigned int break_errors;
@@ -90,177 +72,166 @@ struct pl011_uart {
}; };
#define PL011_UARTEN (1 << 0) #define PL011_UARTEN (1 << 0)
static inline void pl011_uart_enable() static inline void pl011_uart_enable(unsigned int uart_base)
{ {
unsigned int val; unsigned int val;
val = 0; val = 0;
read(val, PL011_UARTCR); read(val, (uart_base + PL011_UARTCR));
val |= PL011_UARTEN; val |= PL011_UARTEN;
write(val, PL011_UARTCR); write(val, (uart_base + PL011_UARTCR));
return; return;
} }
static inline void pl011_uart_disable() static inline void pl011_uart_disable(unsigned int uart_base)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
read(val, PL011_UARTCR); read(val, (uart_base + PL011_UARTCR));
val &= ~PL011_UARTEN; val &= ~PL011_UARTEN;
write(val, PL011_UARTCR); write(val, (uart_base + PL011_UARTCR));
return; return;
} }
#define PL011_TXE (1 << 8) #define PL011_TXE (1 << 8)
static inline void pl011_tx_enable() static inline void pl011_tx_enable(unsigned int uart_base)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
read(val, PL011_UARTCR); read(val, (uart_base + PL011_UARTCR));
val |= PL011_TXE; val |= PL011_TXE;
write(val, PL011_UARTCR); write(val, (uart_base + PL011_UARTCR));
return; return;
} }
static inline void pl011_tx_disable() static inline void pl011_tx_disable(unsigned int uart_base)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
read(val, PL011_UARTCR); read(val, (uart_base + PL011_UARTCR));
val &= ~PL011_TXE; val &= ~PL011_TXE;
write(val, PL011_UARTCR); write(val, (uart_base + PL011_UARTCR));
return; return;
} }
#define PL011_RXE (1 << 9) #define PL011_RXE (1 << 9)
static inline void pl011_rx_enable() static inline void pl011_rx_enable(unsigned int uart_base)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
read(val, PL011_UARTCR); read(val, (uart_base + PL011_UARTCR));
val |= PL011_RXE; val |= PL011_RXE;
write(val, PL011_UARTCR); write(val, (uart_base + PL011_UARTCR));
return; return;
} }
static inline void pl011_rx_disable() static inline void pl011_rx_disable(unsigned int uart_base)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
read(val, PL011_UARTCR); read(val, (uart_base + PL011_UARTCR));
val &= ~PL011_RXE; val &= ~PL011_RXE;
write(val, PL011_UARTCR); write(val, (uart_base + PL011_UARTCR));
return; return;
} }
#define PL011_TWO_STOPBITS_SELECT (1 << 3) #define PL011_TWO_STOPBITS_SELECT (1 << 3)
static inline void pl011_set_stopbits(int stopbits) static inline void pl011_set_stopbits(unsigned int uart_base, int stopbits)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
read(val, PL011_UARTLCR_H); read(val, (uart_base + PL011_UARTLCR_H));
if(stopbits == 2) { /* Set to two bits */ if(stopbits == 2) {
/* Set to two bits */
val |= PL011_TWO_STOPBITS_SELECT; val |= PL011_TWO_STOPBITS_SELECT;
} else { /* Default is 1 */ } else {
/* Default is 1 */
val &= ~PL011_TWO_STOPBITS_SELECT; val &= ~PL011_TWO_STOPBITS_SELECT;
} }
write(val, PL011_UARTLCR_H); write(val, (uart_base + PL011_UARTLCR_H));
return; return;
} }
#define PL011_PARITY_ENABLE (1 << 1) #define PL011_PARITY_ENABLE (1 << 1)
static inline void pl011_parity_enable() static inline void pl011_parity_enable(unsigned int uart_base)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
read(val, PL011_UARTLCR_H); read(val, (uart_base + PL011_UARTLCR_H));
val |= PL011_PARITY_ENABLE; val |= PL011_PARITY_ENABLE;
write(val, PL011_UARTLCR_H); write(val, (uart_base + PL011_UARTLCR_H));
return; return;
} }
static inline void pl011_parity_disable() static inline void pl011_parity_disable(unsigned int uart_base)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
read(val, PL011_UARTLCR_H); read(val, (uart_base + PL011_UARTLCR_H));
val &= ~PL011_PARITY_ENABLE; val &= ~PL011_PARITY_ENABLE;
write(val, PL011_UARTLCR_H); write(val, (uart_base + PL011_UARTLCR_H));
return; return;
} }
#define PL011_PARITY_EVEN (1 << 2) #define PL011_PARITY_EVEN (1 << 2)
static inline void pl011_set_parity_even() static inline void pl011_set_parity_even(unsigned int uart_base)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
read(val, PL011_UARTLCR_H); read(val, (uart_base + PL011_UARTLCR_H));
val |= PL011_PARITY_EVEN; val |= PL011_PARITY_EVEN;
write(val, PL011_UARTLCR_H); write(val, (uart_base + PL011_UARTLCR_H));
return; return;
} }
static inline void pl011_set_parity_odd() static inline void pl011_set_parity_odd(unsigned int uart_base)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
read(val, PL011_UARTLCR_H); read(val, (uart_base + PL011_UARTLCR_H));
val &= ~PL011_PARITY_EVEN; val &= ~PL011_PARITY_EVEN;
write(val, PL011_UARTLCR_H); write(val, (uart_base + PL011_UARTLCR_H));
return; return;
} }
#define PL011_ENABLE_FIFOS (1 << 4) #define PL011_ENABLE_FIFOS (1 << 4)
static inline void pl011_enable_fifos() static inline void pl011_enable_fifos(unsigned int uart_base)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
read(val, PL011_UARTLCR_H); read(val, (uart_base + PL011_UARTLCR_H));
val |= PL011_ENABLE_FIFOS; val |= PL011_ENABLE_FIFOS;
write(val, PL011_UARTLCR_H); write(val, (uart_base + PL011_UARTLCR_H));
return; return;
} }
static inline void pl011_disable_fifos() static inline void pl011_disable_fifos(unsigned int uart_base)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
read(val, PL011_UARTLCR_H); read(val, (uart_base + PL011_UARTLCR_H));
val &= ~PL011_ENABLE_FIFOS; val &= ~PL011_ENABLE_FIFOS;
write(val, PL011_UARTLCR_H); write(val, (uart_base + PL011_UARTLCR_H));
return; return;
} }
#define PL011_WORD_WIDTH_SHIFT (5) #define PL011_WORD_WIDTH_SHIFT (5)
/* Sets the transfer word width for the data register. */ /* Sets the transfer word width for the data register. */
static inline void pl011_set_word_width(int size) static inline void pl011_set_word_width(unsigned int uart_base, int size)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
if(size < 5 || size > 8) /* Default is 8 */ if(size < 5 || size > 8) /* Default is 8 */
size = 8; size = 8;
/* Clear size field */ /* Clear size field */
read(val, PL011_UARTLCR_H); read(val, (uart_base + PL011_UARTLCR_H));
val &= ~(0x3 << PL011_WORD_WIDTH_SHIFT); val &= ~(0x3 << PL011_WORD_WIDTH_SHIFT);
write(val, PL011_UARTLCR_H); write(val, (uart_base + PL011_UARTLCR_H));
/* The formula is to write 5 less of size given: /* The formula is to write 5 less of size given:
* 11 = 8 bits * 11 = 8 bits
@@ -268,9 +239,9 @@ static inline void pl011_set_word_width(int size)
* 01 = 6 bits * 01 = 6 bits
* 00 = 5 bits * 00 = 5 bits
*/ */
read(val, PL011_UARTLCR_H); read(val, (uart_base + PL011_UARTLCR_H));
val |= (size - 5) << PL011_WORD_WIDTH_SHIFT; val |= (size - 5) << PL011_WORD_WIDTH_SHIFT;
write(val, PL011_UARTLCR_H); write(val, (uart_base + PL011_UARTLCR_H));
return; return;
} }
@@ -286,41 +257,40 @@ static inline void pl011_set_word_width(int size)
* 4 rxfifo >= 7/8 full txfifo <= 7/8 full * 4 rxfifo >= 7/8 full txfifo <= 7/8 full
* 5-7 reserved reserved * 5-7 reserved reserved
*/ */
static inline void pl011_set_irq_fifolevel(unsigned int xfer, unsigned int level) static inline void pl011_set_irq_fifolevel(unsigned int uart_base, \
unsigned int xfer, unsigned int level)
{ {
if(xfer != 1 && xfer != 0) /* Invalid fifo */ if(xfer != 1 && xfer != 0) /* Invalid fifo */
return; return;
if(level > 4) /* Invalid level */ if(level > 4) /* Invalid level */
return; return;
write(level << (xfer * 3), (uart_base + PL011_UARTIFLS));
write(level << (xfer * 3), PL011_UARTIFLS);
return; return;
} }
/* returns which irqs are masked */ /* returns which irqs are masked */
static inline unsigned int pl011_read_irqmask(void) static inline unsigned int pl011_read_irqmask(unsigned int uart_base)
{ {
unsigned int flags; unsigned int flags;
read(flags, PL011_UARTIMSC); read(flags, (uart_base + PL011_UARTIMSC));
return flags; return flags;
} }
/* returns masked irq status */ /* returns masked irq status */
static inline unsigned int pl011_read_irqstat(void) static inline unsigned int pl011_read_irqstat(unsigned int uart_base)
{ {
unsigned int irqstatus; unsigned int irqstatus;
read(irqstatus, PL011_UARTMIS); read(irqstatus, (uart_base + PL011_UARTMIS));
return irqstatus; return irqstatus;
} }
/* Clears the given asserted irqs */ /* Clears the given asserted irqs */
static inline void pl011_irq_clear(unsigned int flags) static inline void pl011_irq_clear(unsigned int uart_base, unsigned int flags)
{ {
if(flags > 0x3FF) { /* Invalid irq clearing bitvector */ if(flags > 0x3FF) { /* Invalid irq clearing bitvector */
return; return;
} }
/* Simply write the flags since it's a write-only register */ /* Simply write the flags since it's a write-only register */
write(flags, PL011_UARTICR); write(flags, (uart_base + PL011_UARTICR));
return; return;
} }
@@ -330,51 +300,45 @@ static inline void pl011_irq_clear(unsigned int flags)
/* Enables dma transfers for uart. The dma controller /* Enables dma transfers for uart. The dma controller
* must be initialised, set-up and enabled separately. * must be initialised, set-up and enabled separately.
*/ */
static inline void pl011_tx_dma_enable() static inline void pl011_tx_dma_enable(unsigned int uart_base)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
read(val, PL011_UARTDMACR); read(val, (uart_base + PL011_UARTDMACR));
val |= PL011_TXDMAEN; val |= PL011_TXDMAEN;
write(val, PL011_UARTDMACR); write(val, (uart_base + PL011_UARTDMACR));
return; return;
} }
/* Disables dma transfers for uart */ /* Disables dma transfers for uart */
static inline void pl011_tx_dma_disable() static inline void pl011_tx_dma_disable(unsigned int uart_base)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
read(val, PL011_UARTDMACR); read(val, (uart_base + PL011_UARTDMACR));
val &= ~PL011_TXDMAEN; val &= ~PL011_TXDMAEN;
write(val, PL011_UARTDMACR); write(val, (uart_base + PL011_UARTDMACR));
return; return;
} }
static inline void pl011_rx_dma_enable() static inline void pl011_rx_dma_enable(unsigned int uart_base)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
read(val, PL011_UARTDMACR); read(val, (uart_base + PL011_UARTDMACR));
val |= PL011_RXDMAEN; val |= PL011_RXDMAEN;
write(val, PL011_UARTDMACR); write(val, (uart_base + PL011_UARTDMACR));
return; return;
} }
static inline void pl011_rx_dma_disable() static inline void pl011_rx_dma_disable(unsigned int uart_base)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
read(val, PL011_UARTDMACR); read(val, (uart_base + PL011_UARTDMACR));
val &= ~PL011_RXDMAEN; val &= ~PL011_RXDMAEN;
write(val, PL011_UARTDMACR); write(val, (uart_base + PL011_UARTDMACR));
return; return;
} }
#endif /* __PL011_UART__ */ #endif /* __PL011_UART__ */

3
include/l4/platform/pb926/offsets.h
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@@ -32,6 +32,9 @@
#define PB926_VIC_BASE 0x10140000 /* Primary Vectored IC */ #define PB926_VIC_BASE 0x10140000 /* Primary Vectored IC */
#define PB926_SIC_BASE 0x10003000 /* Secondary IC */ #define PB926_SIC_BASE 0x10003000 /* Secondary IC */
#define PB926_UART0_BASE 0x101F1000 /* Console port (UART0) */ #define PB926_UART0_BASE 0x101F1000 /* Console port (UART0) */
#define PB926_UART1_BASE 0x101F2000 /* Console port (UART1) */
#define PB926_UART2_BASE 0x101F3000 /* Console port (UART2) */
#define PB926_UART3_BASE 0x10009000 /* Console port (UART3) */
/* /*
* Uart virtual address until a file-based console access * Uart virtual address until a file-based console access

2
include/l4/platform/pb926/platform.h
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@@ -10,7 +10,7 @@
#include INC_PLAT(offsets.h) #include INC_PLAT(offsets.h)
#include INC_GLUE(memlayout.h) #include INC_GLUE(memlayout.h)
#define PLATFORM_CONSOLE_BASE PB926_UART0_VBASE #define PLATFORM_CONSOLE0_BASE PB926_UART0_VBASE
/* SP804 timer has TIMER1 at TIMER0 + 0x20 address */ /* SP804 timer has TIMER1 at TIMER0 + 0x20 address */
#define PLATFORM_TIMER0_BASE PB926_TIMER01_VBASE #define PLATFORM_TIMER0_BASE PB926_TIMER01_VBASE

144
src/drivers/uart/pl011/pl011_uart.c
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@@ -6,22 +6,9 @@
#include <l4/drivers/uart/pl011/pl011_uart.h> #include <l4/drivers/uart/pl011/pl011_uart.h>
#include <l4/lib/bit.h> #include <l4/lib/bit.h>
#include INC_PLAT(platform.h)
struct pl011_uart uart = { struct pl011_uart uart;
.base = PL011_BASE,
.ops = {
.initialise = pl011_initialise_device,
.tx_char = pl011_tx_char,
.rx_char = pl011_rx_char,
.set_baudrate = pl011_set_baudrate,
.set_irq_mask = pl011_set_irq_mask,
.clr_irq_mask = pl011_clr_irq_mask,
},
.frame_errors = 0,
.parity_errors = 0,
.break_errors = 0,
.rx_timeout_errors = 0,
};
/* UART-specific internal error codes. /* UART-specific internal error codes.
* TODO: Replace them when generic error codes are in place */ * TODO: Replace them when generic error codes are in place */
@@ -44,56 +31,53 @@ struct pl011_uart uart = {
#define PL011_DSR (1 << 1) #define PL011_DSR (1 << 1)
#define PL011_CTS (1 << 0) #define PL011_CTS (1 << 0)
int pl011_tx_char(char c) int pl011_tx_char(unsigned int uart_base, char c)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
read(val, PL011_UARTFR); read(val, (uart_base + PL011_UARTFR));
if(val & PL011_TXFF) { /* TX FIFO Full */
if(val & PL011_TXFF) {
/* TX FIFO Full */
return -PL011_EAGAIN; return -PL011_EAGAIN;
} }
write(c, PL011_UARTDR);
write(c, (uart_base + PL011_UARTDR));
return 0; return 0;
} }
int pl011_rx_char(char * c) int pl011_rx_char(unsigned int uart_base, char * c)
{ {
unsigned int data; unsigned int data;
unsigned int val; unsigned int val = 0;
val = 0;
read(val, PL011_UARTFR); read(val, (uart_base + PL011_UARTFR));
if(val & PL011_RXFE) { /* RX FIFO Empty */ if(val & PL011_RXFE) {
/* RX FIFO Empty */
return -PL011_EAGAIN; return -PL011_EAGAIN;
} }
read(data, PL011_UARTDR); read(data, (uart_base + PL011_UARTDR));
*c = (char) data; *c = (char) data;
if((data >> 8) & 0xF) { /* There were errors */ if((data >> 8) & 0xF) {
return -1; /* Signal error in xfer */ /* There were errors, signal error */
return -1;
} }
return 0; /* No error return */ return 0;
} }
/* /*
* Sets the baud rate in kbps. It is recommended to use * Sets the baud rate in kbps. It is recommended to use
* standard rates such as: 1200, 2400, 3600, 4800, 7200, * standard rates such as: 1200, 2400, 3600, 4800, 7200,
* 9600, 14400, 19200, 28800, 38400, 57600 76800, 115200. * 9600, 14400, 19200, 28800, 38400, 57600 76800, 115200.
*/ */
void pl011_set_baudrate(unsigned int baud, unsigned int clkrate) void pl011_set_baudrate(unsigned int uart_base, unsigned int baud, \
unsigned int clkrate)
{ {
const unsigned int uartclk = 24000000; /* 24Mhz clock fixed on pb926 */ const unsigned int uartclk = 24000000; /* 24Mhz clock fixed on pb926 */
unsigned int val; unsigned int val = 0;
unsigned int ipart, fpart; unsigned int ipart = 0, fpart = 0;
unsigned int remainder;
remainder = 0;
ipart = 0;
fpart = 0;
val = 0;
/* Use default pb926 rate if no rate is supplied */ /* Use default pb926 rate if no rate is supplied */
if(clkrate == 0) if(clkrate == 0)
@@ -104,55 +88,56 @@ void pl011_set_baudrate(unsigned int baud, unsigned int clkrate)
/* 24000000 / (16 * 38400) */ /* 24000000 / (16 * 38400) */
ipart = 39; ipart = 39;
write(ipart, PL011_UARTIBRD); write(ipart, (uart_base + PL011_UARTIBRD));
write(fpart, PL011_UARTFBRD); write(fpart, (uart_base + PL011_UARTFBRD));
/* For the IBAUD and FBAUD to update, we need to /*
* For the IBAUD and FBAUD to update, we need to
* write to UARTLCR_H because the 3 registers are * write to UARTLCR_H because the 3 registers are
* actually part of a single register in hardware * actually part of a single register in hardware
* which only updates by a write to UARTLCR_H */ * which only updates by a write to UARTLCR_H
read(val, PL011_UARTLCR_H); */
write(val, PL011_UARTLCR_H); read(val, (uart_base + PL011_UARTLCR_H));
write(val, (uart_base + PL011_UARTLCR_H));
return; return;
} }
/* Masks the irqs given in the flags bitvector. */ /* Masks the irqs given in the flags bitvector. */
void pl011_set_irq_mask(unsigned int flags) void pl011_set_irq_mask(unsigned int uart_base, unsigned int flags)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
if(flags > 0x3FF) { /* Invalid irqmask bitvector */ if(flags > 0x3FF) {
/* Invalid irqmask bitvector */
return; return;
} }
read(val, PL011_UARTIMSC); read(val, (uart_base + PL011_UARTIMSC));
val |= flags; val |= flags;
write(val, PL011_UARTIMSC); write(val, (uart_base + PL011_UARTIMSC));
return; return;
} }
/* Clears the irqs given in flags from masking */ /* Clears the irqs given in flags from masking */
void pl011_clr_irq_mask(unsigned int flags) void pl011_clr_irq_mask(unsigned int uart_base, unsigned int flags)
{ {
unsigned int val; unsigned int val = 0;
val = 0;
if(flags > 0x3FF) { /* Invalid irqmask bitvector */ if(flags > 0x3FF) {
/* Invalid irqmask bitvector */
return; return;
} }
read(val, PL011_UARTIMSC); read(val, (uart_base + PL011_UARTIMSC));
val &= ~flags; val &= ~flags;
write(val, PL011_UARTIMSC); write(val, (uart_base + PL011_UARTIMSC));
return; return;
} }
/* Produces 1 character from data register and appends it into /*
* rx buffer keeps record of timeout errors if one occurs. */ * Produces 1 character from data register and appends it into
* rx buffer keeps record of timeout errors if one occurs.
*/
void pl011_rx_irq_handler(struct pl011_uart * uart, unsigned int flags) void pl011_rx_irq_handler(struct pl011_uart * uart, unsigned int flags)
{ {
/* /*
@@ -165,7 +150,6 @@ void pl011_rx_irq_handler(struct pl011_uart * uart, unsigned int flags)
/* Consumes 1 character from tx buffer and attempts to transmit it */ /* Consumes 1 character from tx buffer and attempts to transmit it */
void pl011_tx_irq_handler(struct pl011_uart * uart, unsigned int flags) void pl011_tx_irq_handler(struct pl011_uart * uart, unsigned int flags)
{ {
/* /*
* Currently we do nothing for uart irqs, because there's no external * Currently we do nothing for uart irqs, because there's no external
* client to send/receive data (e.g. userspace processes kernel threads). * client to send/receive data (e.g. userspace processes kernel threads).
@@ -214,7 +198,7 @@ void pl011_irq_handler(struct pl011_uart * uart)
int handler_index; int handler_index;
void (* handler)(struct pl011_uart *, unsigned int); void (* handler)(struct pl011_uart *, unsigned int);
val = pl011_read_irqstat(); val = pl011_read_irqstat(uart->base);
handler_index = 32 - __clz(val); handler_index = 32 - __clz(val);
if(!handler_index) { /* No irq */ if(!handler_index) { /* No irq */
@@ -224,15 +208,16 @@ void pl011_irq_handler(struct pl011_uart * uart)
handler = (void (*) (struct pl011_uart *, unsigned int)) handler = (void (*) (struct pl011_uart *, unsigned int))
pl011_handlers[handler_index]; pl011_handlers[handler_index];
if(handler) { /* If a handler is available */ /* If a handler is available, call it */
(*handler)(uart, val); /* Call it */ if(handler)
} (*handler)(uart, val);
return; return;
} }
void pl011_initialise_driver(void) void pl011_initialise_driver(void)
{ {
uart.ops.initialise(&uart); pl011_initialise_device(&uart);
} }
/* Initialises the uart class data structures, and the device. /* Initialises the uart class data structures, and the device.
@@ -246,32 +231,33 @@ int pl011_initialise_device(struct pl011_uart * uart)
uart->overrun_errors = 0; uart->overrun_errors = 0;
/* Initialise data register for 8 bit data read/writes */ /* Initialise data register for 8 bit data read/writes */
pl011_set_word_width(8); pl011_set_word_width(uart->base, 8);
/* Fifos are disabled because by default it is assumed the port /*
* Fifos are disabled because by default it is assumed the port
* will be used as a user terminal, and in that case the typed * will be used as a user terminal, and in that case the typed
* characters will only show up when fifos are flushed, rather than * characters will only show up when fifos are flushed, rather than
* when each character is typed. We avoid this by not using fifos. * when each character is typed. We avoid this by not using fifos.
*/ */
pl011_disable_fifos(); pl011_disable_fifos(uart->base);
/* Set default baud rate of 38400 */ /* Set default baud rate of 38400 */
pl011_set_baudrate(38400, 24000000); pl011_set_baudrate(uart->base, 38400, 24000000);
/* Set default settings of 1 stop bit, no parity, no hw flow ctrl */ /* Set default settings of 1 stop bit, no parity, no hw flow ctrl */
pl011_set_stopbits(1); pl011_set_stopbits(uart->base, 1);
pl011_parity_disable(); pl011_parity_disable(uart->base);
/* Install the irq handler */ /* Install the irq handler */
/* TODO: INSTALL IT HERE */ /* TODO: INSTALL IT HERE */
/* Enable all irqs */ /* Enable all irqs */
pl011_clr_irq_mask(0x3FF); pl011_clr_irq_mask(uart->base, 0x3FF);
/* Enable rx, tx, and uart chip */ /* Enable rx, tx, and uart chip */
pl011_tx_enable(); pl011_tx_enable(uart->base);
pl011_rx_enable(); pl011_rx_enable(uart->base);
pl011_uart_enable(); pl011_uart_enable(uart->base);
return 0; return 0;
} }

13
src/platform/pb926/platform.c
View File

@@ -19,9 +19,10 @@
#include INC_PLAT(irq.h) #include INC_PLAT(irq.h)
#include INC_ARCH(asm.h) #include INC_ARCH(asm.h)
/* We will use UART0 for kernel as well as user tasks, so map it to kernel and user space */
void init_platform_console(void) void init_platform_console(void)
{ {
add_boot_mapping(PB926_UART0_BASE, PL011_BASE, PAGE_SIZE, add_boot_mapping(PB926_UART0_BASE, PLATFORM_CONSOLE0_BASE, PAGE_SIZE,
MAP_IO_DEFAULT_FLAGS); MAP_IO_DEFAULT_FLAGS);
/* /*
@@ -35,13 +36,13 @@ void init_platform_console(void)
uart_init(); uart_init();
} }
/*
* We are using TIMER0 only, so we map TIMER0 base,
* incase any other timer is needed we need to map it
* to userspace or kernel space as needed
*/
void init_platform_timer(void) void init_platform_timer(void)
{ {
/*
* We are using TIMER0 only, so we map TIMER0 base,
* incase any other timer is needed we need to map it
* to userspace or kernel space as needed
*/
add_boot_mapping(PB926_TIMER01_BASE, PLATFORM_TIMER0_BASE, PAGE_SIZE, add_boot_mapping(PB926_TIMER01_BASE, PLATFORM_TIMER0_BASE, PAGE_SIZE,
MAP_IO_DEFAULT_FLAGS); MAP_IO_DEFAULT_FLAGS);

7
src/platform/pb926/uart.c
View File

@@ -12,8 +12,9 @@ extern struct pl011_uart uart;
void uart_init() void uart_init()
{ {
uart.base = PL011_BASE; /* We are using UART0 for kernel */
uart.ops.initialise(&uart); uart.base = PLATFORM_CONSOLE0_BASE;
pl011_initialise_device(&uart);
} }
/* Generic uart function that lib/putchar.c expects to see implemented */ /* Generic uart function that lib/putchar.c expects to see implemented */
@@ -22,7 +23,7 @@ void uart_putc(char c)
int res; int res;
/* Platform specific uart implementation */ /* Platform specific uart implementation */
do { do {
res = uart.ops.tx_char(c); res =pl011_tx_char(uart.base, c);
} while (res < 0); } while (res < 0);
} }