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60 lines
1.1 KiB
C
60 lines
1.1 KiB
C
#ifndef __ARM_V5_UTCB_H__
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#define __ARM_V5_UTCB_H__
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/*
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* NOTE: Any changes you make here, you *MUST* change
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* utcb_address() macro in syscall.S assembler.
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*/
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/* Read Thread ID User RW register */
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static inline u32 l4_cp15_read_tid_usr_rw(void)
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{
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volatile u32 val;
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__asm__ __volatile__ (
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"mrc p15, 0, %0, c13, c0, 2"
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: "=r" (val)
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:
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);
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return val;
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}
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/* Write Thread ID User RW register */
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static inline void l4_cp15_write_tid_usr_rw(volatile u32 val)
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{
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__asm__ __volatile__ (
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"mcr p15, 0, %0, c13, c0, 2"
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:
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: "r" (val)
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);
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}
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/* Read Thread ID User RO register */
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static inline u32 l4_cp15_read_tid_usr_ro(void)
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{
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volatile u32 val;
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__asm__ __volatile__ (
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"mrc p15, 0, %0, c13, c0, 3"
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: "=r" (val)
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:
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);
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return val;
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}
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/*
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* In ARMv7, utcb resides in the userspace read-only
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* thread register. This adds the benefit of avoiding
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* dirtying the cache and extra management for smp since
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* it is per-cpu.
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*/
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static inline struct utcb *l4_get_utcb()
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{
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// printf("%s: UTCB Adddress: 0x%x\n", __FUNCTION__, l4_cp15_read_tid_usr_ro());
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return (struct utcb *)l4_cp15_read_tid_usr_ro();
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}
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#endif /* __ARM_V5_UTCB_H__ */
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