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129 lines
3.7 KiB
C
129 lines
3.7 KiB
C
/*
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* ARM v5-specific virtual memory details
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*
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* Copyright (C) 2007 Bahadir Balban
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*/
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#ifndef __V5_MM_H__
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#define __V5_MM_H__
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/* ARM specific definitions */
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#define VIRT_MEM_START 0
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#define VIRT_MEM_END 0xFFFFFFFF
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#define SECTION_SIZE SZ_1MB
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#define SECTION_MASK (SECTION_SIZE - 1)
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#define SECTION_ALIGN_MASK (~SECTION_MASK)
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#define SECTION_BITS 20
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#define ARM_PAGE_SIZE SZ_4K
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#define ARM_PAGE_MASK 0xFFF
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#define ARM_PAGE_BITS 12
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#define PGD_SIZE SZ_4K * 4
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#define PGD_ENTRY_TOTAL SZ_4K
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#define PMD_SIZE SZ_1K
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#define PMD_ENTRY_TOTAL 256
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#define PMD_MAP_SIZE SZ_1MB
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#define PMD_ALIGN_MASK (~(PMD_SIZE - 1))
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#define PMD_TYPE_MASK 0x3
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#define PMD_TYPE_FAULT 0
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#define PMD_TYPE_PMD 1
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#define PMD_TYPE_SECTION 2
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#define PTE_TYPE_MASK 0x3
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#define PTE_TYPE_FAULT 0
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#define PTE_TYPE_LARGE 1
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#define PTE_TYPE_SMALL 2
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#define PTE_TYPE_TINY 3
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/* Permission field offsets */
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#define SECTION_AP0 10
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/*
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* These are indices into arrays with pgd_t or pmd_t sized elements,
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* therefore the index must be divided by appropriate element size
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*/
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#define PGD_INDEX(x) (((((unsigned long)(x)) >> 18) \
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& 0x3FFC) / sizeof(pmd_t))
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/*
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* Strip out the page offset in this
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* megabyte from a total of 256 pages.
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*/
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#define PMD_INDEX(x) (((((unsigned long)(x)) >> 10) \
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& 0x3FC) / sizeof (pte_t))
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/* We need this as print-early.S is including this file */
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#ifndef __ASSEMBLY__
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/* Type-checkable page table elements */
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typedef u32 pmd_t;
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typedef u32 pte_t;
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/* Page global directory made up of pgd_t entries */
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typedef struct pgd_table {
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pmd_t entry[PGD_ENTRY_TOTAL];
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} pgd_table_t;
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/* Page middle directory made up of pmd_t entries */
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typedef struct pmd_table {
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pte_t entry[PMD_ENTRY_TOTAL];
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} pmd_table_t;
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/* Applies for both small and large pages */
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#define PAGE_AP0 4
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#define PAGE_AP1 6
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#define PAGE_AP2 8
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#define PAGE_AP3 10
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/* Permission values with rom and sys bits ignored */
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#define SVC_RW_USR_NONE 1
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#define SVC_RW_USR_RO 2
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#define SVC_RW_USR_RW 3
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#define PTE_PROT_MASK (0xFF << 4)
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#define CACHEABILITY 3
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#define BUFFERABILITY 2
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#define cacheable (1 << CACHEABILITY)
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#define bufferable (1 << BUFFERABILITY)
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#define uncacheable 0
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#define unbufferable 0
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/* Helper macros for common cases */
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#define __MAP_USR_RW (cacheable | bufferable | (SVC_RW_USR_RW << PAGE_AP0) \
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| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2) \
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| (SVC_RW_USR_RW << PAGE_AP3))
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#define __MAP_USR_RO (cacheable | bufferable | (SVC_RW_USR_RO << PAGE_AP0) \
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| (SVC_RW_USR_RO << PAGE_AP1) | (SVC_RW_USR_RO << PAGE_AP2) \
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| (SVC_RW_USR_RO << PAGE_AP3))
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#define __MAP_KERN_RW (cacheable | bufferable | (SVC_RW_USR_NONE << PAGE_AP0) \
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| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2) \
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| (SVC_RW_USR_NONE << PAGE_AP3))
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#define __MAP_KERN_IO (uncacheable | unbufferable | (SVC_RW_USR_NONE << PAGE_AP0) \
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| (SVC_RW_USR_NONE << PAGE_AP1) | (SVC_RW_USR_NONE << PAGE_AP2) \
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| (SVC_RW_USR_NONE << PAGE_AP3))
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#define __MAP_USR_IO (uncacheable | unbufferable | (SVC_RW_USR_RW << PAGE_AP0) \
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| (SVC_RW_USR_RW << PAGE_AP1) | (SVC_RW_USR_RW << PAGE_AP2) \
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| (SVC_RW_USR_RW << PAGE_AP3))
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/* There is no execute bit in ARMv5, so we ignore it */
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#define __MAP_USR_RWX __MAP_USR_RW
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#define __MAP_USR_RX __MAP_USR_RO
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#define __MAP_KERN_RWX __MAP_KERN_RW
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#define __MAP_KERN_RX __MAP_KERN_RW /* We always have kernel RW */
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#define __MAP_FAULT 0
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void add_section_mapping_init(unsigned int paddr, unsigned int vaddr,
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unsigned int size, unsigned int flags);
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void remove_section_mapping(unsigned long vaddr);
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extern pgd_table_t init_pgd;
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void arch_update_utcb(unsigned long utcb_address);
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void system_identify(void);
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#endif /* __ASSEMBLY__ */
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#endif /* __V5_MM_H__ */
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