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32c0bb3a76
Irqs can now touch runqueues and do async wakeups. This necessitated that we implement all wake up wait and runqueue locking work with irqs. All this, assumes that in an SMP setup we may have cross-cpu wake ups, runqueue manipulation. If we later decide that we only wake up threads in the current container, (and lock containers to cpus) we won't really need spinlocks, or irq disabling anymore. The current set up might be trivially less responsive, but is more flexible.
51 lines
1.4 KiB
C
51 lines
1.4 KiB
C
#ifndef __PLATFORM_IRQ_H__
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#define __PLATFORM_IRQ_H__
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#define IRQ_CHIPS_MAX 2
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/*
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* Globally unique irq chip offsets:
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*
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* A global irq number is calculated as
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* chip_offset + local_irq_offset.
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*
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* This way, the global irq number uniquely represents
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* an irq on any irq chip.
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*/
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#define VIC_CHIP_OFFSET 0
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#define SIC_CHIP_OFFSET 32
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/* Maximum irqs on VIC and SIC */
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#define VIC_IRQS_MAX 32
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#define SIC_IRQS_MAX 32
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#define IRQS_MAX VIC_IRQS_MAX + SIC_IRQS_MAX
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/* Vectored Interrupt Controller local IRQ numbers */
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#define VIC_IRQ_TIMER01 4
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#define VIC_IRQ_TIMER23 5
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#define VIC_IRQ_RTC 10
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#define VIC_IRQ_UART0 12
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#define VIC_IRQ_UART1 13
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#define VIC_IRQ_UART2 14
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#define VIC_IRQ_SIC 31
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/* Secondary Interrupt controller local IRQ numbers */
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#define SIC_IRQ_SWI 0
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#define SIC_IRQ_UART3 6
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/* Global irq numbers, note these should reflect global device names */
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#define IRQ_TIMER0 (VIC_IRQ_TIMER01 + VIC_CHIP_OFFSET)
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#define IRQ_TIMER1 (VIC_IRQ_TIMER23 + VIC_CHIP_OFFSET)
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#define IRQ_RTC (VIC_IRQ_RTC + VIC_CHIP_OFFSET)
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#define IRQ_UART0 (VIC_IRQ_UART0 + VIC_CHIP_OFFSET)
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#define IRQ_UART1 (VIC_IRQ_UART1 + VIC_CHIP_OFFSET)
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#define IRQ_UART2 (VIC_IRQ_UART2 + VIC_CHIP_OFFSET)
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#define IRQ_SIC (VIC_IRQ_SIC + VIC_CHIP_OFFSET)
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#define IRQ_SICSWI (SIC_IRQ_SWI + SIC_CHIP_OFFSET)
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#define IRQ_UART3 (SIC_IRQ_UART3 + SIC_CHIP_OFFSET)
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#endif /* __PLATFORM_IRQ_H__ */
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