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https://github.com/drasko/codezero.git
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265 lines
6.3 KiB
C
265 lines
6.3 KiB
C
/*
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* PL011 Primecell UART driver
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*
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* Copyright (C) 2007 Bahadir Balban
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*/
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#include <l4/drivers/uart/pl011/pl011_uart.h>
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#include <l4/lib/bit.h>
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#include INC_PLAT(platform.h)
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struct pl011_uart uart;
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/* UART-specific internal error codes.
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* TODO: Replace them when generic error codes are in place */
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#define PL011_ERROR 1
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#define PL011_EAGAIN 2
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/* Error status bits in receive status register */
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#define PL011_FE (1 << 0)
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#define PL011_PE (1 << 1)
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#define PL011_BE (1 << 2)
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#define PL011_OE (1 << 3)
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/* Status bits in flag register */
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#define PL011_TXFE (1 << 7)
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#define PL011_RXFF (1 << 6)
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#define PL011_TXFF (1 << 5)
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#define PL011_RXFE (1 << 4)
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#define PL011_BUSY (1 << 3)
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#define PL011_DCD (1 << 2)
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#define PL011_DSR (1 << 1)
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#define PL011_CTS (1 << 0)
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int pl011_tx_char(unsigned int uart_base, char c)
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{
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unsigned int val = 0;
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read(val, (uart_base + PL011_UARTFR));
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if(val & PL011_TXFF) {
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/* TX FIFO Full */
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return -PL011_EAGAIN;
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}
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write(c, (uart_base + PL011_UARTDR));
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return 0;
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}
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int pl011_rx_char(unsigned int uart_base, char * c)
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{
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unsigned int data;
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unsigned int val = 0;
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read(val, (uart_base + PL011_UARTFR));
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if(val & PL011_RXFE) {
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/* RX FIFO Empty */
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return -PL011_EAGAIN;
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}
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read(data, (uart_base + PL011_UARTDR));
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*c = (char) data;
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if((data >> 8) & 0xF) {
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/* There were errors, signal error */
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return -1;
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}
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return 0;
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}
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/*
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* Sets the baud rate in kbps. It is recommended to use
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* standard rates such as: 1200, 2400, 3600, 4800, 7200,
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* 9600, 14400, 19200, 28800, 38400, 57600 76800, 115200.
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*/
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void pl011_set_baudrate(unsigned int uart_base, unsigned int baud, \
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unsigned int clkrate)
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{
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const unsigned int uartclk = 24000000; /* 24Mhz clock fixed on pb926 */
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unsigned int val = 0;
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unsigned int ipart = 0, fpart = 0;
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/* Use default pb926 rate if no rate is supplied */
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if(clkrate == 0)
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clkrate = uartclk;
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if(baud > 115200 || baud < 1200)
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baud = 38400; /* Default rate. */
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/* 24000000 / (16 * 38400) */
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ipart = 39;
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write(ipart, (uart_base + PL011_UARTIBRD));
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write(fpart, (uart_base + PL011_UARTFBRD));
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/*
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* For the IBAUD and FBAUD to update, we need to
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* write to UARTLCR_H because the 3 registers are
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* actually part of a single register in hardware
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* which only updates by a write to UARTLCR_H
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*/
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read(val, (uart_base + PL011_UARTLCR_H));
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write(val, (uart_base + PL011_UARTLCR_H));
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return;
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}
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/* Masks the irqs given in the flags bitvector. */
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void pl011_set_irq_mask(unsigned int uart_base, unsigned int flags)
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{
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unsigned int val = 0;
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if(flags > 0x3FF) {
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/* Invalid irqmask bitvector */
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return;
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}
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read(val, (uart_base + PL011_UARTIMSC));
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val |= flags;
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write(val, (uart_base + PL011_UARTIMSC));
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return;
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}
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/* Clears the irqs given in flags from masking */
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void pl011_clr_irq_mask(unsigned int uart_base, unsigned int flags)
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{
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unsigned int val = 0;
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if(flags > 0x3FF) {
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/* Invalid irqmask bitvector */
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return;
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}
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read(val, (uart_base + PL011_UARTIMSC));
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val &= ~flags;
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write(val, (uart_base + PL011_UARTIMSC));
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return;
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}
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/*
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* Produces 1 character from data register and appends it into
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* rx buffer keeps record of timeout errors if one occurs.
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*/
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void pl011_rx_irq_handler(struct pl011_uart * uart, unsigned int flags)
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{
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/*
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* Currently we do nothing for uart irqs, because there's no external
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* client to send/receive data (e.g. userspace processes kernel threads).
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*/
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return;
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}
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/* Consumes 1 character from tx buffer and attempts to transmit it */
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void pl011_tx_irq_handler(struct pl011_uart * uart, unsigned int flags)
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{
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/*
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* Currently we do nothing for uart irqs, because there's no external
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* client to send/receive data (e.g. userspace processes kernel threads).
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*/
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return;
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}
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/* Updates error counts and exits. Does nothing to recover errors */
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void pl011_error_irq_handler(struct pl011_uart * uart, unsigned int flags)
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{
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if(flags & PL011_FEIRQ) {
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uart->frame_errors++;
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}
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if(flags & PL011_PEIRQ) {
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uart->parity_errors++;
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}
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if(flags & PL011_BEIRQ) {
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uart->break_errors++;
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}
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if(flags & PL011_OEIRQ) {
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uart->overrun_errors++;
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}
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return;
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}
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void (* pl011_handlers[]) (struct pl011_uart *, unsigned int) = {
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0, /* Modem RI */
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0, /* Modem CTS */
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0, /* Modem DCD */
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0, /* Modem DSR */
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&pl011_rx_irq_handler, /* Rx */
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&pl011_tx_irq_handler, /* Tx */
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&pl011_rx_irq_handler, /* Rx timeout */
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&pl011_error_irq_handler, /* Framing error */
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&pl011_error_irq_handler, /* Parity error */
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&pl011_error_irq_handler, /* Break error */
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&pl011_error_irq_handler /* Overrun error */
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};
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/* UART main entry for irq handling. It redirects actual
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* handling to handlers relevant to the irq that has occured.
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*/
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void pl011_irq_handler(struct pl011_uart * uart)
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{
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unsigned int val;
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int handler_index;
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void (* handler)(struct pl011_uart *, unsigned int);
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val = pl011_read_irqstat(uart->base);
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handler_index = 32 - __clz(val);
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if(!handler_index) { /* No irq */
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return;
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}
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/* Jump to right handler */
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handler = (void (*) (struct pl011_uart *, unsigned int))
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pl011_handlers[handler_index];
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/* If a handler is available, call it */
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if(handler)
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(*handler)(uart, val);
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return;
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}
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void pl011_initialise_driver(void)
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{
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pl011_initialise_device(&uart);
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}
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/* Initialises the uart class data structures, and the device.
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* Terminal-like operation is assumed for default settings.
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*/
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int pl011_initialise_device(struct pl011_uart * uart)
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{
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uart->frame_errors = 0;
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uart->parity_errors = 0;
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uart->break_errors = 0;
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uart->overrun_errors = 0;
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/* Initialise data register for 8 bit data read/writes */
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pl011_set_word_width(uart->base, 8);
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/*
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* Fifos are disabled because by default it is assumed the port
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* will be used as a user terminal, and in that case the typed
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* characters will only show up when fifos are flushed, rather than
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* when each character is typed. We avoid this by not using fifos.
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*/
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pl011_disable_fifos(uart->base);
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/* Set default baud rate of 38400 */
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pl011_set_baudrate(uart->base, 38400, 24000000);
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/* Set default settings of 1 stop bit, no parity, no hw flow ctrl */
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pl011_set_stopbits(uart->base, 1);
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pl011_parity_disable(uart->base);
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/* Install the irq handler */
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/* TODO: INSTALL IT HERE */
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/* Enable all irqs */
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pl011_clr_irq_mask(uart->base, 0x3FF);
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/* Enable rx, tx, and uart chip */
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pl011_tx_enable(uart->base);
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pl011_rx_enable(uart->base);
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pl011_uart_enable(uart->base);
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return 0;
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}
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