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bda0e064af
New files are an exact copy of pb926 files, but will help in testing different configurations and compilations.
61 lines
2.2 KiB
C
61 lines
2.2 KiB
C
/*
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* Describes physical memory layout of pb926 platform.
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*
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* Copyright (C) 2007 Bahadir Balban
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*/
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#ifndef __PLATFORM_PB926_OFFSETS_H__
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#define __PLATFORM_PB926_OFFSETS_H__
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/* Physical memory base */
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#define PHYS_MEM_START 0x00000000 /* inclusive */
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#define PHYS_MEM_END 0x08000000 /* 128 MB, exclusive */
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/*
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* These bases taken from where kernel is `physically' linked at,
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* also used to calculate virtual-to-physical translation offset.
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* See the linker script for their sources. PHYS_ADDR_BASE can't
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* use a linker variable because it's referred from assembler.
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*/
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#define PHYS_ADDR_BASE 0x100000
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/* Device memory base */
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#define PB926_DEV_PHYS 0x10000000
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/* Device offsets in physical memory */
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#define PB926_SYSTEM_REGISTERS 0x10000000 /* System registers */
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#define PB926_SYSCTRL_BASE 0x101E0000 /* System controller */
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#define PB926_WATCHDOG_BASE 0x101E1000 /* Watchdog */
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#define PB926_TIMER01_BASE 0x101E2000 /* Timers 0 and 1 */
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#define PB926_TIMER23_BASE 0x101E3000 /* Timers 2 and 3 */
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#define PB926_RTC_BASE 0x101E8000 /* Real Time Clock */
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#define PB926_VIC_BASE 0x10140000 /* Primary Vectored IC */
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#define PB926_SIC_BASE 0x10003000 /* Secondary IC */
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#define PB926_UART0_BASE 0x101F1000 /* Console port (UART0) */
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/*
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* Uart virtual address until a file-based console access
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* is available for userspace
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*/
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#define USERSPACE_UART_BASE 0x500000
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/*
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* Device offsets in virtual memory. They offset to some virtual
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* device base address. Each page on this virtual base is consecutively
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* allocated to devices. Nice and smooth.
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*/
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#define PB926_TIMER01_VOFFSET 0x00000000
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#define PB926_UART0_VOFFSET 0x00001000
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#define PB926_VIC_VOFFSET 0x00002000
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#define PB926_SIC_VOFFSET 0x00003000
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#define PB926_SYSREGS_VOFFSET 0x00005000
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#define PB926_SYSCTRL_VOFFSET 0x00006000
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#define PB926_UART0_VBASE (IO_AREA0_VADDR + PB926_UART0_VOFFSET)
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#define PB926_TIMER01_VBASE (IO_AREA0_VADDR + PB926_TIMER01_VOFFSET)
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#define PB926_SYSCTRL_VBASE (IO_AREA0_VADDR + PB926_SYSCTRL_VOFFSET)
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#define PB926_VIC_VBASE (IO_AREA0_VADDR + PB926_VIC_VOFFSET)
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#define PB926_SIC_VBASE (IO_AREA0_VADDR + PB926_SIC_VOFFSET)
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#endif /* __PLATFORM_PB926_OFFSETS_H__ */
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