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32 lines
830 B
C
32 lines
830 B
C
#ifndef __PLATFORM_IRQ_H__
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#define __PLATFORM_IRQ_H__
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/* TODO: Not sure about this, need to check */
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#define IRQ_CHIPS_MAX 4
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#define IRQS_MAX 96
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/*
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* IRQ indices,
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* GIC 0 and 1 are for logic tile 1
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* GIC 2 and 3 are for logic tile 2
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*/
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#define IRQ_TIMER01 4
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#define IRQ_TIMER23 5
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#define IRQ_RTC 10
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#define IRQ_UART0 12
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#define IRQ_UART1 13
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#define IRQ_UART2 14
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#define IRQ_UART3 15
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/*
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* TODO: Seems like GIC0 and GIC1 are cascaded for logic tile1
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* and GIC2 and GIC3 are cascaded for logic tile 2.
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* Interrupt Distribution:
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* 0-31: Used as SI provided by distributed interrupt controller
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* 32-63: Externel Peripheral Interrupts
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* 64-71: Interrupts from tile site 1
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* 72-79: Interrupts from tile site 2
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* 80-95: PCI and reserved Interrupts
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*/
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#endif /* __PLATFORM_IRQ_H__ */
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