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66 lines
1.9 KiB
C
66 lines
1.9 KiB
C
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#ifndef __ARCH_ARM_ASM_H__
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#define __ARCH_ARM_ASM_H__
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/* Top nibble of the byte denotes irqs/fiqs disabled, ARM state */
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#define ARM_MODE_MASK 0x1F
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#define ARM_MODE_SVC 0x13
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#define ARM_MODE_UND 0x1B
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#define ARM_MODE_ABT 0x17
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#define ARM_MODE_IRQ 0x12
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#define ARM_MODE_FIQ 0x11
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#define ARM_MODE_USR 0x10
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#define ARM_MODE_SYS 0x1F
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#define ARM_NOIRQ_SVC 0xD3
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#define ARM_NOIRQ_UND 0xDB
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#define ARM_NOIRQ_ABT 0xD7
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#define ARM_NOIRQ_IRQ 0xD2
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#define ARM_NOIRQ_FIQ 0xD1
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#define ARM_NOIRQ_USR 0xD0
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#define ARM_NOIRQ_SYS 0xDF
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/* For enabling *clear* these bits */
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#define ARM_IRQ_BIT 0x80
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#define ARM_FIQ_BIT 0x40
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/* Notes about ARM instructions:
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*
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* TST instruction:
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*
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* Essentially TST "AND"s two values and the result affects the Z (Zero bit)
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* in CPSR, which can be used for conditions. For example in:
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*
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* TST r0, #VALUE
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*
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* If anding r0 and #VALUE results in a positive value (i.e. they have a
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* common bit set as 1) then Z bit is 0, which accounts for an NE (Not equal)
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* condition. Consequently, e.g. a BEQ instruction would be skipped and a BNE
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* would be executed.
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*
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* In the opposite case, r0 and #VALUE has no common bits, and anding them
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* results in 0. This means Z bit is 1, and any EQ instruction coming afterwards
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* would be executed.
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*
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* I have made this explanation here because I think the behaviour of the Z bit
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* is not very clear in TST. Normally Z bit is used for equivalence (e.g. CMP
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* instruction) but in TST case even if two values were equal the Z bit could
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* point to an NE or EQ condition depending on whether the values have non-zero
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* bits.
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*/
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#define dbg_stop_here() __asm__ __volatile__ ( "bkpt #0\n" :: )
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#define BEGIN_PROC(name) \
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.global name; \
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.type name,function; \
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.align; \
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name:
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#define END_PROC(name) \
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.fend_##name: \
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.size name,.fend_##name - name;
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#endif /* __ARCH_ARM_ASM_H__ */
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