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79 lines
2.8 KiB
C
79 lines
2.8 KiB
C
/*
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* Copyright (C) 2009 B Labs Ltd.
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*/
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#ifndef __PLATFORM_IRQ_H__
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#define __PLATFORM_IRQ_H__
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/* Actually there are 4 GIC's on the EB, only 2 are used for tile site 1 */
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#define IRQ_CHIPS_MAX 2
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#if defined(CONFIG_CPU_ARM11MPCORE) || defined (CONFIG_CPU_CORTEXA9)
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#define IRQS_MAX 64
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#else
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#define IRQS_MAX 96
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#endif
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/*
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* Interrupt Distribution:
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* 0-31: Used as SI provided by distributed interrupt controller
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* 32-63: Externel Peripheral Interrupts
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* 64-71: Interrupts from tile site 1
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* 72-79: Interrupts from tile site 2
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* 80-95: PCI and reserved Interrupts
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*/
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#define EB_GIC_IRQ_OFFSET 32
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#define EB_IRQ_WATCHDOG (EB_GIC_IRQ_OFFSET + 0)
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#define EB_IRQ_SOFTINT (EB_GIC_IRQ_OFFSET + 1)
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#define EB_IRQ_COMRX (EB_GIC_IRQ_OFFSET + 2)
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#define EB_IRQ_COMTX (EB_GIC_IRQ_OFFSET + 3)
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#define EB_IRQ_TIMER01 (EB_GIC_IRQ_OFFSET + 4)
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#define EB_IRQ_TIMER23 (EB_GIC_IRQ_OFFSET + 5)
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#define EB_IRQ_GPIO0 (EB_GIC_IRQ_OFFSET + 6)
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#define EB_IRQ_GPIO1 (EB_GIC_IRQ_OFFSET + 7)
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#define EB_IRQ_GPIO2 (EB_GIC_IRQ_OFFSET + 8)
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#define EB_IRQ_RTC (EB_GIC_IRQ_OFFSET + 10)
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#define EB_IRQ_UART0 (EB_GIC_IRQ_OFFSET + 12)
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#define EB_IRQ_UART1 (EB_GIC_IRQ_OFFSET + 13)
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#define EB_IRQ_UART2 (EB_GIC_IRQ_OFFSET + 14)
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#define EB_IRQ_UART3 (EB_GIC_IRQ_OFFSET + 15)
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#define EB_IRQ_SCI (EB_GIC_IRQ_OFFSET + 16) /* Smart Card Interface */
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#define EB_IRQ_MCI0 (EB_GIC_IRQ_OFFSET + 17)
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#define EB_IRQ_MCI1 (EB_GIC_IRQ_OFFSET + 18)
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#define EB_IRQ_AACI (EB_GIC_IRQ_OFFSET + 19) /* Advanced Audio codec */
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#define EB_IRQ_KMI0 (EB_GIC_IRQ_OFFSET + 20) /* Keyboard */
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#define EB_IRQ_KMI1 (EB_GIC_IRQ_OFFSET + 21) /* Mouse */
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#define EB_IRQ_LCD (EB_GIC_IRQ_OFFSET + 20) /* Character LCD */
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#define EB_IRQ_DMAC (EB_GIC_IRQ_OFFSET + 20) /* DMA Controller */
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/* Interrupt Sources to ARM 11 MPCore or EB+A9 MPCore GIC */
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#define MPCORE_GIC_IRQ_AACI (EB_GIC_IRQ_OFFSET + 0)
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#define MPCORE_GIC_IRQ_TIMER01 (EB_GIC_IRQ_OFFSET + 1)
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#define MPCORE_GIC_IRQ_TIMER23 (EB_GIC_IRQ_OFFSET + 2)
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#define MPCORE_GIC_IRQ_USB (EB_GIC_IRQ_OFFSET + 3)
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#define MPCORE_GIC_IRQ_UART0 (EB_GIC_IRQ_OFFSET + 4)
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#define MPCORE_GIC_IRQ_UART1 (EB_GIC_IRQ_OFFSET + 5)
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#define MPCORE_GIC_IRQ_RTC (EB_GIC_IRQ_OFFSET + 6)
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#define MPCORE_GIC_IRQ_KMI0 (EB_GIC_IRQ_OFFSET + 7)
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#define MPCORE_GIC_IRQ_KMI1 (EB_GIC_IRQ_OFFSET + 8)
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#define MPCORE_GIC_IRQ_ETH (EB_GIC_IRQ_OFFSET + 9)
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/* Interrupt from GIC1 on Base board */
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#define MPCORE_GIC_IRQ_EB_GIC1 (EB_GIC_IRQ_OFFSET + 10)
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#define MPCORE_GIC_IRQ_EB_GIC2 (EB_GIC_IRQ_OFFSET + 11)
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#define MPCORE_GIC_IRQ_EB_GIC3 (EB_GIC_IRQ_OFFSET + 12)
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#define MPCORE_GIC_IRQ_EB_GIC4 (EB_GIC_IRQ_OFFSET + 13)
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#if defined (CONFIG_CPU_ARM11MPCORE) || defined (CONFIG_CPU_CORTEXA9)
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#define IRQ_TIMER0 MPCORE_GIC_IRQ_TIMER01
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#define IRQ_TIMER1 MPCORE_GIC_IRQ_TIMER23
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#else
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#define IRQ_TIMER0 EB_IRQ_TIMER01
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#define IRQ_TIMER1 EB_IRQ_TIMER23
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#endif
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#endif /* __PLATFORM_IRQ_H__ */
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