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78 lines
3.4 KiB
C
78 lines
3.4 KiB
C
/*
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* Describes physical memory layout of PB11MPCORE platform.
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*
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* Copyright (C) 2007 Bahadir Balban
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*/
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#ifndef __PLATFORM_PB11MPCORE_OFFSETS_H__
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#define __PLATFORM_PB11MPCORE_OFFSETS_H__
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/* Physical memory base */
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#define PHYS_MEM_START 0x00000000 /* inclusive */
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#define PHYS_MEM_END 0x10000000 /* 256 MB, exclusive */
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/*
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* These bases taken from where kernel is `physically' linked at,
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* also used to calculate virtual-to-physical translation offset.
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* See the linker script for their sources. PHYS_ADDR_BASE can't
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* use a linker variable because it's referred from assembler.
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*/
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#define PHYS_ADDR_BASE 0x100000
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/* Device memory base */
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#define PB11MPCORE_DEV_PHYS 0x10000000
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/* Device offsets in physical memory */
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#define PB11MPCORE_SYSTEM_REGISTERS 0x10000000 /* System registers */
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#define PB11MPCORE_SYSCTRL0_BASE 0x10001000 /* System controller 0 */
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#define PB11MPCORE_UART0_BASE 0x10009000 /* UART 0 */
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#define PB11MPCORE_UART1_BASE 0x1000A000 /* UART 1 */
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#define PB11MPCORE_UART2_BASE 0x1000B000 /* UART 2 */
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#define PB11MPCORE_UART3_BASE 0x1000C000 /* UART 3 */
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#define PB11MPCORE_WATCHDOG0_BASE 0x1000F000 /* WATCHDOG 0 */
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#define PB11MPCORE_WATCHDOG1_BASE 0x10010000 /* WATCHDOG 1 */
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#define PB11MPCORE_TIMER01_BASE 0x10011000 /* TIMER 0-1 */
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#define PB11MPCORE_TIMER23_BASE 0x10012000 /* TIMER 2-3 */
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#define PB11MPCORE_RTC_BASE 0x10017000 /* RTC interface */
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#define PB11MPCORE_TIMER45_BASE 0x10018000 /* TIMER 4-5 */
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#define PB11MPCORE_TIMER67_BASE 0x10019000 /* TIMER 6-7 */
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#define PB11MPCORE_SYSCTRL1_BASE 0x1001A000 /* System controller 1 */
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#define PB11MPCORE_GIC0_BASE 0x1E000000 /* GIC 0 */
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#define PB11MPCORE_GIC1_BASE 0x1E010000 /* GIC 1 */
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#define PB11MPCORE_GIC2_BASE 0x1E020000 /* GIC 2 */
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#define PB11MPCORE_GIC3_BASE 0x1E030000 /* GIC 3 */
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/*
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* Uart virtual address until a file-based console access
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* is available for userspace
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*/
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#define USERSPACE_UART_BASE 0x500000
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/*
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* Device offsets in virtual memory. They offset to some virtual
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* device base address. Each page on this virtual base is consecutively
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* allocated to devices. Nice and smooth.
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*/
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#define PB11MPCORE_SYSREGS_VOFFSET 0x00000000
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#define PB11MPCORE_SYSCTRL0_VOFFSET 0x00001000
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#define PB11MPCORE_SYSCTRL1_VOFFSET 0x00002000
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#define PB11MPCORE_UART0_VOFFSET 0x00003000
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#define PB11MPCORE_TIMER01_VOFFSET 0x00004000
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#define PB11MPCORE_GIC0_VOFFSET 0x00005000
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#define PB11MPCORE_GIC1_VOFFSET 0x00006000
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#define PB11MPCORE_GIC2_VOFFSET 0x00007000
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#define PB11MPCORE_GIC3_VOFFSET 0x00008000
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#define PB11MPCORE_SYSREGS_VBASE (IO_AREA0_VADDR + PB11MPCORE_SYSREGS_VOFFSET)
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#define PB11MPCORE_SYSCTRL0_VBASE (IO_AREA0_VADDR + PB11MPCORE_SYSCTRL0_VOFFSET)
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#define PB11MPCORE_SYSCTRL1_VBASE (IO_AREA0_VADDR + PB11MPCORE_SYSCTRL1_VOFFSET)
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#define PB11MPCORE_UART0_VBASE (IO_AREA0_VADDR + PB11MPCORE_UART0_VOFFSET)
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#define PB11MPCORE_TIMER01_VBASE (IO_AREA0_VADDR + PB11MPCORE_TIMER01_VOFFSET)
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#define PB11MPCORE_GIC0_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC0_VOFFSET)
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#define PB11MPCORE_GIC1_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC1_VOFFSET)
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#define PB11MPCORE_GIC2_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC2_VOFFSET)
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#define PB11MPCORE_GIC3_VBASE (IO_AREA0_VADDR + PB11MPCORE_GIC3_VOFFSET)
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#endif /* __PLATFORM_PB11MPCORE_OFFSETS_H__ */
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