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105 lines
3.6 KiB
C
105 lines
3.6 KiB
C
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#ifndef __PL110_CLCD_H__
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#define __PL110_CLCD_H__
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/* Register offsets */
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#define PL110_CLCD_TIMING0 0x000 /* Horizontal Axis Panel Control*/
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#define PL110_CLCD_TIMING1 0x004 /* Vertical Axis Panel Control */
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#define PL110_CLCD_TIMING2 0x008 /* Clock and Polarity Signal Control*/
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#define PL110_CLCD_TIMING3 0x00c /* Line End Control */
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#define PL110_CLCD_UPBASE 0x010 /* Upper Panel Frame Base Address*/
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#define PL110_CLCD_LPBASE 0x014 /* Lower Panel Frame Base Address */
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#define PL110_CLCD_IMSC 0x018 /* Interrupt Mast Set Clear */
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#define PL110_CLCD_CONTROL 0x01c /* CLCD Control */
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#define PL110_CLCD_RIS 0x020 /* Raw Interrupt Status */
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#define PL110_CLCD_MIS 0x024 /* Masked Interrupt Status */
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#define PL110_CLCD_ICR 0x028 /* Interrupt Clear */
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#define PL110_CLCD_UPCURR 0x02c /* Upper Panel Current Address Value */
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#define PL110_CLCD_LPCURR 0x030 /* Lower Panel Current Address Value */
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//#define PL110_LCD_PALETTE
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#define PL110_CLCD_PERIPHID0 0xfe0 /* Peripheral Identification */
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#define PL110_CLCD_PERIPHID1 0xfe4 /* Peripheral Identification */
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#define PL110_CLCD_PERIPHID2 0xfe8 /* Peripheral Identification */
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#define PL110_CLCD_PERIPHID3 0xfec /* Peripheral Identification */
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#define PL110_CLCD_PCELLID0 0xff0 /* Peripheral Identification */
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#define PL110_CLCD_PCELLID1 0xff4 /* PrimeCell Identification */
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#define PL110_CLCD_PCELLID2 0xff8 /* PrimeCell Identification */
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#define PL110_CLCD_PCELLID3 0xffc /* PrimeCell Identification */
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/* Scan mode */
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#define SCAN_VMODE_NONINTERLACED 0 /* non interlaced */
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#define SCAN_VMODE_INTERLACED 1 /* interlaced */
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#define SCAN_VMODE_DOUBLE 2 /* double scan */
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#define SCAN_VMODE_ODD_FLD_FIRST 4 /* interlaced: top line first */
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#define SCAN_VMODE_MASK 255
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/* Control Register Bits */
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#define PL110_CNTL_LCDEN (1 << 0)
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#define PL110_CNTL_LCDBPP1 (0 << 1)
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#define PL110_CNTL_LCDBPP2 (1 << 1)
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#define PL110_CNTL_LCDBPP4 (2 << 1)
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#define PL110_CNTL_LCDBPP8 (3 << 1)
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#define PL110_CNTL_LCDBPP16 (4 << 1)
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#define PL110_CNTL_LCDBPP16_565 (6 << 1)
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#define PL110_CNTL_LCDBPP24 (5 << 1)
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#define PL110_CNTL_LCDBW (1 << 4)
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#define PL110_CNTL_LCDTFT (1 << 5)
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#define PL110_CNTL_LCDMONO8 (1 << 6)
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#define PL110_CNTL_LCDDUAL (1 << 7)
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#define PL110_CNTL_BGR (1 << 8)
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#define PL110_CNTL_BEBO (1 << 9)
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#define PL110_CNTL_BEPO (1 << 10)
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#define PL110_CNTL_LCDPWR (1 << 11)
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#define PL110_CNTL_LCDVCOMP(x) ((x) << 12)
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#define PL110_CNTL_LDMAFIFOTIME (1 << 15)
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#define PL110_CNTL_WATERMARK (1 << 16)
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#define PL110_TIM2_CLKSEL (1 << 5)
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#define PL110_TIM2_IVS (1 << 11)
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#define PL110_TIM2_IHS (1 << 12)
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#define PL110_TIM2_IPC (1 << 13)
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#define PL110_TIM2_IOE (1 << 14)
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#define PL110_TIM2_BCD (1 << 26)
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struct videomode {
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const char *name; /* optional */
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unsigned int refresh; /* optional */
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unsigned int xres;
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unsigned int yres;
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unsigned int pixclock;
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unsigned int left_margin;
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unsigned int right_margin;
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unsigned int upper_margin;
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unsigned int lower_margin;
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unsigned int hsync_len;
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unsigned int vsync_len;
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unsigned int sync;
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unsigned int vmode;
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unsigned int flag;
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};
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struct pl110_clcd_panel {
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struct videomode mode;
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signed short width; /* width in mm */
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signed short height; /* height in mm */
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unsigned int tim2;
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unsigned int tim3;
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unsigned int cntl;
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unsigned int bpp:8,
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fixedtimings:1,
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grayscale:1;
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unsigned int connector;
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};
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struct pl110_clcd {
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unsigned int virt_base;
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struct pl110_clcd_panel *panel;
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char *frame_buffer;
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};
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void pl110_initialise(struct pl110_clcd *clcd, char *buf);
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#endif /* __PL110_CLCD_H__ */
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