mirror of
https://github.com/drasko/codezero.git
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381 lines
7.9 KiB
C
381 lines
7.9 KiB
C
/*
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* PL011 UART Generic driver implementation.
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*
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* Copyright (C) 2007 Bahadir Balban
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*
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* The particular intention of this code is that it has been carefully written
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* as decoupled from os-specific code and in a verbose way such that it clearly
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* demonstrates how the device operates, reducing the amount of time to be spent
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* for understanding the operational model and implementing a driver from
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* scratch. This is the very first to be such a driver so far, hopefully it will
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* turn out to be useful.
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*/
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#ifndef __PL011_UART_H__
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#define __PL011_UART_H__
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#include INC_PLAT(uart.h)
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#include INC_ARCH(io.h)
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#define PL011_BASE PLATFORM_CONSOLE_BASE
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/* Register offsets */
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#define PL011_UARTDR (PL011_BASE + 0x00)
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#define PL011_UARTRSR (PL011_BASE + 0x04)
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#define PL011_UARTECR (PL011_BASE + 0x04)
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#define PL011_UARTFR (PL011_BASE + 0x18)
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#define PL011_UARTILPR (PL011_BASE + 0x20)
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#define PL011_UARTIBRD (PL011_BASE + 0x24)
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#define PL011_UARTFBRD (PL011_BASE + 0x28)
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#define PL011_UARTLCR_H (PL011_BASE + 0x2C)
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#define PL011_UARTCR (PL011_BASE + 0x30)
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#define PL011_UARTIFLS (PL011_BASE + 0x34)
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#define PL011_UARTIMSC (PL011_BASE + 0x38)
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#define PL011_UARTRIS (PL011_BASE + 0x3C)
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#define PL011_UARTMIS (PL011_BASE + 0x40)
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#define PL011_UARTICR (PL011_BASE + 0x44)
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#define PL011_UARTDMACR (PL011_BASE + 0x48)
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/* IRQ bits for each uart irq event */
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#define PL011_RXIRQ (1 << 4)
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#define PL011_TXIRQ (1 << 5)
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#define PL011_RXTIMEOUTIRQ (1 << 6)
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#define PL011_FEIRQ (1 << 7)
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#define PL011_PEIRQ (1 << 8)
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#define PL011_BEIRQ (1 << 9)
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#define PL011_OEIRQ (1 << 10)
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struct pl011_uart;
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void pl011_initialise_driver();
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int pl011_initialise_device(struct pl011_uart *);
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int pl011_tx_char(char);
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int pl011_rx_char(char *);
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void pl011_set_baudrate(unsigned int, unsigned int);
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void pl011_set_irq_mask(unsigned int);
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void pl011_clr_irq_mask(unsigned int);
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void pl011_irq_handler(struct pl011_uart *);
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void pl011_tx_irq_handler(struct pl011_uart *, unsigned int);
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void pl011_rx_irq_handler(struct pl011_uart *, unsigned int);
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void pl011_error_irq_handler(struct pl011_uart *, unsigned int);
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struct pl011_uart_ops {
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int (*initialise)(struct pl011_uart *);
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int (*tx_char)(char);
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int (*rx_char)(char *);
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void (*set_baudrate)(unsigned int, unsigned int);
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void (*set_irq_mask)(unsigned int);
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void (*clr_irq_mask)(unsigned int);
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void (*irq_handler)(struct pl011_uart *);
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void (*tx_irq_handler)(struct pl011_uart *, unsigned int);
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void (*rx_irq_handler)(struct pl011_uart *, unsigned int);
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void (*error_irq_handler)(struct pl011_uart *, unsigned int);
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};
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struct pl011_uart {
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unsigned int base;
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struct pl011_uart_ops ops;
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unsigned int frame_errors;
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unsigned int parity_errors;
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unsigned int break_errors;
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unsigned int overrun_errors;
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unsigned int rx_timeout_errors;
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};
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#define PL011_UARTEN (1 << 0)
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static inline void pl011_uart_enable()
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{
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unsigned int val;
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val = 0;
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read(val, PL011_UARTCR);
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val |= PL011_UARTEN;
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write(val, PL011_UARTCR);
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return;
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}
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static inline void pl011_uart_disable()
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{
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unsigned int val;
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val = 0;
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read(val, PL011_UARTCR);
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val &= ~PL011_UARTEN;
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write(val, PL011_UARTCR);
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return;
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}
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#define PL011_TXE (1 << 8)
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static inline void pl011_tx_enable()
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{
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unsigned int val;
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val = 0;
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read(val, PL011_UARTCR);
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val |= PL011_TXE;
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write(val, PL011_UARTCR);
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return;
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}
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static inline void pl011_tx_disable()
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{
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unsigned int val;
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val = 0;
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read(val, PL011_UARTCR);
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val &= ~PL011_TXE;
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write(val, PL011_UARTCR);
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return;
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}
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#define PL011_RXE (1 << 9)
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static inline void pl011_rx_enable()
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{
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unsigned int val;
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val = 0;
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read(val, PL011_UARTCR);
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val |= PL011_RXE;
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write(val, PL011_UARTCR);
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return;
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}
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static inline void pl011_rx_disable()
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{
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unsigned int val;
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val = 0;
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read(val, PL011_UARTCR);
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val &= ~PL011_RXE;
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write(val, PL011_UARTCR);
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return;
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}
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#define PL011_TWO_STOPBITS_SELECT (1 << 3)
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static inline void pl011_set_stopbits(int stopbits)
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{
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unsigned int val;
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val = 0;
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read(val, PL011_UARTLCR_H);
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if(stopbits == 2) { /* Set to two bits */
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val |= PL011_TWO_STOPBITS_SELECT;
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} else { /* Default is 1 */
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val &= ~PL011_TWO_STOPBITS_SELECT;
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}
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write(val, PL011_UARTLCR_H);
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return;
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}
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#define PL011_PARITY_ENABLE (1 << 1)
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static inline void pl011_parity_enable()
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{
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unsigned int val;
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val = 0;
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read(val, PL011_UARTLCR_H);
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val |= PL011_PARITY_ENABLE;
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write(val, PL011_UARTLCR_H);
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return;
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}
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static inline void pl011_parity_disable()
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{
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unsigned int val;
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val = 0;
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read(val, PL011_UARTLCR_H);
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val &= ~PL011_PARITY_ENABLE;
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write(val, PL011_UARTLCR_H);
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return;
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}
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#define PL011_PARITY_EVEN (1 << 2)
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static inline void pl011_set_parity_even()
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{
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unsigned int val;
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val = 0;
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read(val, PL011_UARTLCR_H);
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val |= PL011_PARITY_EVEN;
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write(val, PL011_UARTLCR_H);
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return;
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}
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static inline void pl011_set_parity_odd()
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{
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unsigned int val;
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val = 0;
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read(val, PL011_UARTLCR_H);
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val &= ~PL011_PARITY_EVEN;
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write(val, PL011_UARTLCR_H);
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return;
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}
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#define PL011_ENABLE_FIFOS (1 << 4)
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static inline void pl011_enable_fifos()
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{
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unsigned int val;
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val = 0;
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read(val, PL011_UARTLCR_H);
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val |= PL011_ENABLE_FIFOS;
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write(val, PL011_UARTLCR_H);
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return;
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}
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static inline void pl011_disable_fifos()
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{
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unsigned int val;
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val = 0;
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read(val, PL011_UARTLCR_H);
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val &= ~PL011_ENABLE_FIFOS;
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write(val, PL011_UARTLCR_H);
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return;
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}
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#define PL011_WORD_WIDTH_SHIFT (5)
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/* Sets the transfer word width for the data register. */
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static inline void pl011_set_word_width(int size)
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{
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unsigned int val;
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val = 0;
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if(size < 5 || size > 8) /* Default is 8 */
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size = 8;
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/* Clear size field */
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read(val, PL011_UARTLCR_H);
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val &= ~(0x3 << PL011_WORD_WIDTH_SHIFT);
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write(val, PL011_UARTLCR_H);
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/* The formula is to write 5 less of size given:
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* 11 = 8 bits
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* 10 = 7 bits
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* 01 = 6 bits
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* 00 = 5 bits
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*/
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read(val, PL011_UARTLCR_H);
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val |= (size - 5) << PL011_WORD_WIDTH_SHIFT;
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write(val, PL011_UARTLCR_H);
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return;
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}
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/*
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* Defines at which level of fifo fullness an irq will be generated.
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* @xfer: tx fifo = 0, rx fifo = 1
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* @level: Generate irq if:
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* 0 rxfifo >= 1/8 full txfifo <= 1/8 full
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* 1 rxfifo >= 1/4 full txfifo <= 1/4 full
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* 2 rxfifo >= 1/2 full txfifo <= 1/2 full
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* 3 rxfifo >= 3/4 full txfifo <= 3/4 full
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* 4 rxfifo >= 7/8 full txfifo <= 7/8 full
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* 5-7 reserved reserved
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*/
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static inline void pl011_set_irq_fifolevel(unsigned int xfer, unsigned int level)
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{
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if(xfer != 1 && xfer != 0) /* Invalid fifo */
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return;
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if(level > 4) /* Invalid level */
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return;
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write(level << (xfer * 3), PL011_UARTIFLS);
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return;
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}
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/* returns which irqs are masked */
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static inline unsigned int pl011_read_irqmask(void)
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{
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unsigned int flags;
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read(flags, PL011_UARTIMSC);
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return flags;
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}
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/* returns masked irq status */
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static inline unsigned int pl011_read_irqstat(void)
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{
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unsigned int irqstatus;
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read(irqstatus, PL011_UARTMIS);
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return irqstatus;
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}
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/* Clears the given asserted irqs */
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static inline void pl011_irq_clear(unsigned int flags)
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{
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if(flags > 0x3FF) { /* Invalid irq clearing bitvector */
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return;
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}
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/* Simply write the flags since it's a write-only register */
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write(flags, PL011_UARTICR);
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return;
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}
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#define PL011_TXDMAEN (1 << 1)
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#define PL011_RXDMAEN (1 << 0)
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/* Enables dma transfers for uart. The dma controller
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* must be initialised, set-up and enabled separately.
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*/
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static inline void pl011_tx_dma_enable()
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{
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unsigned int val;
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val = 0;
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read(val, PL011_UARTDMACR);
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val |= PL011_TXDMAEN;
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write(val, PL011_UARTDMACR);
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return;
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}
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/* Disables dma transfers for uart */
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static inline void pl011_tx_dma_disable()
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{
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unsigned int val;
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val = 0;
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read(val, PL011_UARTDMACR);
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val &= ~PL011_TXDMAEN;
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write(val, PL011_UARTDMACR);
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return;
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}
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static inline void pl011_rx_dma_enable()
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{
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unsigned int val;
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val = 0;
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read(val, PL011_UARTDMACR);
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val |= PL011_RXDMAEN;
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write(val, PL011_UARTDMACR);
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return;
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}
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static inline void pl011_rx_dma_disable()
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{
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unsigned int val;
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val = 0;
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read(val, PL011_UARTDMACR);
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val &= ~PL011_RXDMAEN;
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write(val, PL011_UARTDMACR);
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return;
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}
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#endif /* __PL011_UART__ */
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