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    //! Sends "Hello, world!" through the ITM port 0
    //!
    //! ITM is much faster than semihosting. Like 4 orders of magnitude or so.
    //!
    //! **NOTE** Cortex-M0 chips don't support ITM.
    //!
    //! You'll have to connect the microcontroller's SWO pin to the SWD interface. Note that some
    //! development boards don't provide this option.
    //!
    //! You'll need [`itmdump`] to receive the message on the host plus you'll need to uncomment two
    //! `monitor` commands in the `.gdbinit` file.
    //!
    //! [`itmdump`]: https://docs.rs/itm/0.2.1/itm/
    //!
    //! ---
    //!
    //! ```
    //!
    //! #![no_main]
    //! #![no_std]
    //!
    //! #[macro_use]
    //! extern crate cortex_m;
    //! #[macro_use]
    //! extern crate cortex_m_rt as rt;
    //! extern crate panic_semihosting;
    //!
    //! use cortex_m::{asm, Peripherals};
    //! use rt::ExceptionFrame;
    //!
    //! entry!(main);
    //!
    //! fn main() -> ! {
    //!     let mut p = Peripherals::take().unwrap();
    //!     let stim = &mut p.ITM.stim[0];
    //!
    //!     iprintln!(stim, "Hello, world!");
    //!
    //!     loop {
    //!         asm::bkpt();
    //!     }
    //! }
    //!
    //! // define the hard fault handler
    //! exception!(HardFault, hard_fault);
    //!
    //! fn hard_fault(ef: &ExceptionFrame) -> ! {
    //!     panic!("HardFault at {:#?}", ef);
    //! }
    //!
    //! // define the default exception handler
    //! exception!(*, default_handler);
    //!
    //! fn default_handler(irqn: i16) {
    //!     panic!("Unhandled exception (IRQn = {})", irqn);
    //! }
    //! ```
    // Auto-generated. Do not modify.

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