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    //! Instrumentation Trace Macrocell
    //!
    //! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)

    use core::cell::UnsafeCell;
    use core::ptr;

    use volatile_register::{RO, RW, WO};

    /// Register block
    #[repr(C)]
    pub struct RegisterBlock {
        /// Stimulus Port
        pub stim: [Stim; 256],
        reserved0: [u32; 640],
        /// Trace Enable
        pub ter: [RW<u32>; 8],
        reserved1: [u32; 8],
        /// Trace Privilege
        pub tpr: RW<u32>,
        reserved2: [u32; 15],
        /// Trace Control
        pub tcr: RW<u32>,
        reserved3: [u32; 75],
        /// Lock Access
        pub lar: WO<u32>,
        /// Lock Status
        pub lsr: RO<u32>,
    }

    /// Stimulus Port
    pub struct Stim {
        register: UnsafeCell<u32>,
    }

    impl Stim {
        /// Writes an `u8` payload into the stimulus port
        pub fn write_u8(&mut self, value: u8) {
            unsafe { ptr::write_volatile(self.register.get() as *mut u8, value) }
        }

        /// Writes an `u16` payload into the stimulus port
        pub fn write_u16(&mut self, value: u16) {
            unsafe { ptr::write_volatile(self.register.get() as *mut u16, value) }
        }

        /// Writes an `u32` payload into the stimulus port
        pub fn write_u32(&mut self, value: u32) {
            unsafe { ptr::write_volatile(self.register.get(), value) }
        }

        /// Returns `true` if the stimulus port is ready to accept more data
        pub fn is_fifo_ready(&self) -> bool {
            unsafe { ptr::read_volatile(self.register.get()) == 1 }
        }
    }

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