commit 0c3bcdf02a25f59ef92be0c1c1eda31947868427 Author: Travis CI User Date: Mon Sep 3 15:09:46 2018 +0000 Update documentation diff --git a/.lock b/.lock new file mode 100755 index 0000000..e69de29 diff --git a/COPYRIGHT.txt b/COPYRIGHT.txt new file mode 100644 index 0000000..c69861a --- /dev/null +++ b/COPYRIGHT.txt @@ -0,0 +1,59 @@ +These documentation pages include resources by third parties. This copyright +file applies only to those resources. The following third party resources are +included, and carry their own copyright notices and license terms: + +* Fira Sans (FiraSans-Regular.woff, FiraSans-Medium.woff): + + Copyright (c) 2014, Mozilla Foundation https://mozilla.org/ + with Reserved Font Name Fira Sans. + + Copyright (c) 2014, Telefonica S.A. + + Licensed under the SIL Open Font License, Version 1.1. + See FiraSans-LICENSE.txt. + +* Heuristica (Heuristica-Italic.woff): + + Copyright 1989, 1991 Adobe Systems Incorporated. All rights reserved. + Utopia is either a registered trademark or trademark of Adobe Systems + Incorporated in the United States and/or other countries. Used under + license. + + Copyright 2006 Han The Thanh, Vntopia font family, http://vntex.sf.net + + Copyright (c) 2008-2012, Andrey V. Panov (panov@canopus.iacp.dvo.ru), + with Reserved Font Name Heuristica. + + Licensed under the SIL Open Font License, Version 1.1. + See Heuristica-LICENSE.txt. + +* rustdoc.css, main.js, and playpen.js: + + Copyright 2015 The Rust Developers. + Licensed under the Apache License, Version 2.0 (see LICENSE-APACHE.txt) or + the MIT license (LICENSE-MIT.txt) at your option. + +* normalize.css: + + Copyright (c) Nicolas Gallagher and Jonathan Neal. + Licensed under the MIT license (see LICENSE-MIT.txt). + +* Source Code Pro (SourceCodePro-Regular.woff, SourceCodePro-Semibold.woff): + + Copyright 2010, 2012 Adobe Systems Incorporated (http://www.adobe.com/), + with Reserved Font Name 'Source'. All Rights Reserved. Source is a trademark + of Adobe Systems Incorporated in the United States and/or other countries. + + Licensed under the SIL Open Font License, Version 1.1. + See SourceCodePro-LICENSE.txt. + +* Source Serif Pro (SourceSerifPro-Regular.woff, SourceSerifPro-Bold.woff): + + Copyright 2014 Adobe Systems Incorporated (http://www.adobe.com/), with + Reserved Font Name 'Source'. All Rights Reserved. Source is a trademark of + Adobe Systems Incorporated in the United States and/or other countries. + + Licensed under the SIL Open Font License, Version 1.1. + See SourceSerifPro-LICENSE.txt. + +This copyright file is intended to be distributed with rustdoc output. diff --git a/FiraSans-LICENSE.txt b/FiraSans-LICENSE.txt new file mode 100644 index 0000000..b4a3967 --- /dev/null +++ b/FiraSans-LICENSE.txt @@ -0,0 +1,99 @@ +Copyright (c) 2014, Mozilla Foundation https://mozilla.org/ +with Reserved Font Name Fira Sans. + +Copyright (c) 2014, Mozilla Foundation https://mozilla.org/ +with Reserved Font Name Fira Mono. + +Copyright (c) 2014, Telefonica S.A. + +This Font Software is licensed under the SIL Open Font License, Version 1.1. +This license is copied below, and is also available with a FAQ at: +http://scripts.sil.org/OFL + + +----------------------------------------------------------- +SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +----------------------------------------------------------- + +PREAMBLE +The goals of the Open Font License (OFL) are to stimulate worldwide +development of collaborative font projects, to support the font creation +efforts of academic and linguistic communities, and to provide a free and +open framework in which fonts may be shared and improved in partnership +with others. + +The OFL allows the licensed fonts to be used, studied, modified and +redistributed freely as long as they are not sold by themselves. The +fonts, including any derivative works, can be bundled, embedded, +redistributed and/or sold with any software provided that any reserved +names are not used by derivative works. The fonts and derivatives, +however, cannot be released under any other type of license. The +requirement for fonts to remain under this license does not apply +to any document created using the fonts or their derivatives. + +DEFINITIONS +"Font Software" refers to the set of files released by the Copyright +Holder(s) under this license and clearly marked as such. This may +include source files, build scripts and documentation. + +"Reserved Font Name" refers to any names specified as such after the +copyright statement(s). + +"Original Version" refers to the collection of Font Software components as +distributed by the Copyright Holder(s). + +"Modified Version" refers to any derivative made by adding to, deleting, +or substituting -- in part or in whole -- any of the components of the +Original Version, by changing formats or by porting the Font Software to a +new environment. + +"Author" refers to any designer, engineer, programmer, technical +writer or other person who contributed to the Font Software. + +PERMISSION & CONDITIONS +Permission is hereby granted, free of charge, to any person obtaining +a copy of the Font Software, to use, study, copy, merge, embed, modify, +redistribute, and sell modified and unmodified copies of the Font +Software, subject to the following conditions: + +1) Neither the Font Software nor any of its individual components, +in Original or Modified Versions, may be sold by itself. + +2) Original or Modified Versions of the Font Software may be bundled, +redistributed and/or sold with any software, provided that each copy +contains the above copyright notice and this license. These can be +included either as stand-alone text files, human-readable headers or +in the appropriate machine-readable metadata fields within text or +binary files as long as those fields can be easily viewed by the user. + +3) No Modified Version of the Font Software may use the Reserved Font +Name(s) unless explicit written permission is granted by the corresponding +Copyright Holder. This restriction only applies to the primary font name as +presented to the users. + +4) The name(s) of the Copyright Holder(s) or the Author(s) of the Font +Software shall not be used to promote, endorse or advertise any +Modified Version, except to acknowledge the contribution(s) of the +Copyright Holder(s) and the Author(s) or with their explicit written +permission. + +5) The Font Software, modified or unmodified, in part or in whole, +must be distributed entirely under this license, and must not be +distributed under any other license. The requirement for fonts to +remain under this license does not apply to any document created +using the Font Software. + +TERMINATION +This license becomes null and void if any of the above conditions are +not met. + +DISCLAIMER +THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT +OF COPYRIGHT, PATENT, TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL THE +COPYRIGHT HOLDER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +INCLUDING ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL +DAMAGES, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM +OTHER DEALINGS IN THE FONT SOFTWARE. diff --git a/FiraSans-Medium.woff b/FiraSans-Medium.woff new file mode 100644 index 0000000..5627227 Binary files /dev/null and b/FiraSans-Medium.woff differ diff --git a/FiraSans-Regular.woff b/FiraSans-Regular.woff new file mode 100644 index 0000000..9ff4044 Binary files /dev/null and b/FiraSans-Regular.woff differ diff --git a/Heuristica-Italic.woff b/Heuristica-Italic.woff new file mode 100644 index 0000000..b0cebf0 Binary files /dev/null and b/Heuristica-Italic.woff differ diff --git a/Heuristica-LICENSE.txt b/Heuristica-LICENSE.txt new file mode 100644 index 0000000..dd85e40 --- /dev/null +++ b/Heuristica-LICENSE.txt @@ -0,0 +1,101 @@ +Copyright 1989, 1991 Adobe Systems Incorporated. All rights reserved. +Utopia is either a registered trademark or trademark of Adobe Systems +Incorporated in the United States and/or other countries. Used under +license. + +Copyright 2006 Han The Thanh, Vntopia font family, http://vntex.sf.net + +Copyright (c) 2008-2012, Andrey V. Panov (panov@canopus.iacp.dvo.ru), +with Reserved Font Name Heuristica. + +This Font Software is licensed under the SIL Open Font License, Version 1.1. +This license is copied below, and is also available with a FAQ at: +http://scripts.sil.org/OFL + + +----------------------------------------------------------- +SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +----------------------------------------------------------- + +PREAMBLE +The goals of the Open Font License (OFL) are to stimulate worldwide +development of collaborative font projects, to support the font creation +efforts of academic and linguistic communities, and to provide a free and +open framework in which fonts may be shared and improved in partnership +with others. + +The OFL allows the licensed fonts to be used, studied, modified and +redistributed freely as long as they are not sold by themselves. The +fonts, including any derivative works, can be bundled, embedded, +redistributed and/or sold with any software provided that any reserved +names are not used by derivative works. The fonts and derivatives, +however, cannot be released under any other type of license. The +requirement for fonts to remain under this license does not apply +to any document created using the fonts or their derivatives. + +DEFINITIONS +"Font Software" refers to the set of files released by the Copyright +Holder(s) under this license and clearly marked as such. This may +include source files, build scripts and documentation. + +"Reserved Font Name" refers to any names specified as such after the +copyright statement(s). + +"Original Version" refers to the collection of Font Software components as +distributed by the Copyright Holder(s). + +"Modified Version" refers to any derivative made by adding to, deleting, +or substituting -- in part or in whole -- any of the components of the +Original Version, by changing formats or by porting the Font Software to a +new environment. + +"Author" refers to any designer, engineer, programmer, technical +writer or other person who contributed to the Font Software. + +PERMISSION & CONDITIONS +Permission is hereby granted, free of charge, to any person obtaining +a copy of the Font Software, to use, study, copy, merge, embed, modify, +redistribute, and sell modified and unmodified copies of the Font +Software, subject to the following conditions: + +1) Neither the Font Software nor any of its individual components, +in Original or Modified Versions, may be sold by itself. + +2) Original or Modified Versions of the Font Software may be bundled, +redistributed and/or sold with any software, provided that each copy +contains the above copyright notice and this license. These can be +included either as stand-alone text files, human-readable headers or +in the appropriate machine-readable metadata fields within text or +binary files as long as those fields can be easily viewed by the user. + +3) No Modified Version of the Font Software may use the Reserved Font +Name(s) unless explicit written permission is granted by the corresponding +Copyright Holder. This restriction only applies to the primary font name as +presented to the users. + +4) The name(s) of the Copyright Holder(s) or the Author(s) of the Font +Software shall not be used to promote, endorse or advertise any +Modified Version, except to acknowledge the contribution(s) of the +Copyright Holder(s) and the Author(s) or with their explicit written +permission. + +5) The Font Software, modified or unmodified, in part or in whole, +must be distributed entirely under this license, and must not be +distributed under any other license. The requirement for fonts to +remain under this license does not apply to any document created +using the Font Software. + +TERMINATION +This license becomes null and void if any of the above conditions are +not met. + +DISCLAIMER +THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT +OF COPYRIGHT, PATENT, TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL THE +COPYRIGHT HOLDER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +INCLUDING ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL +DAMAGES, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM +OTHER DEALINGS IN THE FONT SOFTWARE. diff --git a/LICENSE-APACHE.txt b/LICENSE-APACHE.txt new file mode 100644 index 0000000..16fe87b --- /dev/null +++ b/LICENSE-APACHE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + +Copyright [yyyy] [name of copyright owner] + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. diff --git a/LICENSE-MIT.txt b/LICENSE-MIT.txt new file mode 100644 index 0000000..31aa793 --- /dev/null +++ b/LICENSE-MIT.txt @@ -0,0 +1,23 @@ +Permission is hereby granted, free of charge, to any +person obtaining a copy of this software and associated +documentation files (the "Software"), to deal in the +Software without restriction, including without +limitation the rights to use, copy, modify, merge, +publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software +is furnished to do so, subject to the following +conditions: + +The above copyright notice and this permission notice +shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF +ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A +PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT +SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR +IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. diff --git a/SourceCodePro-LICENSE.txt b/SourceCodePro-LICENSE.txt new file mode 100644 index 0000000..0754257 --- /dev/null +++ b/SourceCodePro-LICENSE.txt @@ -0,0 +1,93 @@ +Copyright 2010, 2012 Adobe Systems Incorporated (http://www.adobe.com/), with Reserved Font Name 'Source'. All Rights Reserved. Source is a trademark of Adobe Systems Incorporated in the United States and/or other countries. + +This Font Software is licensed under the SIL Open Font License, Version 1.1. + +This license is copied below, and is also available with a FAQ at: http://scripts.sil.org/OFL + + +----------------------------------------------------------- +SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +----------------------------------------------------------- + +PREAMBLE +The goals of the Open Font License (OFL) are to stimulate worldwide +development of collaborative font projects, to support the font creation +efforts of academic and linguistic communities, and to provide a free and +open framework in which fonts may be shared and improved in partnership +with others. + +The OFL allows the licensed fonts to be used, studied, modified and +redistributed freely as long as they are not sold by themselves. The +fonts, including any derivative works, can be bundled, embedded, +redistributed and/or sold with any software provided that any reserved +names are not used by derivative works. The fonts and derivatives, +however, cannot be released under any other type of license. The +requirement for fonts to remain under this license does not apply +to any document created using the fonts or their derivatives. + +DEFINITIONS +"Font Software" refers to the set of files released by the Copyright +Holder(s) under this license and clearly marked as such. This may +include source files, build scripts and documentation. + +"Reserved Font Name" refers to any names specified as such after the +copyright statement(s). + +"Original Version" refers to the collection of Font Software components as +distributed by the Copyright Holder(s). + +"Modified Version" refers to any derivative made by adding to, deleting, +or substituting -- in part or in whole -- any of the components of the +Original Version, by changing formats or by porting the Font Software to a +new environment. + +"Author" refers to any designer, engineer, programmer, technical +writer or other person who contributed to the Font Software. + +PERMISSION & CONDITIONS +Permission is hereby granted, free of charge, to any person obtaining +a copy of the Font Software, to use, study, copy, merge, embed, modify, +redistribute, and sell modified and unmodified copies of the Font +Software, subject to the following conditions: + +1) Neither the Font Software nor any of its individual components, +in Original or Modified Versions, may be sold by itself. + +2) Original or Modified Versions of the Font Software may be bundled, +redistributed and/or sold with any software, provided that each copy +contains the above copyright notice and this license. These can be +included either as stand-alone text files, human-readable headers or +in the appropriate machine-readable metadata fields within text or +binary files as long as those fields can be easily viewed by the user. + +3) No Modified Version of the Font Software may use the Reserved Font +Name(s) unless explicit written permission is granted by the corresponding +Copyright Holder. This restriction only applies to the primary font name as +presented to the users. + +4) The name(s) of the Copyright Holder(s) or the Author(s) of the Font +Software shall not be used to promote, endorse or advertise any +Modified Version, except to acknowledge the contribution(s) of the +Copyright Holder(s) and the Author(s) or with their explicit written +permission. + +5) The Font Software, modified or unmodified, in part or in whole, +must be distributed entirely under this license, and must not be +distributed under any other license. The requirement for fonts to +remain under this license does not apply to any document created +using the Font Software. + +TERMINATION +This license becomes null and void if any of the above conditions are +not met. + +DISCLAIMER +THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT +OF COPYRIGHT, PATENT, TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL THE +COPYRIGHT HOLDER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +INCLUDING ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL +DAMAGES, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM +OTHER DEALINGS IN THE FONT SOFTWARE. diff --git a/SourceCodePro-Regular.woff b/SourceCodePro-Regular.woff new file mode 100644 index 0000000..5576670 Binary files /dev/null and b/SourceCodePro-Regular.woff differ diff --git a/SourceCodePro-Semibold.woff b/SourceCodePro-Semibold.woff new file mode 100644 index 0000000..ca972a1 Binary files /dev/null and b/SourceCodePro-Semibold.woff differ diff --git a/SourceSerifPro-Bold.woff b/SourceSerifPro-Bold.woff new file mode 100644 index 0000000..ac1b1b3 Binary files /dev/null and b/SourceSerifPro-Bold.woff differ diff --git a/SourceSerifPro-LICENSE.txt b/SourceSerifPro-LICENSE.txt new file mode 100644 index 0000000..b77d653 --- /dev/null +++ b/SourceSerifPro-LICENSE.txt @@ -0,0 +1,93 @@ +Copyright 2014 Adobe Systems Incorporated (http://www.adobe.com/), with Reserved Font Name 'Source'. All Rights Reserved. Source is a trademark of Adobe Systems Incorporated in the United States and/or other countries. + +This Font Software is licensed under the SIL Open Font License, Version 1.1. + +This license is copied below, and is also available with a FAQ at: http://scripts.sil.org/OFL + + +----------------------------------------------------------- +SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +----------------------------------------------------------- + +PREAMBLE +The goals of the Open Font License (OFL) are to stimulate worldwide +development of collaborative font projects, to support the font creation +efforts of academic and linguistic communities, and to provide a free and +open framework in which fonts may be shared and improved in partnership +with others. + +The OFL allows the licensed fonts to be used, studied, modified and +redistributed freely as long as they are not sold by themselves. The +fonts, including any derivative works, can be bundled, embedded, +redistributed and/or sold with any software provided that any reserved +names are not used by derivative works. The fonts and derivatives, +however, cannot be released under any other type of license. The +requirement for fonts to remain under this license does not apply +to any document created using the fonts or their derivatives. + +DEFINITIONS +"Font Software" refers to the set of files released by the Copyright +Holder(s) under this license and clearly marked as such. This may +include source files, build scripts and documentation. + +"Reserved Font Name" refers to any names specified as such after the +copyright statement(s). + +"Original Version" refers to the collection of Font Software components as +distributed by the Copyright Holder(s). + +"Modified Version" refers to any derivative made by adding to, deleting, +or substituting -- in part or in whole -- any of the components of the +Original Version, by changing formats or by porting the Font Software to a +new environment. + +"Author" refers to any designer, engineer, programmer, technical +writer or other person who contributed to the Font Software. + +PERMISSION & CONDITIONS +Permission is hereby granted, free of charge, to any person obtaining +a copy of the Font Software, to use, study, copy, merge, embed, modify, +redistribute, and sell modified and unmodified copies of the Font +Software, subject to the following conditions: + +1) Neither the Font Software nor any of its individual components, +in Original or Modified Versions, may be sold by itself. + +2) Original or Modified Versions of the Font Software may be bundled, +redistributed and/or sold with any software, provided that each copy +contains the above copyright notice and this license. These can be +included either as stand-alone text files, human-readable headers or +in the appropriate machine-readable metadata fields within text or +binary files as long as those fields can be easily viewed by the user. + +3) No Modified Version of the Font Software may use the Reserved Font +Name(s) unless explicit written permission is granted by the corresponding +Copyright Holder. This restriction only applies to the primary font name as +presented to the users. + +4) The name(s) of the Copyright Holder(s) or the Author(s) of the Font +Software shall not be used to promote, endorse or advertise any +Modified Version, except to acknowledge the contribution(s) of the +Copyright Holder(s) and the Author(s) or with their explicit written +permission. + +5) The Font Software, modified or unmodified, in part or in whole, +must be distributed entirely under this license, and must not be +distributed under any other license. The requirement for fonts to +remain under this license does not apply to any document created +using the Font Software. + +TERMINATION +This license becomes null and void if any of the above conditions are +not met. + +DISCLAIMER +THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT +OF COPYRIGHT, PATENT, TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL THE +COPYRIGHT HOLDER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +INCLUDING ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL +DAMAGES, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM +OTHER DEALINGS IN THE FONT SOFTWARE. diff --git a/SourceSerifPro-Regular.woff b/SourceSerifPro-Regular.woff new file mode 100644 index 0000000..e8c43b8 Binary files /dev/null and b/SourceSerifPro-Regular.woff differ diff --git a/aliases.js b/aliases.js new file mode 100644 index 0000000..10ec5b1 --- /dev/null +++ b/aliases.js @@ -0,0 +1,11 @@ +var ALIASES = {}; +ALIASES['aligned'] = {}; +ALIASES['bare_metal'] = {}; +ALIASES['cortex_m'] = {}; +ALIASES['cortex_m_quickstart'] = {}; +ALIASES['cortex_m_rt'] = {}; +ALIASES['cortex_m_semihosting'] = {}; +ALIASES['panic_semihosting'] = {}; +ALIASES['r0'] = {}; +ALIASES['vcell'] = {}; +ALIASES['volatile_register'] = {}; diff --git a/aligned/Aligned.t.html b/aligned/Aligned.t.html new file mode 100644 index 0000000..338930e --- /dev/null +++ b/aligned/Aligned.t.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to struct.Aligned.html...

+ + + \ No newline at end of file diff --git a/aligned/Aligned.v.html b/aligned/Aligned.v.html new file mode 100644 index 0000000..ab20d62 --- /dev/null +++ b/aligned/Aligned.v.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to fn.Aligned.html...

+ + + \ No newline at end of file diff --git a/aligned/Alignment.t.html b/aligned/Alignment.t.html new file mode 100644 index 0000000..d5b97ce --- /dev/null +++ b/aligned/Alignment.t.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to trait.Alignment.html...

+ + + \ No newline at end of file diff --git a/aligned/all.html b/aligned/all.html new file mode 100644 index 0000000..d30b426 --- /dev/null +++ b/aligned/all.html @@ -0,0 +1,3 @@ +List of all items in this crate

[−] + + List of all items

Structs

Traits

Functions

\ No newline at end of file diff --git a/aligned/fn.Aligned.html b/aligned/fn.Aligned.html new file mode 100644 index 0000000..ef30fd1 --- /dev/null +++ b/aligned/fn.Aligned.html @@ -0,0 +1,2 @@ +aligned::Aligned - Rust

[−][src]Function aligned::Aligned

pub fn Aligned<ALIGNMENT, ARRAY>(array: ARRAY) -> Aligned<ALIGNMENT, ARRAY> where
    ALIGNMENT: Alignment, 

Aligned constructor

+
\ No newline at end of file diff --git a/aligned/index.html b/aligned/index.html new file mode 100644 index 0000000..cedea52 --- /dev/null +++ b/aligned/index.html @@ -0,0 +1,53 @@ +aligned - Rust

[−][src]Crate aligned

Statically allocated arrays with guaranteed memory alignments

+

Examples

+
+#![feature(const_fn)]
+
+use std::mem;
+
+use aligned::Aligned;
+
+// Array aligned to a 2 byte boundary
+static X: Aligned<u16, [u8; 3]> = Aligned([0; 3]);
+
+// Array aligned to a 4 byte boundary
+static Y: Aligned<u32, [u8; 3]> = Aligned([0; 3]);
+
+// Unaligned array
+static Z: [u8; 3] = [0; 3];
+
+// You can allocate the aligned arrays on the stack too
+let w: Aligned<u64, _> = Aligned([0u8; 3]);
+
+assert_eq!(mem::align_of_val(&X), 2);
+assert_eq!(mem::align_of_val(&Y), 4);
+assert_eq!(mem::align_of_val(&Z), 1);
+assert_eq!(mem::align_of_val(&w), 8);
+

Structs

+ + + + +
Aligned +

An ARRAY aligned to mem::align_of::<ALIGNMENT>() bytes

+ +

Traits

+ + + + +
Alignment +

IMPLEMENTATION DETAIL

+ +

Functions

+ + + + +
Aligned +

Aligned constructor

+ +
\ No newline at end of file diff --git a/aligned/sidebar-items.js b/aligned/sidebar-items.js new file mode 100644 index 0000000..62178cf --- /dev/null +++ b/aligned/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"fn":[["Aligned","`Aligned` constructor"]],"struct":[["Aligned","An `ARRAY` aligned to `mem::align_of::()` bytes"]],"trait":[["Alignment","IMPLEMENTATION DETAIL"]]}); \ No newline at end of file diff --git a/aligned/struct.Aligned.html b/aligned/struct.Aligned.html new file mode 100644 index 0000000..e560ed9 --- /dev/null +++ b/aligned/struct.Aligned.html @@ -0,0 +1,323 @@ +aligned::Aligned - Rust

[−][src]Struct aligned::Aligned

pub struct Aligned<ALIGNMENT, ARRAY> where
    ARRAY: ?Sized,  {
+    pub array: ARRAY,
+    // some fields omitted
+}

An ARRAY aligned to mem::align_of::<ALIGNMENT>() bytes

+

+ Fields

+ +

The array

+

Trait Implementations

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 0]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 0]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 0]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 0]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 1]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 1]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 1]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 1]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 2]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 2]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 2]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 2]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 3]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 3]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 3]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 3]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 4]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 4]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 4]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 4]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 5]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 5]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 5]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 5]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 6]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 6]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 6]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 6]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 7]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 7]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 7]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 7]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 8]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 8]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 8]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 8]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 9]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 9]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 9]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 9]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 10]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 10]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 10]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 10]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 11]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 11]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 11]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 11]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 12]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 12]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 12]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 12]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 13]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 13]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 13]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 13]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 14]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 14]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 14]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 14]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 15]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 15]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 15]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 15]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 16]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 16]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 16]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 16]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 17]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 17]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 17]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 17]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 18]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 18]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 18]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 18]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 19]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 19]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 19]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 19]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 20]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 20]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 20]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 20]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 21]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 21]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 21]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 21]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 22]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 22]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 22]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 22]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 23]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 23]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 23]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 23]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 24]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 24]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 24]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 24]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 25]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 25]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 25]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 25]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 26]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 26]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 26]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 26]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 27]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 27]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 27]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 27]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 28]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 28]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 28]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 28]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 29]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 29]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 29]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 29]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 30]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 30]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 30]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 30]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 31]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 31]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 31]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 31]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 32]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 32]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 32]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 32]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 64]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 64]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 64]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 64]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 128]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 128]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 128]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 128]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 256]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 256]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 256]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 256]>
[src]

Performs the mutable indexing (container[index]) operation.

+

impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 1024]>
[src]

+

The resulting type after dereferencing.

+

Dereferences the value.

+

impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 1024]>
[src]

Mutably dereferences the value.

+

impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 1024]>
[src]

+

The returned type after indexing.

+

Performs the indexing (container[index]) operation.

+

impl<T, ALIGNMENT> IndexMut<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 1024]>
[src]

Performs the mutable indexing (container[index]) operation.

+

Auto Trait Implementations

impl<ALIGNMENT, ARRAY: ?Sized> Send for Aligned<ALIGNMENT, ARRAY> where
    ALIGNMENT: Send,
    ARRAY: Send, 

impl<ALIGNMENT, ARRAY: ?Sized> Sync for Aligned<ALIGNMENT, ARRAY> where
    ALIGNMENT: Sync,
    ARRAY: Sync, 

Blanket Implementations

impl<T, U> TryFrom for T where
    T: From<U>, 
[src]

+
🔬 This is a nightly-only experimental API. (try_from)

The type returned in the event of a conversion error.

+

🔬 This is a nightly-only experimental API. (try_from)

Performs the conversion.

+

impl<T> From for T
[src]

Performs the conversion.

+

impl<T, U> TryInto for T where
    U: TryFrom<T>, 
[src]

+
🔬 This is a nightly-only experimental API. (try_from)

The type returned in the event of a conversion error.

+

🔬 This is a nightly-only experimental API. (try_from)

Performs the conversion.

+

impl<T, U> Into for T where
    U: From<T>, 
[src]

Performs the conversion.

+

impl<T> Borrow for T where
    T: ?Sized, 
[src]

Immutably borrows from an owned value. Read more

+

impl<T> BorrowMut for T where
    T: ?Sized, 
[src]

Mutably borrows from an owned value. Read more

+

impl<T> Any for T where
    T: 'static + ?Sized, 
[src]

🔬 This is a nightly-only experimental API. (get_type_id)

this method will likely be replaced by an associated static

+

Gets the TypeId of self. Read more

+
\ No newline at end of file diff --git a/aligned/trait.Alignment.html b/aligned/trait.Alignment.html new file mode 100644 index 0000000..c7f4d1d --- /dev/null +++ b/aligned/trait.Alignment.html @@ -0,0 +1,7 @@ +aligned::Alignment - Rust

[−][src]Trait aligned::Alignment

pub unsafe trait Alignment { }

IMPLEMENTATION DETAIL

+

Implementors

  • impl Alignment for u16
    [src]
    • +
  • impl Alignment for u32
    [src]
    • +
  • impl Alignment for u64
    [src]
    • +
\ No newline at end of file diff --git a/bare_metal/CriticalSection.t.html b/bare_metal/CriticalSection.t.html new file mode 100644 index 0000000..52ba839 --- /dev/null +++ b/bare_metal/CriticalSection.t.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to struct.CriticalSection.html...

+ + + \ No newline at end of file diff --git a/bare_metal/Mutex.t.html b/bare_metal/Mutex.t.html new file mode 100644 index 0000000..4adb623 --- /dev/null +++ b/bare_metal/Mutex.t.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to struct.Mutex.html...

+ + + \ No newline at end of file diff --git a/bare_metal/Nr.t.html b/bare_metal/Nr.t.html new file mode 100644 index 0000000..4803dd9 --- /dev/null +++ b/bare_metal/Nr.t.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to trait.Nr.html...

+ + + \ No newline at end of file diff --git a/bare_metal/Peripheral.t.html b/bare_metal/Peripheral.t.html new file mode 100644 index 0000000..29db612 --- /dev/null +++ b/bare_metal/Peripheral.t.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to struct.Peripheral.html...

+ + + \ No newline at end of file diff --git a/bare_metal/all.html b/bare_metal/all.html new file mode 100644 index 0000000..dd5a736 --- /dev/null +++ b/bare_metal/all.html @@ -0,0 +1,3 @@ +List of all items in this crate

[−] + + List of all items

Structs

Traits

\ No newline at end of file diff --git a/bare_metal/index.html b/bare_metal/index.html new file mode 100644 index 0000000..7b331fa --- /dev/null +++ b/bare_metal/index.html @@ -0,0 +1,36 @@ +bare_metal - Rust

[−][src]Crate bare_metal

Abstractions common to bare metal systems

+

Structs

+ + + + + + + + + + + + +
CriticalSection +

Critical section token

+ +
Mutex +

A "mutex" based on critical sections

+ +
Peripheral +

A peripheral

+ +

Traits

+ + + + +
Nr +

Interrupt number

+ +
\ No newline at end of file diff --git a/bare_metal/sidebar-items.js b/bare_metal/sidebar-items.js new file mode 100644 index 0000000..8356b65 --- /dev/null +++ b/bare_metal/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"struct":[["CriticalSection","Critical section token"],["Mutex","A \"mutex\" based on critical sections"],["Peripheral","A peripheral"]],"trait":[["Nr","Interrupt number"]]}); \ No newline at end of file diff --git a/bare_metal/struct.CriticalSection.html b/bare_metal/struct.CriticalSection.html new file mode 100644 index 0000000..432cedf --- /dev/null +++ b/bare_metal/struct.CriticalSection.html @@ -0,0 +1,18 @@ +bare_metal::CriticalSection - Rust

[−][src]Struct bare_metal::CriticalSection

pub struct CriticalSection { /* fields omitted */ }

Critical section token

+

Indicates that you are executing code within a critical section

+

Methods

impl CriticalSection
[src]

Creates a critical section token

+

This method is meant to be used to create safe abstractions rather than +meant to be directly used in applications.

+

Auto Trait Implementations

Blanket Implementations

impl<T, U> TryFrom for T where
    T: From<U>, 
[src]

+
🔬 This is a nightly-only experimental API. (try_from)

The type returned in the event of a conversion error.

+

🔬 This is a nightly-only experimental API. (try_from)

Performs the conversion.

+

impl<T> From for T
[src]

Performs the conversion.

+

impl<T, U> TryInto for T where
    U: TryFrom<T>, 
[src]

+
🔬 This is a nightly-only experimental API. (try_from)

The type returned in the event of a conversion error.

+

🔬 This is a nightly-only experimental API. (try_from)

Performs the conversion.

+

impl<T, U> Into for T where
    U: From<T>, 
[src]

Performs the conversion.

+

impl<T> Borrow for T where
    T: ?Sized, 
[src]

Immutably borrows from an owned value. Read more

+

impl<T> BorrowMut for T where
    T: ?Sized, 
[src]

Mutably borrows from an owned value. Read more

+

impl<T> Any for T where
    T: 'static + ?Sized, 
[src]

🔬 This is a nightly-only experimental API. (get_type_id)

this method will likely be replaced by an associated static

+

Gets the TypeId of self. Read more

+
\ No newline at end of file diff --git a/bare_metal/struct.Mutex.html b/bare_metal/struct.Mutex.html new file mode 100644 index 0000000..92be618 --- /dev/null +++ b/bare_metal/struct.Mutex.html @@ -0,0 +1,16 @@ +bare_metal::Mutex - Rust

[−][src]Struct bare_metal::Mutex

pub struct Mutex<T> { /* fields omitted */ }

A "mutex" based on critical sections

+

Methods

impl<T> Mutex<T>
[src]

Creates a new mutex

+

impl<T> Mutex<T>
[src]

Borrows the data for the duration of the critical section

+

Trait Implementations

impl<T> Sync for Mutex<T> where
    T: Send, 
[src]

Auto Trait Implementations

impl<T> Send for Mutex<T> where
    T: Send, 

Blanket Implementations

impl<T, U> TryFrom for T where
    T: From<U>, 
[src]

+
🔬 This is a nightly-only experimental API. (try_from)

The type returned in the event of a conversion error.

+

🔬 This is a nightly-only experimental API. (try_from)

Performs the conversion.

+

impl<T> From for T
[src]

Performs the conversion.

+

impl<T, U> TryInto for T where
    U: TryFrom<T>, 
[src]

+
🔬 This is a nightly-only experimental API. (try_from)

The type returned in the event of a conversion error.

+

🔬 This is a nightly-only experimental API. (try_from)

Performs the conversion.

+

impl<T, U> Into for T where
    U: From<T>, 
[src]

Performs the conversion.

+

impl<T> Borrow for T where
    T: ?Sized, 
[src]

Immutably borrows from an owned value. Read more

+

impl<T> BorrowMut for T where
    T: ?Sized, 
[src]

Mutably borrows from an owned value. Read more

+

impl<T> Any for T where
    T: 'static + ?Sized, 
[src]

🔬 This is a nightly-only experimental API. (get_type_id)

this method will likely be replaced by an associated static

+

Gets the TypeId of self. Read more

+
\ No newline at end of file diff --git a/bare_metal/struct.Peripheral.html b/bare_metal/struct.Peripheral.html new file mode 100644 index 0000000..f9da082 --- /dev/null +++ b/bare_metal/struct.Peripheral.html @@ -0,0 +1,19 @@ +bare_metal::Peripheral - Rust

[−][src]Struct bare_metal::Peripheral

pub struct Peripheral<T> where
    T: 'static,  { /* fields omitted */ }

A peripheral

+

Methods

impl<T> Peripheral<T>
[src]

Creates a new peripheral

+

address is the base address of the register block

+

Borrows the peripheral for the duration of a critical section

+

Returns a pointer to the register block

+

Trait Implementations

impl<T: Debug> Debug for Peripheral<T> where
    T: 'static, 
[src]

Formats the value using the given formatter. Read more

+

Auto Trait Implementations

impl<T> !Send for Peripheral<T>

impl<T> !Sync for Peripheral<T>

Blanket Implementations

impl<T, U> TryFrom for T where
    T: From<U>, 
[src]

+
🔬 This is a nightly-only experimental API. (try_from)

The type returned in the event of a conversion error.

+

🔬 This is a nightly-only experimental API. (try_from)

Performs the conversion.

+

impl<T> From for T
[src]

Performs the conversion.

+

impl<T, U> TryInto for T where
    U: TryFrom<T>, 
[src]

+
🔬 This is a nightly-only experimental API. (try_from)

The type returned in the event of a conversion error.

+

🔬 This is a nightly-only experimental API. (try_from)

Performs the conversion.

+

impl<T, U> Into for T where
    U: From<T>, 
[src]

Performs the conversion.

+

impl<T> Borrow for T where
    T: ?Sized, 
[src]

Immutably borrows from an owned value. Read more

+

impl<T> BorrowMut for T where
    T: ?Sized, 
[src]

Mutably borrows from an owned value. Read more

+

impl<T> Any for T where
    T: 'static + ?Sized, 
[src]

🔬 This is a nightly-only experimental API. (get_type_id)

this method will likely be replaced by an associated static

+

Gets the TypeId of self. Read more

+
\ No newline at end of file diff --git a/bare_metal/trait.Nr.html b/bare_metal/trait.Nr.html new file mode 100644 index 0000000..74b435d --- /dev/null +++ b/bare_metal/trait.Nr.html @@ -0,0 +1,12 @@ +bare_metal::Nr - Rust

[−][src]Trait bare_metal::Nr

pub unsafe trait Nr {
+    fn nr(&self) -> u8;
+}

Interrupt number

+
+

+ Required Methods +

+
+

Returns the number associated with an interrupt

+

Implementors

    \ No newline at end of file diff --git a/brush.svg b/brush.svg new file mode 100644 index 0000000..072264a --- /dev/null +++ b/brush.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/cortex_m/all.html b/cortex_m/all.html new file mode 100644 index 0000000..67e9d1b --- /dev/null +++ b/cortex_m/all.html @@ -0,0 +1,3 @@ +List of all items in this crate

    [−] + + List of all items

    Structs

    Enums

    Traits

    Macros

    Functions

    \ No newline at end of file diff --git a/cortex_m/asm/bkpt.v.html b/cortex_m/asm/bkpt.v.html new file mode 100644 index 0000000..f3200ae --- /dev/null +++ b/cortex_m/asm/bkpt.v.html @@ -0,0 +1,10 @@ + + + + + + +

    Redirecting to fn.bkpt.html...

    + + + \ No newline at end of file diff --git a/cortex_m/asm/delay.v.html b/cortex_m/asm/delay.v.html new file mode 100644 index 0000000..e796f22 --- /dev/null +++ b/cortex_m/asm/delay.v.html @@ -0,0 +1,10 @@ + + + + + + +

    Redirecting to fn.delay.html...

    + + + \ No newline at end of file diff --git a/cortex_m/asm/dmb.v.html b/cortex_m/asm/dmb.v.html new file mode 100644 index 0000000..bc586d4 --- /dev/null +++ b/cortex_m/asm/dmb.v.html @@ -0,0 +1,10 @@ + + + + + + +

    Redirecting to fn.dmb.html...

    + + + \ No newline at end of file diff --git a/cortex_m/asm/dsb.v.html b/cortex_m/asm/dsb.v.html new file mode 100644 index 0000000..bebf028 --- /dev/null +++ b/cortex_m/asm/dsb.v.html @@ -0,0 +1,10 @@ + + + + + + +

    Redirecting to fn.dsb.html...

    + + + \ No newline at end of file diff --git a/cortex_m/asm/fn.bkpt.html b/cortex_m/asm/fn.bkpt.html new file mode 100644 index 0000000..b0b9c78 --- /dev/null +++ b/cortex_m/asm/fn.bkpt.html @@ -0,0 +1,4 @@ +cortex_m::asm::bkpt - Rust

    [−][src]Function cortex_m::asm::bkpt

    pub fn bkpt()

    Puts the processor in Debug state. Debuggers can pick this up as a "breakpoint".

    +

    NOTE calling bkpt when the processor is not connected to a debugger will cause an +exception.

    +
    \ No newline at end of file diff --git a/cortex_m/asm/fn.delay.html b/cortex_m/asm/fn.delay.html new file mode 100644 index 0000000..00e3395 --- /dev/null +++ b/cortex_m/asm/fn.delay.html @@ -0,0 +1,5 @@ +cortex_m::asm::delay - Rust

    [−][src]Function cortex_m::asm::delay

    pub fn delay(_n: u32)

    Blocks the program for at least n instruction cycles

    +

    This is implemented in assembly so its execution time is the same regardless of the optimization +level.

    +

    NOTE that the delay can take much longer if interrupts are serviced during its execution.

    +
    \ No newline at end of file diff --git a/cortex_m/asm/fn.dmb.html b/cortex_m/asm/fn.dmb.html new file mode 100644 index 0000000..bedf27a --- /dev/null +++ b/cortex_m/asm/fn.dmb.html @@ -0,0 +1,5 @@ +cortex_m::asm::dmb - Rust

    [−][src]Function cortex_m::asm::dmb

    pub fn dmb()

    Data Memory Barrier

    +

    Ensures that all explicit memory accesses that appear in program order before the DMB +instruction are observed before any explicit memory accesses that appear in program order +after the DMB instruction.

    +
    \ No newline at end of file diff --git a/cortex_m/asm/fn.dsb.html b/cortex_m/asm/fn.dsb.html new file mode 100644 index 0000000..bf8583c --- /dev/null +++ b/cortex_m/asm/fn.dsb.html @@ -0,0 +1,8 @@ +cortex_m::asm::dsb - Rust

    [−][src]Function cortex_m::asm::dsb

    pub fn dsb()

    Data Synchronization Barrier

    +

    Acts as a special kind of memory barrier. No instruction in program order after this instruction +can execute until this instruction completes. This instruction completes only when both:

    +
      +
    • any explicit memory access made before this instruction is complete
      • +
    • all cache and branch predictor maintenance operations before this instruction complete
      • +
    +
    \ No newline at end of file diff --git a/cortex_m/asm/fn.isb.html b/cortex_m/asm/fn.isb.html new file mode 100644 index 0000000..8f4e1c6 --- /dev/null +++ b/cortex_m/asm/fn.isb.html @@ -0,0 +1,4 @@ +cortex_m::asm::isb - Rust

    [−][src]Function cortex_m::asm::isb

    pub fn isb()

    Instruction Synchronization Barrier

    +

    Flushes the pipeline in the processor, so that all instructions following the ISB are fetched +from cache or memory, after the instruction has been completed.

    +
    \ No newline at end of file diff --git a/cortex_m/asm/fn.nop.html b/cortex_m/asm/fn.nop.html new file mode 100644 index 0000000..2396554 --- /dev/null +++ b/cortex_m/asm/fn.nop.html @@ -0,0 +1,2 @@ +cortex_m::asm::nop - Rust

    [−][src]Function cortex_m::asm::nop

    pub fn nop()

    A no-operation. Useful to prevent delay loops from being optimized away.

    +
    \ No newline at end of file diff --git a/cortex_m/asm/fn.sev.html b/cortex_m/asm/fn.sev.html new file mode 100644 index 0000000..25f57f5 --- /dev/null +++ b/cortex_m/asm/fn.sev.html @@ -0,0 +1,2 @@ +cortex_m::asm::sev - Rust

    [−][src]Function cortex_m::asm::sev

    pub fn sev()

    Send Event

    +
    \ No newline at end of file diff --git a/cortex_m/asm/fn.wfe.html b/cortex_m/asm/fn.wfe.html new file mode 100644 index 0000000..fb8b085 --- /dev/null +++ b/cortex_m/asm/fn.wfe.html @@ -0,0 +1,2 @@ +cortex_m::asm::wfe - Rust

    [−][src]Function cortex_m::asm::wfe

    pub fn wfe()

    Wait For Event

    +
    \ No newline at end of file diff --git a/cortex_m/asm/fn.wfi.html b/cortex_m/asm/fn.wfi.html new file mode 100644 index 0000000..c7f0fdc --- /dev/null +++ b/cortex_m/asm/fn.wfi.html @@ -0,0 +1,2 @@ +cortex_m::asm::wfi - Rust

    [−][src]Function cortex_m::asm::wfi

    pub fn wfi()

    Wait For Interrupt

    +
    \ No newline at end of file diff --git a/cortex_m/asm/index.html b/cortex_m/asm/index.html new file mode 100644 index 0000000..7ea4bec --- /dev/null +++ b/cortex_m/asm/index.html @@ -0,0 +1,75 @@ +cortex_m::asm - Rust

    [−][src]Module cortex_m::asm

    Miscellaneous assembly instructions

    +

    Functions

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    bkpt +

    Puts the processor in Debug state. Debuggers can pick this up as a "breakpoint".

    + +
    delay +

    Blocks the program for at least n instruction cycles

    + +
    dmb +

    Data Memory Barrier

    + +
    dsb +

    Data Synchronization Barrier

    + +
    isb +

    Instruction Synchronization Barrier

    + +
    nop +

    A no-operation. Useful to prevent delay loops from being optimized away.

    + +
    sev +

    Send Event

    + +
    wfe +

    Wait For Event

    + +
    wfi +

    Wait For Interrupt

    + +
    \ No newline at end of file diff --git a/cortex_m/asm/isb.v.html b/cortex_m/asm/isb.v.html new file mode 100644 index 0000000..5b01b20 --- /dev/null +++ b/cortex_m/asm/isb.v.html @@ -0,0 +1,10 @@ + + + + + + +

    Redirecting to fn.isb.html...

    + + + \ No newline at end of file diff --git a/cortex_m/asm/nop.v.html b/cortex_m/asm/nop.v.html new file mode 100644 index 0000000..acc7181 --- /dev/null +++ b/cortex_m/asm/nop.v.html @@ -0,0 +1,10 @@ + + + + + + +

    Redirecting to fn.nop.html...

    + + + \ No newline at end of file diff --git a/cortex_m/asm/sev.v.html b/cortex_m/asm/sev.v.html new file mode 100644 index 0000000..359ffa5 --- /dev/null +++ b/cortex_m/asm/sev.v.html @@ -0,0 +1,10 @@ + + + + + + +

    Redirecting to fn.sev.html...

    + + + \ No newline at end of file diff --git a/cortex_m/asm/sidebar-items.js b/cortex_m/asm/sidebar-items.js new file mode 100644 index 0000000..9452003 --- /dev/null +++ b/cortex_m/asm/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"fn":[["bkpt","Puts the processor in Debug state. Debuggers can pick this up as a \"breakpoint\"."],["delay","Blocks the program for at least `n` instruction cycles"],["dmb","Data Memory Barrier"],["dsb","Data Synchronization Barrier"],["isb","Instruction Synchronization Barrier"],["nop","A no-operation. Useful to prevent delay loops from being optimized away."],["sev","Send Event"],["wfe","Wait For Event"],["wfi","Wait For Interrupt"]]}); \ No newline at end of file diff --git a/cortex_m/asm/wfe.v.html b/cortex_m/asm/wfe.v.html new file mode 100644 index 0000000..9dd6564 --- /dev/null +++ b/cortex_m/asm/wfe.v.html @@ -0,0 +1,10 @@ + + + + + + +

    Redirecting to fn.wfe.html...

    + + + \ No newline at end of file diff --git a/cortex_m/asm/wfi.v.html b/cortex_m/asm/wfi.v.html new file mode 100644 index 0000000..8b0ae65 --- /dev/null +++ b/cortex_m/asm/wfi.v.html @@ -0,0 +1,10 @@ + + + + + + +

    Redirecting to fn.wfi.html...

    + + + \ No newline at end of file diff --git a/cortex_m/index.html b/cortex_m/index.html new file mode 100644 index 0000000..16c5b52 --- /dev/null +++ b/cortex_m/index.html @@ -0,0 +1,95 @@ +cortex_m - Rust

    [−][src]Crate cortex_m

    Low level access to Cortex-M processors

    +

    This crate provides:

    +
      +
    • Access to core peripherals like NVIC, SCB and SysTick.
      • +
    • Access to core registers like CONTROL, MSP and PSR.
      • +
    • Interrupt manipulation mechanisms
      • +
    • Safe wrappers around Cortex-M specific instructions like bkpt
      • +
    +

    Optional features

    inline-asm

    +

    When this feature is enabled the implementation of all the functions inside the asm and +register modules use inline assembly (asm!) instead of external assembly (FFI into separate +assembly files pre-compiled using arm-none-eabi-gcc). The advantages of enabling inline-asm +are:

    +
      +
    • +

      Reduced overhead. FFI eliminates the possibility of inlining so all operations include a +function call overhead when inline-asm is not enabled.

      +
      • +
    • +

      Some of the register API only becomes available only when inline-asm is enabled. Check the +API docs for details.

      +
      • +
    +

    The disadvantage is that inline-asm requires a nightly toolchain.

    +

    const-fn

    +

    Enabling this feature turns the Mutex.new constructor into a const fn.

    +

    This feature requires a nightly toolchain.

    +

    Re-exports

    +
    pub use peripheral::Peripherals;

    Modules

    + + + + + + + + + + + + + + + + + + + + +
    asm +

    Miscellaneous assembly instructions

    + +
    interrupt +

    Interrupts

    + +
    itm +

    Instrumentation Trace Macrocell

    + +
    peripheral +

    Core peripherals

    + +
    register +

    Processor core registers

    + +

    Macros

    + + + + + + + + + + + + +
    iprint +

    Macro for sending a formatted string through an ITM channel

    + +
    iprintln +

    Macro for sending a formatted string through an ITM channel, with a newline.

    + +
    singleton +

    Macro to create a mutable reference to a statically allocated value

    + +
    \ No newline at end of file diff --git a/cortex_m/interrupt/CriticalSection.t.html b/cortex_m/interrupt/CriticalSection.t.html new file mode 100644 index 0000000..52ba839 --- /dev/null +++ b/cortex_m/interrupt/CriticalSection.t.html @@ -0,0 +1,10 @@ + + + + + + +

    Redirecting to struct.CriticalSection.html...

    + + + \ No newline at end of file diff --git a/cortex_m/interrupt/Mutex.t.html b/cortex_m/interrupt/Mutex.t.html new file mode 100644 index 0000000..4adb623 --- /dev/null +++ b/cortex_m/interrupt/Mutex.t.html @@ -0,0 +1,10 @@ + + + + + + +

    Redirecting to struct.Mutex.html...

    + + + \ No newline at end of file diff --git a/cortex_m/interrupt/Nr.t.html b/cortex_m/interrupt/Nr.t.html new file mode 100644 index 0000000..4803dd9 --- /dev/null +++ b/cortex_m/interrupt/Nr.t.html @@ -0,0 +1,10 @@ + + + + + + +

    Redirecting to trait.Nr.html...

    + + + \ No newline at end of file diff --git a/cortex_m/interrupt/disable.v.html b/cortex_m/interrupt/disable.v.html new file mode 100644 index 0000000..72fe0d0 --- /dev/null +++ b/cortex_m/interrupt/disable.v.html @@ -0,0 +1,10 @@ + + + + + + +

    Redirecting to fn.disable.html...

    + + + \ No newline at end of file diff --git a/cortex_m/interrupt/enable.v.html b/cortex_m/interrupt/enable.v.html new file mode 100644 index 0000000..9a951bf --- /dev/null +++ b/cortex_m/interrupt/enable.v.html @@ -0,0 +1,10 @@ + + + + + + +

    Redirecting to fn.enable.html...

    + + + \ No newline at end of file diff --git a/cortex_m/interrupt/fn.disable.html b/cortex_m/interrupt/fn.disable.html new file mode 100644 index 0000000..86693eb --- /dev/null +++ b/cortex_m/interrupt/fn.disable.html @@ -0,0 +1,2 @@ +cortex_m::interrupt::disable - Rust

    [−][src]Function cortex_m::interrupt::disable

    pub fn disable()

    Disables all interrupts

    +
    \ No newline at end of file diff --git a/cortex_m/interrupt/fn.enable.html b/cortex_m/interrupt/fn.enable.html new file mode 100644 index 0000000..f57876d --- /dev/null +++ b/cortex_m/interrupt/fn.enable.html @@ -0,0 +1,6 @@ +cortex_m::interrupt::enable - Rust

    [−][src]Function cortex_m::interrupt::enable

    pub unsafe fn enable()

    Enables all the interrupts

    +

    Safety

    +
      +
    • Do not call this function inside an interrupt::free critical section
      • +
    +
    \ No newline at end of file diff --git a/cortex_m/interrupt/fn.free.html b/cortex_m/interrupt/fn.free.html new file mode 100644 index 0000000..0ede4c9 --- /dev/null +++ b/cortex_m/interrupt/fn.free.html @@ -0,0 +1,3 @@ +cortex_m::interrupt::free - Rust

    [−][src]Function cortex_m::interrupt::free

    pub fn free<F, R>(f: F) -> R where
        F: FnOnce(&CriticalSection) -> R, 

    Execute closure f in an interrupt-free context.

    +

    This as also known as a "critical section".

    +
    \ No newline at end of file diff --git a/cortex_m/interrupt/free.v.html b/cortex_m/interrupt/free.v.html new file mode 100644 index 0000000..9732aaa --- /dev/null +++ b/cortex_m/interrupt/free.v.html @@ -0,0 +1,10 @@ + + + + + + +

    Redirecting to fn.free.html...

    + + + \ No newline at end of file diff --git a/cortex_m/interrupt/index.html b/cortex_m/interrupt/index.html new file mode 100644 index 0000000..ae3edf4 --- /dev/null +++ b/cortex_m/interrupt/index.html @@ -0,0 +1,53 @@ +cortex_m::interrupt - Rust

    [−][src]Module cortex_m::interrupt

    Interrupts

    +

    Structs

    + + + + + + + + +
    CriticalSection +

    Critical section token

    + +
    Mutex +

    A "mutex" based on critical sections

    + +

    Traits

    + + + + +
    Nr +

    Interrupt number

    + +

    Functions

    + + + + + + + + + + + + +
    disable +

    Disables all interrupts

    + +
    enable⚠ +

    Enables all the interrupts

    + +
    free +

    Execute closure f in an interrupt-free context.

    + +
    \ No newline at end of file diff --git a/cortex_m/interrupt/sidebar-items.js b/cortex_m/interrupt/sidebar-items.js new file mode 100644 index 0000000..201fd19 --- /dev/null +++ b/cortex_m/interrupt/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"fn":[["disable","Disables all interrupts"],["enable","Enables all the interrupts"],["free","Execute closure `f` in an interrupt-free context."]],"struct":[["CriticalSection","Critical section token"],["Mutex","A \"mutex\" based on critical sections"]],"trait":[["Nr","Interrupt number"]]}); \ No newline at end of file diff --git a/cortex_m/interrupt/struct.CriticalSection.html b/cortex_m/interrupt/struct.CriticalSection.html new file mode 100644 index 0000000..911a890 --- /dev/null +++ b/cortex_m/interrupt/struct.CriticalSection.html @@ -0,0 +1,18 @@ +cortex_m::interrupt::CriticalSection - Rust

    [−][src]Struct cortex_m::interrupt::CriticalSection

    pub struct CriticalSection { /* fields omitted */ }

    Critical section token

    +

    Indicates that you are executing code within a critical section

    +

    Methods

    impl CriticalSection
    [src]

    Creates a critical section token

    +

    This method is meant to be used to create safe abstractions rather than +meant to be directly used in applications.

    +

    Auto Trait Implementations

    Blanket Implementations

    impl<T, U> TryFrom for T where
        T: From<U>, 
    [src]

    +
    🔬 This is a nightly-only experimental API. (try_from)

    The type returned in the event of a conversion error.

    +

    🔬 This is a nightly-only experimental API. (try_from)

    Performs the conversion.

    +

    impl<T> From for T
    [src]

    Performs the conversion.

    +

    impl<T, U> TryInto for T where
        U: TryFrom<T>, 
    [src]

    +
    🔬 This is a nightly-only experimental API. (try_from)

    The type returned in the event of a conversion error.

    +

    🔬 This is a nightly-only experimental API. (try_from)

    Performs the conversion.

    +

    impl<T, U> Into for T where
        U: From<T>, 
    [src]

    Performs the conversion.

    +

    impl<T> Borrow for T where
        T: ?Sized, 
    [src]

    Immutably borrows from an owned value. Read more

    +

    impl<T> BorrowMut for T where
        T: ?Sized, 
    [src]

    Mutably borrows from an owned value. Read more

    +

    impl<T> Any for T where
        T: 'static + ?Sized, 
    [src]

    🔬 This is a nightly-only experimental API. (get_type_id)

    this method will likely be replaced by an associated static

    +

    Gets the TypeId of self. Read more

    +
    \ No newline at end of file diff --git a/cortex_m/interrupt/struct.Mutex.html b/cortex_m/interrupt/struct.Mutex.html new file mode 100644 index 0000000..bb815e6 --- /dev/null +++ b/cortex_m/interrupt/struct.Mutex.html @@ -0,0 +1,16 @@ +cortex_m::interrupt::Mutex - Rust

    [−][src]Struct cortex_m::interrupt::Mutex

    pub struct Mutex<T> { /* fields omitted */ }

    A "mutex" based on critical sections

    +

    Methods

    impl<T> Mutex<T>
    [src]

    Creates a new mutex

    +

    impl<T> Mutex<T>
    [src]

    Borrows the data for the duration of the critical section

    +

    Trait Implementations

    impl<T> Sync for Mutex<T> where
        T: Send, 
    [src]

    Auto Trait Implementations

    impl<T> Send for Mutex<T> where
        T: Send, 

    Blanket Implementations

    impl<T, U> TryFrom for T where
        T: From<U>, 
    [src]

    +
    🔬 This is a nightly-only experimental API. (try_from)

    The type returned in the event of a conversion error.

    +

    🔬 This is a nightly-only experimental API. (try_from)

    Performs the conversion.

    +

    impl<T> From for T
    [src]

    Performs the conversion.

    +

    impl<T, U> TryInto for T where
        U: TryFrom<T>, 
    [src]

    +
    🔬 This is a nightly-only experimental API. (try_from)

    The type returned in the event of a conversion error.

    +

    🔬 This is a nightly-only experimental API. (try_from)

    Performs the conversion.

    +

    impl<T, U> Into for T where
        U: From<T>, 
    [src]

    Performs the conversion.

    +

    impl<T> Borrow for T where
        T: ?Sized, 
    [src]

    Immutably borrows from an owned value. Read more

    +

    impl<T> BorrowMut for T where
        T: ?Sized, 
    [src]

    Mutably borrows from an owned value. Read more

    +

    impl<T> Any for T where
        T: 'static + ?Sized, 
    [src]

    🔬 This is a nightly-only experimental API. (get_type_id)

    this method will likely be replaced by an associated static

    +

    Gets the TypeId of self. Read more

    +
    \ No newline at end of file diff --git a/cortex_m/interrupt/trait.Nr.html b/cortex_m/interrupt/trait.Nr.html new file mode 100644 index 0000000..16450a5 --- /dev/null +++ b/cortex_m/interrupt/trait.Nr.html @@ -0,0 +1,12 @@ +cortex_m::interrupt::Nr - Rust

    [−][src]Trait cortex_m::interrupt::Nr

    pub unsafe trait Nr {
+    fn nr(&self) -> u8;
+}

    Interrupt number

    +
    +

    + Required Methods +

    +
    +

    Returns the number associated with an interrupt

    +

    Implementors

      \ No newline at end of file diff --git a/cortex_m/iprint.m.html b/cortex_m/iprint.m.html new file mode 100644 index 0000000..fae18f1 --- /dev/null +++ b/cortex_m/iprint.m.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.iprint.html...

      + + + \ No newline at end of file diff --git a/cortex_m/iprintln.m.html b/cortex_m/iprintln.m.html new file mode 100644 index 0000000..0889d8b --- /dev/null +++ b/cortex_m/iprintln.m.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.iprintln.html...

      + + + \ No newline at end of file diff --git a/cortex_m/itm/fn.write_aligned.html b/cortex_m/itm/fn.write_aligned.html new file mode 100644 index 0000000..0d80a44 --- /dev/null +++ b/cortex_m/itm/fn.write_aligned.html @@ -0,0 +1,12 @@ +cortex_m::itm::write_aligned - Rust

      [−][src]Function cortex_m::itm::write_aligned

      pub fn write_aligned(port: &mut Stim, buffer: &Aligned<u32, [u8]>)

      Writes a 4-byte aligned buffer to the ITM port

      +

      Examples

      +
      ⓘThis example is not tested
      +let mut buffer: Aligned<u32, _> = Aligned([0; 14]);
+
+buffer.copy_from_slice(b"Hello, world!\n");
+
+itm::write_aligned(&itm.stim[0], &buffer);
+
+// Or equivalently
+itm::write_aligned(&itm.stim[0], &Aligned(*b"Hello, world!\n"));
      +
      \ No newline at end of file diff --git a/cortex_m/itm/fn.write_all.html b/cortex_m/itm/fn.write_all.html new file mode 100644 index 0000000..eb9d387 --- /dev/null +++ b/cortex_m/itm/fn.write_all.html @@ -0,0 +1,2 @@ +cortex_m::itm::write_all - Rust

      [−][src]Function cortex_m::itm::write_all

      pub fn write_all(port: &mut Stim, buffer: &[u8])

      Writes a buffer to the ITM port

      +
      \ No newline at end of file diff --git a/cortex_m/itm/fn.write_fmt.html b/cortex_m/itm/fn.write_fmt.html new file mode 100644 index 0000000..46591ff --- /dev/null +++ b/cortex_m/itm/fn.write_fmt.html @@ -0,0 +1,2 @@ +cortex_m::itm::write_fmt - Rust

      [−][src]Function cortex_m::itm::write_fmt

      pub fn write_fmt(port: &mut Stim, args: Arguments)

      Writes fmt::Arguments to the ITM port

      +
      \ No newline at end of file diff --git a/cortex_m/itm/fn.write_str.html b/cortex_m/itm/fn.write_str.html new file mode 100644 index 0000000..318e352 --- /dev/null +++ b/cortex_m/itm/fn.write_str.html @@ -0,0 +1,2 @@ +cortex_m::itm::write_str - Rust

      [−][src]Function cortex_m::itm::write_str

      pub fn write_str(port: &mut Stim, string: &str)

      Writes a string to the ITM port

      +
      \ No newline at end of file diff --git a/cortex_m/itm/index.html b/cortex_m/itm/index.html new file mode 100644 index 0000000..cfd4d26 --- /dev/null +++ b/cortex_m/itm/index.html @@ -0,0 +1,36 @@ +cortex_m::itm - Rust

      [−][src]Module cortex_m::itm

      Instrumentation Trace Macrocell

      +

      NOTE This module is only available on ARMv7-M and newer

      +

      Functions

      + + + + + + + + + + + + + + + + +
      write_aligned +

      Writes a 4-byte aligned buffer to the ITM port

      + +
      write_all +

      Writes a buffer to the ITM port

      + +
      write_fmt +

      Writes fmt::Arguments to the ITM port

      + +
      write_str +

      Writes a string to the ITM port

      + +
      \ No newline at end of file diff --git a/cortex_m/itm/sidebar-items.js b/cortex_m/itm/sidebar-items.js new file mode 100644 index 0000000..9341bef --- /dev/null +++ b/cortex_m/itm/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"fn":[["write_aligned","Writes a 4-byte aligned `buffer` to the ITM `port`"],["write_all","Writes a `buffer` to the ITM `port`"],["write_fmt","Writes `fmt::Arguments` to the ITM `port`"],["write_str","Writes a string to the ITM `port`"]]}); \ No newline at end of file diff --git a/cortex_m/itm/write_aligned.v.html b/cortex_m/itm/write_aligned.v.html new file mode 100644 index 0000000..97348e3 --- /dev/null +++ b/cortex_m/itm/write_aligned.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.write_aligned.html...

      + + + \ No newline at end of file diff --git a/cortex_m/itm/write_all.v.html b/cortex_m/itm/write_all.v.html new file mode 100644 index 0000000..e109ebd --- /dev/null +++ b/cortex_m/itm/write_all.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.write_all.html...

      + + + \ No newline at end of file diff --git a/cortex_m/itm/write_fmt.v.html b/cortex_m/itm/write_fmt.v.html new file mode 100644 index 0000000..56ceafe --- /dev/null +++ b/cortex_m/itm/write_fmt.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.write_fmt.html...

      + + + \ No newline at end of file diff --git a/cortex_m/itm/write_str.v.html b/cortex_m/itm/write_str.v.html new file mode 100644 index 0000000..ee39efd --- /dev/null +++ b/cortex_m/itm/write_str.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.write_str.html...

      + + + \ No newline at end of file diff --git a/cortex_m/macro.iprint!.html b/cortex_m/macro.iprint!.html new file mode 100644 index 0000000..fae18f1 --- /dev/null +++ b/cortex_m/macro.iprint!.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.iprint.html...

      + + + \ No newline at end of file diff --git a/cortex_m/macro.iprint.html b/cortex_m/macro.iprint.html new file mode 100644 index 0000000..6aac7f5 --- /dev/null +++ b/cortex_m/macro.iprint.html @@ -0,0 +1,7 @@ +cortex_m::iprint - Rust

      [−][src]Macro cortex_m::iprint

      +macro_rules! iprint {
+    ($channel:expr, $s:expr) => { ... };
+    ($channel:expr, $($arg:tt)*) => { ... };
+}
      +

      Macro for sending a formatted string through an ITM channel

      +
      \ No newline at end of file diff --git a/cortex_m/macro.iprintln!.html b/cortex_m/macro.iprintln!.html new file mode 100644 index 0000000..0889d8b --- /dev/null +++ b/cortex_m/macro.iprintln!.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.iprintln.html...

      + + + \ No newline at end of file diff --git a/cortex_m/macro.iprintln.html b/cortex_m/macro.iprintln.html new file mode 100644 index 0000000..c672b9d --- /dev/null +++ b/cortex_m/macro.iprintln.html @@ -0,0 +1,8 @@ +cortex_m::iprintln - Rust

      [−][src]Macro cortex_m::iprintln

      +macro_rules! iprintln {
+    ($channel:expr) => { ... };
+    ($channel:expr, $fmt:expr) => { ... };
+    ($channel:expr, $fmt:expr, $($arg:tt)*) => { ... };
+}
      +

      Macro for sending a formatted string through an ITM channel, with a newline.

      +
      \ No newline at end of file diff --git a/cortex_m/macro.singleton!.html b/cortex_m/macro.singleton!.html new file mode 100644 index 0000000..67106d0 --- /dev/null +++ b/cortex_m/macro.singleton!.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.singleton.html...

      + + + \ No newline at end of file diff --git a/cortex_m/macro.singleton.html b/cortex_m/macro.singleton.html new file mode 100644 index 0000000..6ee28ae --- /dev/null +++ b/cortex_m/macro.singleton.html @@ -0,0 +1,27 @@ +cortex_m::singleton - Rust

      [−][src]Macro cortex_m::singleton

      +macro_rules! singleton {
+    (: $ty:ty = $expr:expr) => { ... };
+}
      +

      Macro to create a mutable reference to a statically allocated value

      +

      This macro returns a value with type Option<&'static mut $ty>. Some($expr) will be returned +the first time the macro is executed; further calls will return None. To avoid unwrapping a +None variant the caller must ensure that the macro is called from a function that's executed +at most once in the whole lifetime of the program.

      +

      Example

      +
      +#[macro_use(singleton)]
+extern crate cortex_m;
+
+fn main() {
+    // OK if `main` is executed only once
+    let x: &'static mut bool = singleton!(: bool = false).unwrap();
+
+    let y = alias();
+    // BAD this second call to `alias` will definitively `panic!`
+    let y_alias = alias();
+}
+
+fn alias() -> &'static mut bool {
+    singleton!(: bool = false).unwrap()
+}
      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/CBP.t.html b/cortex_m/peripheral/CBP.t.html new file mode 100644 index 0000000..1934282 --- /dev/null +++ b/cortex_m/peripheral/CBP.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.CBP.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/CPUID.t.html b/cortex_m/peripheral/CPUID.t.html new file mode 100644 index 0000000..ae3bb8c --- /dev/null +++ b/cortex_m/peripheral/CPUID.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.CPUID.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/DCB.t.html b/cortex_m/peripheral/DCB.t.html new file mode 100644 index 0000000..1a50bd7 --- /dev/null +++ b/cortex_m/peripheral/DCB.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.DCB.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/DWT.t.html b/cortex_m/peripheral/DWT.t.html new file mode 100644 index 0000000..3cbb29d --- /dev/null +++ b/cortex_m/peripheral/DWT.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.DWT.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/FPB.t.html b/cortex_m/peripheral/FPB.t.html new file mode 100644 index 0000000..c3d9c82 --- /dev/null +++ b/cortex_m/peripheral/FPB.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.FPB.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/FPU.t.html b/cortex_m/peripheral/FPU.t.html new file mode 100644 index 0000000..264922f --- /dev/null +++ b/cortex_m/peripheral/FPU.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.FPU.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/ITM.t.html b/cortex_m/peripheral/ITM.t.html new file mode 100644 index 0000000..6e39527 --- /dev/null +++ b/cortex_m/peripheral/ITM.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.ITM.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/MPU.t.html b/cortex_m/peripheral/MPU.t.html new file mode 100644 index 0000000..44c6781 --- /dev/null +++ b/cortex_m/peripheral/MPU.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.MPU.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/NVIC.t.html b/cortex_m/peripheral/NVIC.t.html new file mode 100644 index 0000000..1b17a08 --- /dev/null +++ b/cortex_m/peripheral/NVIC.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.NVIC.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/Peripherals.t.html b/cortex_m/peripheral/Peripherals.t.html new file mode 100644 index 0000000..0b3924f --- /dev/null +++ b/cortex_m/peripheral/Peripherals.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.Peripherals.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/SCB.t.html b/cortex_m/peripheral/SCB.t.html new file mode 100644 index 0000000..22dad8d --- /dev/null +++ b/cortex_m/peripheral/SCB.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.SCB.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/SYST.t.html b/cortex_m/peripheral/SYST.t.html new file mode 100644 index 0000000..0f561d9 --- /dev/null +++ b/cortex_m/peripheral/SYST.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.SYST.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/TPIU.t.html b/cortex_m/peripheral/TPIU.t.html new file mode 100644 index 0000000..30622d5 --- /dev/null +++ b/cortex_m/peripheral/TPIU.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.TPIU.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/cbp/RegisterBlock.t.html b/cortex_m/peripheral/cbp/RegisterBlock.t.html new file mode 100644 index 0000000..95870c5 --- /dev/null +++ b/cortex_m/peripheral/cbp/RegisterBlock.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.RegisterBlock.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/cbp/index.html b/cortex_m/peripheral/cbp/index.html new file mode 100644 index 0000000..4c7a2c5 --- /dev/null +++ b/cortex_m/peripheral/cbp/index.html @@ -0,0 +1,12 @@ +cortex_m::peripheral::cbp - Rust

      [−][src]Module cortex_m::peripheral::cbp

      Cache and branch predictor maintenance operations

      +

      NOTE Available only on ARMv7-M (thumbv7*m-none-eabi*)

      +

      Structs

      + + + + +
      RegisterBlock +

      Register block

      + +
      \ No newline at end of file diff --git a/cortex_m/peripheral/cbp/sidebar-items.js b/cortex_m/peripheral/cbp/sidebar-items.js new file mode 100644 index 0000000..9e664d0 --- /dev/null +++ b/cortex_m/peripheral/cbp/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"struct":[["RegisterBlock","Register block"]]}); \ No newline at end of file diff --git a/cortex_m/peripheral/cbp/struct.RegisterBlock.html b/cortex_m/peripheral/cbp/struct.RegisterBlock.html new file mode 100644 index 0000000..3ce77d8 --- /dev/null +++ b/cortex_m/peripheral/cbp/struct.RegisterBlock.html @@ -0,0 +1,78 @@ +cortex_m::peripheral::cbp::RegisterBlock - Rust

      [−][src]Struct cortex_m::peripheral::cbp::RegisterBlock

      #[repr(C)]
+
      pub struct RegisterBlock {
+    pub iciallu: WO<u32>,
+    pub icimvau: WO<u32>,
+    pub dcimvac: WO<u32>,
+    pub dcisw: WO<u32>,
+    pub dccmvau: WO<u32>,
+    pub dccmvac: WO<u32>,
+    pub dccsw: WO<u32>,
+    pub dccimvac: WO<u32>,
+    pub dccisw: WO<u32>,
+    pub bpiall: WO<u32>,
+    // some fields omitted
+}

      Register block

      +

      + Fields

      + +

      I-cache invalidate all to PoU

      +
      + +

      I-cache invalidate by MVA to PoU

      +
      + +

      D-cache invalidate by MVA to PoC

      +
      + +

      D-cache invalidate by set-way

      +
      + +

      D-cache clean by MVA to PoU

      +
      + +

      D-cache clean by MVA to PoC

      +
      + +

      D-cache clean by set-way

      +
      + +

      D-cache clean and invalidate by MVA to PoC

      +
      + +

      D-cache clean and invalidate by set-way

      +
      + +

      Branch predictor invalidate all

      +

      Auto Trait Implementations

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/cpuid/CsselrCacheType.t.html b/cortex_m/peripheral/cpuid/CsselrCacheType.t.html new file mode 100644 index 0000000..82892f1 --- /dev/null +++ b/cortex_m/peripheral/cpuid/CsselrCacheType.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to enum.CsselrCacheType.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/cpuid/RegisterBlock.t.html b/cortex_m/peripheral/cpuid/RegisterBlock.t.html new file mode 100644 index 0000000..95870c5 --- /dev/null +++ b/cortex_m/peripheral/cpuid/RegisterBlock.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.RegisterBlock.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/cpuid/enum.CsselrCacheType.html b/cortex_m/peripheral/cpuid/enum.CsselrCacheType.html new file mode 100644 index 0000000..54779c0 --- /dev/null +++ b/cortex_m/peripheral/cpuid/enum.CsselrCacheType.html @@ -0,0 +1,21 @@ +cortex_m::peripheral::cpuid::CsselrCacheType - Rust

      [−][src]Enum cortex_m::peripheral::cpuid::CsselrCacheType

      pub enum CsselrCacheType {
+    DataOrUnified,
+    Instruction,
+}

      Type of cache to select on CSSELR writes.

      +

      + Variants

      +

      Select DCache or unified cache

      +

      Select ICache

      +

      Auto Trait Implementations

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/cpuid/index.html b/cortex_m/peripheral/cpuid/index.html new file mode 100644 index 0000000..ddc4a65 --- /dev/null +++ b/cortex_m/peripheral/cpuid/index.html @@ -0,0 +1,20 @@ +cortex_m::peripheral::cpuid - Rust

      [−][src]Module cortex_m::peripheral::cpuid

      CPUID

      +

      Structs

      + + + + +
      RegisterBlock +

      Register block

      + +

      Enums

      + + + + +
      CsselrCacheType +

      Type of cache to select on CSSELR writes.

      + +
      \ No newline at end of file diff --git a/cortex_m/peripheral/cpuid/sidebar-items.js b/cortex_m/peripheral/cpuid/sidebar-items.js new file mode 100644 index 0000000..af3d11d --- /dev/null +++ b/cortex_m/peripheral/cpuid/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"enum":[["CsselrCacheType","Type of cache to select on CSSELR writes."]],"struct":[["RegisterBlock","Register block"]]}); \ No newline at end of file diff --git a/cortex_m/peripheral/cpuid/struct.RegisterBlock.html b/cortex_m/peripheral/cpuid/struct.RegisterBlock.html new file mode 100644 index 0000000..848c079 --- /dev/null +++ b/cortex_m/peripheral/cpuid/struct.RegisterBlock.html @@ -0,0 +1,78 @@ +cortex_m::peripheral::cpuid::RegisterBlock - Rust

      [−][src]Struct cortex_m::peripheral::cpuid::RegisterBlock

      #[repr(C)]
+
      pub struct RegisterBlock {
+    pub base: RO<u32>,
+    pub pfr: [RO<u32>; 2],
+    pub dfr: RO<u32>,
+    pub afr: RO<u32>,
+    pub mmfr: [RO<u32>; 4],
+    pub isar: [RO<u32>; 5],
+    pub clidr: RO<u32>,
+    pub ctr: RO<u32>,
+    pub ccsidr: RO<u32>,
+    pub csselr: RW<u32>,
+    // some fields omitted
+}

      Register block

      +

      + Fields

      + +

      CPUID base

      +
      + +

      Processor Feature (not present on Cortex-M0 variants)

      +
      + +

      Debug Feature (not present on Cortex-M0 variants)

      +
      + +

      Auxiliary Feature (not present on Cortex-M0 variants)

      +
      + +

      Memory Model Feature (not present on Cortex-M0 variants)

      +
      + +

      Instruction Set Attribute (not present on Cortex-M0 variants)

      +
      + +

      Cache Level ID (only present on Cortex-M7)

      +
      + +

      Cache Type (only present on Cortex-M7)

      +
      + +

      Cache Size ID (only present on Cortex-M7)

      +
      + +

      Cache Size Selection (only present on Cortex-M7)

      +

      Auto Trait Implementations

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/dcb/RegisterBlock.t.html b/cortex_m/peripheral/dcb/RegisterBlock.t.html new file mode 100644 index 0000000..95870c5 --- /dev/null +++ b/cortex_m/peripheral/dcb/RegisterBlock.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.RegisterBlock.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/dcb/index.html b/cortex_m/peripheral/dcb/index.html new file mode 100644 index 0000000..4532307 --- /dev/null +++ b/cortex_m/peripheral/dcb/index.html @@ -0,0 +1,11 @@ +cortex_m::peripheral::dcb - Rust

      [−][src]Module cortex_m::peripheral::dcb

      Debug Control Block

      +

      Structs

      + + + + +
      RegisterBlock +

      Register block

      + +
      \ No newline at end of file diff --git a/cortex_m/peripheral/dcb/sidebar-items.js b/cortex_m/peripheral/dcb/sidebar-items.js new file mode 100644 index 0000000..9e664d0 --- /dev/null +++ b/cortex_m/peripheral/dcb/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"struct":[["RegisterBlock","Register block"]]}); \ No newline at end of file diff --git a/cortex_m/peripheral/dcb/struct.RegisterBlock.html b/cortex_m/peripheral/dcb/struct.RegisterBlock.html new file mode 100644 index 0000000..11a24b9 --- /dev/null +++ b/cortex_m/peripheral/dcb/struct.RegisterBlock.html @@ -0,0 +1,41 @@ +cortex_m::peripheral::dcb::RegisterBlock - Rust

      [−][src]Struct cortex_m::peripheral::dcb::RegisterBlock

      #[repr(C)]
+
      pub struct RegisterBlock {
+    pub dhcsr: RW<u32>,
+    pub dcrsr: WO<u32>,
+    pub dcrdr: RW<u32>,
+    pub demcr: RW<u32>,
+}

      Register block

      +

      + Fields

      + +

      Debug Halting Control and Status

      +
      + +

      Debug Core Register Selector

      +
      + +

      Debug Core Register Data

      +
      + +

      Debug Exception and Monitor Control

      +

      Auto Trait Implementations

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/dwt/Comparator.t.html b/cortex_m/peripheral/dwt/Comparator.t.html new file mode 100644 index 0000000..d266483 --- /dev/null +++ b/cortex_m/peripheral/dwt/Comparator.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.Comparator.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/dwt/RegisterBlock.t.html b/cortex_m/peripheral/dwt/RegisterBlock.t.html new file mode 100644 index 0000000..95870c5 --- /dev/null +++ b/cortex_m/peripheral/dwt/RegisterBlock.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.RegisterBlock.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/dwt/index.html b/cortex_m/peripheral/dwt/index.html new file mode 100644 index 0000000..2a89609 --- /dev/null +++ b/cortex_m/peripheral/dwt/index.html @@ -0,0 +1,19 @@ +cortex_m::peripheral::dwt - Rust

      [−][src]Module cortex_m::peripheral::dwt

      Data Watchpoint and Trace unit

      +

      Structs

      + + + + + + + + +
      Comparator +

      Comparator

      + +
      RegisterBlock +

      Register block

      + +
      \ No newline at end of file diff --git a/cortex_m/peripheral/dwt/sidebar-items.js b/cortex_m/peripheral/dwt/sidebar-items.js new file mode 100644 index 0000000..2bd2b84 --- /dev/null +++ b/cortex_m/peripheral/dwt/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"struct":[["Comparator","Comparator"],["RegisterBlock","Register block"]]}); \ No newline at end of file diff --git a/cortex_m/peripheral/dwt/struct.Comparator.html b/cortex_m/peripheral/dwt/struct.Comparator.html new file mode 100644 index 0000000..e25925f --- /dev/null +++ b/cortex_m/peripheral/dwt/struct.Comparator.html @@ -0,0 +1,36 @@ +cortex_m::peripheral::dwt::Comparator - Rust

      [−][src]Struct cortex_m::peripheral::dwt::Comparator

      #[repr(C)]
+
      pub struct Comparator {
+    pub comp: RW<u32>,
+    pub mask: RW<u32>,
+    pub function: RW<u32>,
+    // some fields omitted
+}

      Comparator

      +

      + Fields

      + +

      Comparator

      +
      + +

      Comparator Mask

      +
      + +

      Comparator Function

      +

      Auto Trait Implementations

      impl Send for Comparator

      impl !Sync for Comparator

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/dwt/struct.RegisterBlock.html b/cortex_m/peripheral/dwt/struct.RegisterBlock.html new file mode 100644 index 0000000..7705a25 --- /dev/null +++ b/cortex_m/peripheral/dwt/struct.RegisterBlock.html @@ -0,0 +1,84 @@ +cortex_m::peripheral::dwt::RegisterBlock - Rust

      [−][src]Struct cortex_m::peripheral::dwt::RegisterBlock

      #[repr(C)]
+
      pub struct RegisterBlock {
+    pub ctrl: RW<u32>,
+    pub cyccnt: RW<u32>,
+    pub cpicnt: RW<u32>,
+    pub exccnt: RW<u32>,
+    pub sleepcnt: RW<u32>,
+    pub lsucnt: RW<u32>,
+    pub foldcnt: RW<u32>,
+    pub pcsr: RO<u32>,
+    pub c: [Comparator; 16],
+    pub lar: WO<u32>,
+    pub lsr: RO<u32>,
+    // some fields omitted
+}

      Register block

      +

      + Fields

      + +

      Control

      +
      + +

      Cycle Count

      +
      + +

      CPI Count

      +
      + +

      Exception Overhead Count

      +
      + +

      Sleep Count

      +
      + +

      LSU Count

      +
      + +

      Folded-instruction Count

      +
      + +

      Program Counter Sample

      +
      + +

      Comparators

      +
      + +

      Lock Access

      +
      + +

      Lock Status

      +

      Auto Trait Implementations

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/fpb/RegisterBlock.t.html b/cortex_m/peripheral/fpb/RegisterBlock.t.html new file mode 100644 index 0000000..95870c5 --- /dev/null +++ b/cortex_m/peripheral/fpb/RegisterBlock.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.RegisterBlock.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/fpb/index.html b/cortex_m/peripheral/fpb/index.html new file mode 100644 index 0000000..d8ac74b --- /dev/null +++ b/cortex_m/peripheral/fpb/index.html @@ -0,0 +1,12 @@ +cortex_m::peripheral::fpb - Rust

      [−][src]Module cortex_m::peripheral::fpb

      Flash Patch and Breakpoint unit

      +

      NOTE Available only on ARMv7-M (thumbv7*m-none-eabi*)

      +

      Structs

      + + + + +
      RegisterBlock +

      Register block

      + +
      \ No newline at end of file diff --git a/cortex_m/peripheral/fpb/sidebar-items.js b/cortex_m/peripheral/fpb/sidebar-items.js new file mode 100644 index 0000000..9e664d0 --- /dev/null +++ b/cortex_m/peripheral/fpb/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"struct":[["RegisterBlock","Register block"]]}); \ No newline at end of file diff --git a/cortex_m/peripheral/fpb/struct.RegisterBlock.html b/cortex_m/peripheral/fpb/struct.RegisterBlock.html new file mode 100644 index 0000000..735efd1 --- /dev/null +++ b/cortex_m/peripheral/fpb/struct.RegisterBlock.html @@ -0,0 +1,48 @@ +cortex_m::peripheral::fpb::RegisterBlock - Rust

      [−][src]Struct cortex_m::peripheral::fpb::RegisterBlock

      #[repr(C)]
+
      pub struct RegisterBlock {
+    pub ctrl: RW<u32>,
+    pub remap: RW<u32>,
+    pub comp: [RW<u32>; 127],
+    pub lar: WO<u32>,
+    pub lsr: RO<u32>,
+    // some fields omitted
+}

      Register block

      +

      + Fields

      + +

      Control

      +
      + +

      Remap

      +
      + +

      Comparator

      +
      + +

      Lock Access

      +
      + +

      Lock Status

      +

      Auto Trait Implementations

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/fpu/RegisterBlock.t.html b/cortex_m/peripheral/fpu/RegisterBlock.t.html new file mode 100644 index 0000000..95870c5 --- /dev/null +++ b/cortex_m/peripheral/fpu/RegisterBlock.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.RegisterBlock.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/fpu/index.html b/cortex_m/peripheral/fpu/index.html new file mode 100644 index 0000000..fa0c2ab --- /dev/null +++ b/cortex_m/peripheral/fpu/index.html @@ -0,0 +1,12 @@ +cortex_m::peripheral::fpu - Rust

      [−][src]Module cortex_m::peripheral::fpu

      Floating Point Unit

      +

      NOTE Available only on ARMv7E-M (thumbv7em-none-eabihf)

      +

      Structs

      + + + + +
      RegisterBlock +

      Register block

      + +
      \ No newline at end of file diff --git a/cortex_m/peripheral/fpu/sidebar-items.js b/cortex_m/peripheral/fpu/sidebar-items.js new file mode 100644 index 0000000..9e664d0 --- /dev/null +++ b/cortex_m/peripheral/fpu/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"struct":[["RegisterBlock","Register block"]]}); \ No newline at end of file diff --git a/cortex_m/peripheral/fpu/struct.RegisterBlock.html b/cortex_m/peripheral/fpu/struct.RegisterBlock.html new file mode 100644 index 0000000..e13a2d8 --- /dev/null +++ b/cortex_m/peripheral/fpu/struct.RegisterBlock.html @@ -0,0 +1,42 @@ +cortex_m::peripheral::fpu::RegisterBlock - Rust

      [−][src]Struct cortex_m::peripheral::fpu::RegisterBlock

      #[repr(C)]
+
      pub struct RegisterBlock {
+    pub fpccr: RW<u32>,
+    pub fpcar: RW<u32>,
+    pub fpdscr: RW<u32>,
+    pub mvfr: [RO<u32>; 3],
+    // some fields omitted
+}

      Register block

      +

      + Fields

      + +

      Floating Point Context Control

      +
      + +

      Floating Point Context Address

      +
      + +

      Floating Point Default Status Control

      +
      + +

      Media and FP Feature

      +

      Auto Trait Implementations

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/index.html b/cortex_m/peripheral/index.html new file mode 100644 index 0000000..937d7cf --- /dev/null +++ b/cortex_m/peripheral/index.html @@ -0,0 +1,271 @@ +cortex_m::peripheral - Rust

      [−][src]Module cortex_m::peripheral

      Core peripherals

      +

      API

      +

      To use (most of) the peripheral API first you must get an instance of the peripheral. All the +core peripherals are modeled as singletons (there can only ever be, at most, one instance of any +one of them at any given point in time) and the only way to get an instance of them is through +the Peripherals::take method.

      + +
      +extern crate cortex_m;
+
+use cortex_m::peripheral::Peripherals;
+
+fn main() {
+    let mut peripherals = Peripherals::take().unwrap();
+    peripherals.DWT.enable_cycle_counter();
+}
      +

      This method can only be successfully called once -- this is why the method returns an +Option. Subsequent calls to the method will result in a None value being returned.

      + +
      +extern crate cortex_m;
+
+use cortex_m::peripheral::Peripherals;
+
+fn main() {
+    let ok = Peripherals::take().unwrap();
+    let panics = Peripherals::take().unwrap();
+}
      +

      A part of the peripheral API doesn't require access to a peripheral instance. This part of the +API is provided as static methods on the peripheral types. One example is the +DWT::get_cycle_count method.

      + +
      +extern crate cortex_m;
+
+use cortex_m::peripheral::{DWT, Peripherals};
+
+fn main() {
+    {
+        let mut peripherals = Peripherals::take().unwrap();
+        peripherals.DWT.enable_cycle_counter();
+    } // all the peripheral singletons are destroyed here
+
+    // but this method can be called without a DWT instance
+    let cyccnt = DWT::get_cycle_count();
+}
      +

      The singleton property can be unsafely bypassed using the ptr static method which is +available on all the peripheral types. This method is a useful building block for implementing +safe higher level abstractions.

      + +
      +extern crate cortex_m;
+
+use cortex_m::peripheral::{DWT, Peripherals};
+
+fn main() {
+    {
+        let mut peripherals = Peripherals::take().unwrap();
+        peripherals.DWT.enable_cycle_counter();
+    } // all the peripheral singletons are destroyed here
+
+    // actually safe because this is an atomic read with no side effects
+    let cyccnt = unsafe { (*DWT::ptr()).cyccnt.read() };
+}
      +

      References

      +
        +
      • ARMv7-M Architecture Reference Manual (Issue E.b) - Chapter B3
        • +
      +

      Modules

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      cbp +

      Cache and branch predictor maintenance operations

      + +
      cpuid +

      CPUID

      + +
      dcb +

      Debug Control Block

      + +
      dwt +

      Data Watchpoint and Trace unit

      + +
      fpb +

      Flash Patch and Breakpoint unit

      + +
      fpu +

      Floating Point Unit

      + +
      itm +

      Instrumentation Trace Macrocell

      + +
      mpu +

      Memory Protection Unit

      + +
      nvic +

      Nested Vector Interrupt Controller

      + +
      scb +

      System Control Block

      + +
      syst +

      SysTick: System Timer

      + +
      tpiu +

      Trace Port Interface Unit;

      + +

      Structs

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      CBP +

      Cache and branch predictor maintenance operations

      + +
      CPUID +

      CPUID

      + +
      DCB +

      Debug Control Block

      + +
      DWT +

      Data Watchpoint and Trace unit

      + +
      FPB +

      Flash Patch and Breakpoint unit

      + +
      FPU +

      Floating Point Unit

      + +
      ITM +

      Instrumentation Trace Macrocell

      + +
      MPU +

      Memory Protection Unit

      + +
      NVIC +

      Nested Vector Interrupt Controller

      + +
      Peripherals +

      Core peripherals

      + +
      SCB +

      System Control Block

      + +
      SYST +

      SysTick: System Timer

      + +
      TPIU +

      Trace Port Interface Unit

      + +
      \ No newline at end of file diff --git a/cortex_m/peripheral/itm/RegisterBlock.t.html b/cortex_m/peripheral/itm/RegisterBlock.t.html new file mode 100644 index 0000000..95870c5 --- /dev/null +++ b/cortex_m/peripheral/itm/RegisterBlock.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.RegisterBlock.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/itm/Stim.t.html b/cortex_m/peripheral/itm/Stim.t.html new file mode 100644 index 0000000..0f19c4d --- /dev/null +++ b/cortex_m/peripheral/itm/Stim.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.Stim.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/itm/index.html b/cortex_m/peripheral/itm/index.html new file mode 100644 index 0000000..dac78f4 --- /dev/null +++ b/cortex_m/peripheral/itm/index.html @@ -0,0 +1,20 @@ +cortex_m::peripheral::itm - Rust

      [−][src]Module cortex_m::peripheral::itm

      Instrumentation Trace Macrocell

      +

      NOTE Available only on ARMv7-M (thumbv7*m-none-eabi*)

      +

      Structs

      + + + + + + + + +
      RegisterBlock +

      Register block

      + +
      Stim +

      Stimulus Port

      + +
      \ No newline at end of file diff --git a/cortex_m/peripheral/itm/sidebar-items.js b/cortex_m/peripheral/itm/sidebar-items.js new file mode 100644 index 0000000..580ccd3 --- /dev/null +++ b/cortex_m/peripheral/itm/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"struct":[["RegisterBlock","Register block"],["Stim","Stimulus Port"]]}); \ No newline at end of file diff --git a/cortex_m/peripheral/itm/struct.RegisterBlock.html b/cortex_m/peripheral/itm/struct.RegisterBlock.html new file mode 100644 index 0000000..2f6b41d --- /dev/null +++ b/cortex_m/peripheral/itm/struct.RegisterBlock.html @@ -0,0 +1,54 @@ +cortex_m::peripheral::itm::RegisterBlock - Rust

      [−][src]Struct cortex_m::peripheral::itm::RegisterBlock

      #[repr(C)]
+
      pub struct RegisterBlock {
+    pub stim: [Stim; 256],
+    pub ter: [RW<u32>; 8],
+    pub tpr: RW<u32>,
+    pub tcr: RW<u32>,
+    pub lar: WO<u32>,
+    pub lsr: RO<u32>,
+    // some fields omitted
+}

      Register block

      +

      + Fields

      + +

      Stimulus Port

      +
      + +

      Trace Enable

      +
      + +

      Trace Privilege

      +
      + +

      Trace Control

      +
      + +

      Lock Access

      +
      + +

      Lock Status

      +

      Auto Trait Implementations

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/itm/struct.Stim.html b/cortex_m/peripheral/itm/struct.Stim.html new file mode 100644 index 0000000..dc0be69 --- /dev/null +++ b/cortex_m/peripheral/itm/struct.Stim.html @@ -0,0 +1,18 @@ +cortex_m::peripheral::itm::Stim - Rust

      [−][src]Struct cortex_m::peripheral::itm::Stim

      pub struct Stim { /* fields omitted */ }

      Stimulus Port

      +

      Methods

      impl Stim
      [src]

      Writes an u8 payload into the stimulus port

      +

      Writes an u16 payload into the stimulus port

      +

      Writes an u32 payload into the stimulus port

      +

      Returns true if the stimulus port is ready to accept more data

      +

      Auto Trait Implementations

      impl Send for Stim

      impl !Sync for Stim

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/mpu/RegisterBlock.t.html b/cortex_m/peripheral/mpu/RegisterBlock.t.html new file mode 100644 index 0000000..95870c5 --- /dev/null +++ b/cortex_m/peripheral/mpu/RegisterBlock.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.RegisterBlock.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/mpu/index.html b/cortex_m/peripheral/mpu/index.html new file mode 100644 index 0000000..31b2512 --- /dev/null +++ b/cortex_m/peripheral/mpu/index.html @@ -0,0 +1,11 @@ +cortex_m::peripheral::mpu - Rust

      [−][src]Module cortex_m::peripheral::mpu

      Memory Protection Unit

      +

      Structs

      + + + + +
      RegisterBlock +

      Register block

      + +
      \ No newline at end of file diff --git a/cortex_m/peripheral/mpu/sidebar-items.js b/cortex_m/peripheral/mpu/sidebar-items.js new file mode 100644 index 0000000..9e664d0 --- /dev/null +++ b/cortex_m/peripheral/mpu/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"struct":[["RegisterBlock","Register block"]]}); \ No newline at end of file diff --git a/cortex_m/peripheral/mpu/struct.RegisterBlock.html b/cortex_m/peripheral/mpu/struct.RegisterBlock.html new file mode 100644 index 0000000..192d6a2 --- /dev/null +++ b/cortex_m/peripheral/mpu/struct.RegisterBlock.html @@ -0,0 +1,83 @@ +cortex_m::peripheral::mpu::RegisterBlock - Rust

      [−][src]Struct cortex_m::peripheral::mpu::RegisterBlock

      #[repr(C)]
+
      pub struct RegisterBlock {
+    pub _type: RO<u32>,
+    pub ctrl: RW<u32>,
+    pub rnr: RW<u32>,
+    pub rbar: RW<u32>,
+    pub rasr: RW<u32>,
+    pub rbar_a1: RW<u32>,
+    pub rsar_a1: RW<u32>,
+    pub rbar_a2: RW<u32>,
+    pub rsar_a2: RW<u32>,
+    pub rbar_a3: RW<u32>,
+    pub rsar_a3: RW<u32>,
+}

      Register block

      +

      + Fields

      + +

      Type

      +
      + +

      Control

      +
      + +

      Region Number

      +
      + +

      Region Base Address

      +
      + +

      Region Attribute and Size

      +
      + +

      Alias 1 of RBAR

      +
      + +

      Alias 1 of RSAR

      +
      + +

      Alias 2 of RBAR

      +
      + +

      Alias 2 of RSAR

      +
      + +

      Alias 3 of RBAR

      +
      + +

      Alias 3 of RSAR

      +

      Auto Trait Implementations

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/nvic/RegisterBlock.t.html b/cortex_m/peripheral/nvic/RegisterBlock.t.html new file mode 100644 index 0000000..95870c5 --- /dev/null +++ b/cortex_m/peripheral/nvic/RegisterBlock.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.RegisterBlock.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/nvic/index.html b/cortex_m/peripheral/nvic/index.html new file mode 100644 index 0000000..59b6ad3 --- /dev/null +++ b/cortex_m/peripheral/nvic/index.html @@ -0,0 +1,11 @@ +cortex_m::peripheral::nvic - Rust

      [−][src]Module cortex_m::peripheral::nvic

      Nested Vector Interrupt Controller

      +

      Structs

      + + + + +
      RegisterBlock +

      Register block

      + +
      \ No newline at end of file diff --git a/cortex_m/peripheral/nvic/sidebar-items.js b/cortex_m/peripheral/nvic/sidebar-items.js new file mode 100644 index 0000000..9e664d0 --- /dev/null +++ b/cortex_m/peripheral/nvic/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"struct":[["RegisterBlock","Register block"]]}); \ No newline at end of file diff --git a/cortex_m/peripheral/nvic/struct.RegisterBlock.html b/cortex_m/peripheral/nvic/struct.RegisterBlock.html new file mode 100644 index 0000000..b487cf1 --- /dev/null +++ b/cortex_m/peripheral/nvic/struct.RegisterBlock.html @@ -0,0 +1,62 @@ +cortex_m::peripheral::nvic::RegisterBlock - Rust

      [−][src]Struct cortex_m::peripheral::nvic::RegisterBlock

      #[repr(C)]
+
      pub struct RegisterBlock {
+    pub iser: [RW<u32>; 16],
+    pub icer: [RW<u32>; 16],
+    pub ispr: [RW<u32>; 16],
+    pub icpr: [RW<u32>; 16],
+    pub iabr: [RO<u32>; 16],
+    pub ipr: [RW<u8>; 496],
+    // some fields omitted
+}

      Register block

      +

      + Fields

      + +

      Interrupt Set-Enable

      +
      + +

      Interrupt Clear-Enable

      +
      + +

      Interrupt Set-Pending

      +
      + +

      Interrupt Clear-Pending

      +
      + +

      Interrupt Active Bit (not present on Cortex-M0 variants)

      +
      + +

      Interrupt Priority

      +

      On ARMv7-M, 124 word-sized registers are available. Each of those +contains of 4 interrupt priorities of 8 byte each.The architecture +specifically allows accessing those along byte boundaries, so they are +represented as 496 byte-sized registers, for convenience, and to allow +atomic priority updates.

      +

      On ARMv6-M, the registers must only be accessed along word boundaries, +so convenient byte-sized representation wouldn't work on that +architecture.

      +

      Auto Trait Implementations

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/scb/Exception.t.html b/cortex_m/peripheral/scb/Exception.t.html new file mode 100644 index 0000000..77f30c1 --- /dev/null +++ b/cortex_m/peripheral/scb/Exception.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to enum.Exception.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/scb/RegisterBlock.t.html b/cortex_m/peripheral/scb/RegisterBlock.t.html new file mode 100644 index 0000000..95870c5 --- /dev/null +++ b/cortex_m/peripheral/scb/RegisterBlock.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.RegisterBlock.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/scb/VectActive.t.html b/cortex_m/peripheral/scb/VectActive.t.html new file mode 100644 index 0000000..2c7b223 --- /dev/null +++ b/cortex_m/peripheral/scb/VectActive.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to enum.VectActive.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/scb/enum.Exception.html b/cortex_m/peripheral/scb/enum.Exception.html new file mode 100644 index 0000000..a9c12dc --- /dev/null +++ b/cortex_m/peripheral/scb/enum.Exception.html @@ -0,0 +1,45 @@ +cortex_m::peripheral::scb::Exception - Rust

      [−][src]Enum cortex_m::peripheral::scb::Exception

      pub enum Exception {
+    NonMaskableInt,
+    HardFault,
+    MemoryManagement,
+    BusFault,
+    UsageFault,
+    SecureFault,
+    SVCall,
+    DebugMonitor,
+    PendSV,
+    SysTick,
+}

      Processor core exceptions (internal interrupts)

      +

      + Variants

      +

      Non maskable interrupt

      +

      Hard fault interrupt

      +

      Memory management interrupt (not present on Cortex-M0 variants)

      +

      Bus fault interrupt (not present on Cortex-M0 variants)

      +

      Usage fault interrupt (not present on Cortex-M0 variants)

      +

      Secure fault interrupt (only on ARMv8-M)

      +

      SV call interrupt

      +

      Debug monitor interrupt (not present on Cortex-M0 variants)

      +

      Pend SV interrupt

      +

      System Tick interrupt

      +

      Methods

      impl Exception
      [src]

      Returns the IRQ number of this Exception

      +

      The return value is always within the closed range [-1, -14]

      +

      Trait Implementations

      impl Clone for Exception
      [src]

      Returns a copy of the value. Read more

      +

      Performs copy-assignment from source. Read more

      +

      impl Copy for Exception
      [src]

      impl Debug for Exception
      [src]

      Formats the value using the given formatter. Read more

      +

      impl Eq for Exception
      [src]

      impl PartialEq for Exception
      [src]

      This method tests for self and other values to be equal, and is used by ==. Read more

      +

      This method tests for !=.

      +

      Auto Trait Implementations

      impl Send for Exception

      impl Sync for Exception

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/scb/enum.VectActive.html b/cortex_m/peripheral/scb/enum.VectActive.html new file mode 100644 index 0000000..33f6eeb --- /dev/null +++ b/cortex_m/peripheral/scb/enum.VectActive.html @@ -0,0 +1,34 @@ +cortex_m::peripheral::scb::VectActive - Rust

      [−][src]Enum cortex_m::peripheral::scb::VectActive

      pub enum VectActive {
+    ThreadMode,
+    Exception(Exception),
+    Interrupt {
+        irqn: u8,
+    },
+}

      Active exception number

      +

      + Variants

      +

      Thread mode

      +

      Processor core exception (internal interrupts)

      +

      Device specific exception (external interrupts)

      +

      Fields of Interrupt

      + +

      Interrupt number. This number is always within half open range [0, 240)

      +

      Methods

      impl VectActive
      [src]

      Converts a byte into VectActive

      +

      Trait Implementations

      impl Clone for VectActive
      [src]

      Returns a copy of the value. Read more

      +

      Performs copy-assignment from source. Read more

      +

      impl Copy for VectActive
      [src]

      impl Debug for VectActive
      [src]

      Formats the value using the given formatter. Read more

      +

      impl Eq for VectActive
      [src]

      impl PartialEq for VectActive
      [src]

      This method tests for self and other values to be equal, and is used by ==. Read more

      +

      This method tests for !=.

      +

      Auto Trait Implementations

      impl Send for VectActive

      impl Sync for VectActive

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/scb/index.html b/cortex_m/peripheral/scb/index.html new file mode 100644 index 0000000..fde92fa --- /dev/null +++ b/cortex_m/peripheral/scb/index.html @@ -0,0 +1,28 @@ +cortex_m::peripheral::scb - Rust

      [−][src]Module cortex_m::peripheral::scb

      System Control Block

      +

      Structs

      + + + + +
      RegisterBlock +

      Register block

      + +

      Enums

      + + + + + + + + +
      Exception +

      Processor core exceptions (internal interrupts)

      + +
      VectActive +

      Active exception number

      + +
      \ No newline at end of file diff --git a/cortex_m/peripheral/scb/sidebar-items.js b/cortex_m/peripheral/scb/sidebar-items.js new file mode 100644 index 0000000..1edfcc4 --- /dev/null +++ b/cortex_m/peripheral/scb/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"enum":[["Exception","Processor core exceptions (internal interrupts)"],["VectActive","Active exception number"]],"struct":[["RegisterBlock","Register block"]]}); \ No newline at end of file diff --git a/cortex_m/peripheral/scb/struct.RegisterBlock.html b/cortex_m/peripheral/scb/struct.RegisterBlock.html new file mode 100644 index 0000000..7942d9f --- /dev/null +++ b/cortex_m/peripheral/scb/struct.RegisterBlock.html @@ -0,0 +1,104 @@ +cortex_m::peripheral::scb::RegisterBlock - Rust

      [−][src]Struct cortex_m::peripheral::scb::RegisterBlock

      #[repr(C)]
+
      pub struct RegisterBlock {
+    pub icsr: RW<u32>,
+    pub vtor: RW<u32>,
+    pub aircr: RW<u32>,
+    pub scr: RW<u32>,
+    pub ccr: RW<u32>,
+    pub shpr: [RW<u8>; 12],
+    pub shcrs: RW<u32>,
+    pub cfsr: RW<u32>,
+    pub hfsr: RW<u32>,
+    pub dfsr: RW<u32>,
+    pub mmfar: RW<u32>,
+    pub bfar: RW<u32>,
+    pub afsr: RW<u32>,
+    pub cpacr: RW<u32>,
+    // some fields omitted
+}

      Register block

      +

      + Fields

      + +

      Interrupt Control and State

      +
      + +

      Vector Table Offset (not present on Cortex-M0 variants)

      +
      + +

      Application Interrupt and Reset Control

      +
      + +

      System Control

      +
      + +

      Configuration and Control

      +
      + +

      System Handler Priority (word accessible only on Cortex-M0 variants)

      +

      On ARMv7-M, shpr[0] points to SHPR1

      +

      On ARMv6-M, shpr[0] points to SHPR2

      +
      + +

      System Handler Control and State

      +
      + +

      Configurable Fault Status (not present on Cortex-M0 variants)

      +
      + +

      HardFault Status (not present on Cortex-M0 variants)

      +
      + +

      Debug Fault Status (not present on Cortex-M0 variants)

      +
      + +

      MemManage Fault Address (not present on Cortex-M0 variants)

      +
      + +

      BusFault Address (not present on Cortex-M0 variants)

      +
      + +

      Auxiliary Fault Status (not present on Cortex-M0 variants)

      +
      + +

      Coprocessor Access Control (not present on Cortex-M0 variants)

      +

      Auto Trait Implementations

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/sidebar-items.js b/cortex_m/peripheral/sidebar-items.js new file mode 100644 index 0000000..f7cbca1 --- /dev/null +++ b/cortex_m/peripheral/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"mod":[["cbp","Cache and branch predictor maintenance operations"],["cpuid","CPUID"],["dcb","Debug Control Block"],["dwt","Data Watchpoint and Trace unit"],["fpb","Flash Patch and Breakpoint unit"],["fpu","Floating Point Unit"],["itm","Instrumentation Trace Macrocell"],["mpu","Memory Protection Unit"],["nvic","Nested Vector Interrupt Controller"],["scb","System Control Block"],["syst","SysTick: System Timer"],["tpiu","Trace Port Interface Unit;"]],"struct":[["CBP","Cache and branch predictor maintenance operations"],["CPUID","CPUID"],["DCB","Debug Control Block"],["DWT","Data Watchpoint and Trace unit"],["FPB","Flash Patch and Breakpoint unit"],["FPU","Floating Point Unit"],["ITM","Instrumentation Trace Macrocell"],["MPU","Memory Protection Unit"],["NVIC","Nested Vector Interrupt Controller"],["Peripherals","Core peripherals"],["SCB","System Control Block"],["SYST","SysTick: System Timer"],["TPIU","Trace Port Interface Unit"]]}); \ No newline at end of file diff --git a/cortex_m/peripheral/struct.CBP.html b/cortex_m/peripheral/struct.CBP.html new file mode 100644 index 0000000..9029670 --- /dev/null +++ b/cortex_m/peripheral/struct.CBP.html @@ -0,0 +1,31 @@ +cortex_m::peripheral::CBP - Rust

      [−][src]Struct cortex_m::peripheral::CBP

      pub struct CBP { /* fields omitted */ }

      Cache and branch predictor maintenance operations

      +

      Methods

      impl CBP
      [src]

      I-cache invalidate all to PoU

      +

      I-cache invalidate by MVA to PoU

      +

      D-cache invalidate by MVA to PoC

      +

      D-cache invalidate by set-way

      +

      set is masked to be between 0 and 3, and way between 0 and 511.

      +

      D-cache clean by MVA to PoU

      +

      D-cache clean by MVA to PoC

      +

      D-cache clean by set-way

      +

      set is masked to be between 0 and 3, and way between 0 and 511.

      +

      D-cache clean and invalidate by MVA to PoC

      +

      D-cache clean and invalidate by set-way

      +

      set is masked to be between 0 and 3, and way between 0 and 511.

      +

      Branch predictor invalidate all

      +

      impl CBP
      [src]

      Returns a pointer to the register block

      +

      Trait Implementations

      impl Send for CBP
      [src]

      impl Deref for CBP
      [src]

      +

      The resulting type after dereferencing.

      +

      Dereferences the value.

      +

      Auto Trait Implementations

      impl !Sync for CBP

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/struct.CPUID.html b/cortex_m/peripheral/struct.CPUID.html new file mode 100644 index 0000000..e0ae667 --- /dev/null +++ b/cortex_m/peripheral/struct.CPUID.html @@ -0,0 +1,25 @@ +cortex_m::peripheral::CPUID - Rust

      [−][src]Struct cortex_m::peripheral::CPUID

      pub struct CPUID { /* fields omitted */ }

      CPUID

      +

      Methods

      impl CPUID
      [src]

      Selects the current CCSIDR

      +
        +
      • level: the required cache level minus 1, e.g. 0 for L1, 1 for L2
        • +
      • ind: select instruction cache or data/unified cache
        • +
      +

      level is masked to be between 0 and 7.

      +

      Returns the number of sets and ways in the selected cache

      +

      impl CPUID
      [src]

      Returns a pointer to the register block

      +

      Trait Implementations

      impl Send for CPUID
      [src]

      impl Deref for CPUID
      [src]

      +

      The resulting type after dereferencing.

      +

      Dereferences the value.

      +

      Auto Trait Implementations

      impl !Sync for CPUID

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/struct.DCB.html b/cortex_m/peripheral/struct.DCB.html new file mode 100644 index 0000000..817d527 --- /dev/null +++ b/cortex_m/peripheral/struct.DCB.html @@ -0,0 +1,18 @@ +cortex_m::peripheral::DCB - Rust

      [−][src]Struct cortex_m::peripheral::DCB

      pub struct DCB { /* fields omitted */ }

      Debug Control Block

      +

      Methods

      impl DCB
      [src]

      Returns a pointer to the register block

      +

      Trait Implementations

      impl Send for DCB
      [src]

      impl Deref for DCB
      [src]

      +

      The resulting type after dereferencing.

      +

      Dereferences the value.

      +

      Auto Trait Implementations

      impl !Sync for DCB

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/struct.DWT.html b/cortex_m/peripheral/struct.DWT.html new file mode 100644 index 0000000..dddc230 --- /dev/null +++ b/cortex_m/peripheral/struct.DWT.html @@ -0,0 +1,20 @@ +cortex_m::peripheral::DWT - Rust

      [−][src]Struct cortex_m::peripheral::DWT

      pub struct DWT { /* fields omitted */ }

      Data Watchpoint and Trace unit

      +

      Methods

      impl DWT
      [src]

      Enables the cycle counter

      +

      Returns the current clock cycle count

      +

      impl DWT
      [src]

      Returns a pointer to the register block

      +

      Trait Implementations

      impl Send for DWT
      [src]

      impl Deref for DWT
      [src]

      +

      The resulting type after dereferencing.

      +

      Dereferences the value.

      +

      Auto Trait Implementations

      impl !Sync for DWT

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/struct.FPB.html b/cortex_m/peripheral/struct.FPB.html new file mode 100644 index 0000000..17d04f6 --- /dev/null +++ b/cortex_m/peripheral/struct.FPB.html @@ -0,0 +1,18 @@ +cortex_m::peripheral::FPB - Rust

      [−][src]Struct cortex_m::peripheral::FPB

      pub struct FPB { /* fields omitted */ }

      Flash Patch and Breakpoint unit

      +

      Methods

      impl FPB
      [src]

      Returns a pointer to the register block

      +

      Trait Implementations

      impl Send for FPB
      [src]

      impl Deref for FPB
      [src]

      +

      The resulting type after dereferencing.

      +

      Dereferences the value.

      +

      Auto Trait Implementations

      impl !Sync for FPB

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/struct.FPU.html b/cortex_m/peripheral/struct.FPU.html new file mode 100644 index 0000000..15be950 --- /dev/null +++ b/cortex_m/peripheral/struct.FPU.html @@ -0,0 +1,18 @@ +cortex_m::peripheral::FPU - Rust

      [−][src]Struct cortex_m::peripheral::FPU

      pub struct FPU { /* fields omitted */ }

      Floating Point Unit

      +

      Methods

      impl FPU
      [src]

      Returns a pointer to the register block

      +

      Trait Implementations

      impl Send for FPU
      [src]

      impl Deref for FPU
      [src]

      +

      The resulting type after dereferencing.

      +

      Dereferences the value.

      +

      Auto Trait Implementations

      impl !Sync for FPU

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/struct.ITM.html b/cortex_m/peripheral/struct.ITM.html new file mode 100644 index 0000000..4104dfd --- /dev/null +++ b/cortex_m/peripheral/struct.ITM.html @@ -0,0 +1,19 @@ +cortex_m::peripheral::ITM - Rust

      [−][src]Struct cortex_m::peripheral::ITM

      pub struct ITM { /* fields omitted */ }

      Instrumentation Trace Macrocell

      +

      Methods

      impl ITM
      [src]

      Returns a pointer to the register block

      +

      Trait Implementations

      impl Send for ITM
      [src]

      impl Deref for ITM
      [src]

      +

      The resulting type after dereferencing.

      +

      Dereferences the value.

      +

      impl DerefMut for ITM
      [src]

      Mutably dereferences the value.

      +

      Auto Trait Implementations

      impl !Sync for ITM

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/struct.MPU.html b/cortex_m/peripheral/struct.MPU.html new file mode 100644 index 0000000..0ffdb3a --- /dev/null +++ b/cortex_m/peripheral/struct.MPU.html @@ -0,0 +1,18 @@ +cortex_m::peripheral::MPU - Rust

      [−][src]Struct cortex_m::peripheral::MPU

      pub struct MPU { /* fields omitted */ }

      Memory Protection Unit

      +

      Methods

      impl MPU
      [src]

      Returns a pointer to the register block

      +

      Trait Implementations

      impl Send for MPU
      [src]

      impl Deref for MPU
      [src]

      +

      The resulting type after dereferencing.

      +

      Dereferences the value.

      +

      Auto Trait Implementations

      impl !Sync for MPU

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/struct.NVIC.html b/cortex_m/peripheral/struct.NVIC.html new file mode 100644 index 0000000..c31d535 --- /dev/null +++ b/cortex_m/peripheral/struct.NVIC.html @@ -0,0 +1,34 @@ +cortex_m::peripheral::NVIC - Rust

      [−][src]Struct cortex_m::peripheral::NVIC

      pub struct NVIC { /* fields omitted */ }

      Nested Vector Interrupt Controller

      +

      Methods

      impl NVIC
      [src]

      Clears interrupt's pending state

      +

      Disables interrupt

      +

      Enables interrupt

      +

      Returns the NVIC priority of interrupt

      +

      NOTE NVIC encodes priority in the highest bits of a byte so values like 1 and 2 map +to the same priority. Also for NVIC priorities, a lower value (e.g. 16) has higher +priority (urgency) than a larger value (e.g. 32).

      +

      Is interrupt active or pre-empted and stacked

      +

      Checks if interrupt is enabled

      +

      Checks if interrupt is pending

      +

      Forces interrupt into pending state

      +

      Sets the "priority" of interrupt to prio

      +

      NOTE See get_priority method for an explanation +of how NVIC priorities work.

      +

      On ARMv6-M, updating an interrupt priority requires a read-modify-write operation. On +ARMv7-M, the operation is performed in a single atomic write operation.

      +

      impl NVIC
      [src]

      Returns a pointer to the register block

      +

      Trait Implementations

      impl Send for NVIC
      [src]

      impl Deref for NVIC
      [src]

      +

      The resulting type after dereferencing.

      +

      Dereferences the value.

      +

      Auto Trait Implementations

      impl !Sync for NVIC

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/struct.Peripherals.html b/cortex_m/peripheral/struct.Peripherals.html new file mode 100644 index 0000000..01950e2 --- /dev/null +++ b/cortex_m/peripheral/struct.Peripherals.html @@ -0,0 +1,90 @@ +cortex_m::peripheral::Peripherals - Rust

      [−][src]Struct cortex_m::peripheral::Peripherals

      pub struct Peripherals {
+    pub CBP: CBP,
+    pub CPUID: CPUID,
+    pub DCB: DCB,
+    pub DWT: DWT,
+    pub FPB: FPB,
+    pub FPU: FPU,
+    pub ITM: ITM,
+    pub MPU: MPU,
+    pub NVIC: NVIC,
+    pub SCB: SCB,
+    pub SYST: SYST,
+    pub TPIU: TPIU,
+}

      Core peripherals

      +

      + Fields

      + +

      Cache and branch predictor maintenance operations (not present on Cortex-M0 variants)

      +
      + +

      CPUID

      +
      + +

      Debug Control Block

      +
      + +

      Data Watchpoint and Trace unit

      +
      + +

      Flash Patch and Breakpoint unit (not present on Cortex-M0 variants)

      +
      + +

      Floating Point Unit (only present on thumbv7em-none-eabihf)

      +
      + +

      Instrumentation Trace Macrocell (not present on Cortex-M0 variants)

      +
      + +

      Memory Protection Unit

      +
      + +

      Nested Vector Interrupt Controller

      +
      + +

      System Control Block

      +
      + +

      SysTick: System Timer

      +
      + +

      Trace Port Interface Unit (not present on Cortex-M0 variants)

      +

      Methods

      impl Peripherals
      [src]

      Returns all the core peripherals once

      +

      Unchecked version of Peripherals::take

      +

      Auto Trait Implementations

      impl Send for Peripherals

      impl !Sync for Peripherals

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/struct.SCB.html b/cortex_m/peripheral/struct.SCB.html new file mode 100644 index 0000000..7f4229d --- /dev/null +++ b/cortex_m/peripheral/struct.SCB.html @@ -0,0 +1,47 @@ +cortex_m::peripheral::SCB - Rust

      [−][src]Struct cortex_m::peripheral::SCB

      pub struct SCB { /* fields omitted */ }

      System Control Block

      +

      Methods

      impl SCB
      [src]

      Returns the active exception number

      +

      impl SCB
      [src]

      Enables I-Cache if currently disabled

      +

      Disables I-Cache if currently enabled

      +

      Returns whether the I-Cache is currently enabled

      +

      Invalidates I-Cache

      +

      Enables D-cache if currently disabled

      +

      Disables D-cache if currently enabled

      +

      Returns whether the D-Cache is currently enabled

      +

      Cleans D-cache

      +

      Cleans and invalidates D-cache

      +

      Invalidates D-cache by address

      +

      addr: the address to invalidate +size: size of the memory block, in number of bytes

      +

      Invalidates cache starting from the lowest 32-byte aligned address represented by addr, +in blocks of 32 bytes until at least size bytes have been invalidated.

      +

      Cleans D-cache by address

      +

      addr: the address to clean +size: size of the memory block, in number of bytes

      +

      Cleans cache starting from the lowest 32-byte aligned address represented by addr, +in blocks of 32 bytes until at least size bytes have been cleaned.

      +

      Cleans and invalidates D-cache by address

      +

      addr: the address to clean and invalidate +size: size of the memory block, in number of bytes

      +

      Cleans and invalidates cache starting from the lowest 32-byte aligned address represented +by addr, in blocks of 32 bytes until at least size bytes have been cleaned and +invalidated.

      +

      impl SCB
      [src]

      Set the SLEEPDEEP bit in the SCR register

      +

      Clear the SLEEPDEEP bit in the SCR register

      +

      impl SCB
      [src]

      Initiate a system reset request to reset the MCU

      +

      impl SCB
      [src]

      Returns a pointer to the register block

      +

      Trait Implementations

      impl Send for SCB
      [src]

      impl Deref for SCB
      [src]

      +

      The resulting type after dereferencing.

      +

      Dereferences the value.

      +

      Auto Trait Implementations

      impl !Sync for SCB

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/struct.SYST.html b/cortex_m/peripheral/struct.SYST.html new file mode 100644 index 0000000..43206f9 --- /dev/null +++ b/cortex_m/peripheral/struct.SYST.html @@ -0,0 +1,60 @@ +cortex_m::peripheral::SYST - Rust

      [−][src]Struct cortex_m::peripheral::SYST

      pub struct SYST { /* fields omitted */ }

      SysTick: System Timer

      +

      Methods

      impl SYST
      [src]

      Clears current value to 0

      +

      After calling clear_current(), the next call to has_wrapped() will return false.

      +

      Disables counter

      +

      Disables SysTick interrupt

      +

      Enables counter

      +

      NOTE The reference manual indicates that:

      +

      "The SysTick counter reload and current value are undefined at reset, the correct +initialization sequence for the SysTick counter is:

      +
        +
      • Program reload value
        • +
      • Clear current value
        • +
      • Program Control and Status register"
        • +
      +

      The sequence translates to self.set_reload(x); self.clear_current(); self.enable_counter()

      +

      Enables SysTick interrupt

      +

      Gets clock source

      +

      NOTE This takes &mut self because the read operation is side effectful and can clear the +bit that indicates that the timer has wrapped (cf. SYST.has_wrapped)

      +

      Gets current value

      +

      Gets reload value

      +

      Returns the reload value with which the counter would wrap once per 10 +ms

      +

      Returns 0 if the value is not known (e.g. because the clock can +change dynamically).

      +

      Checks if an external reference clock is available

      +

      Checks if the counter wrapped (underflowed) since the last check

      +

      NOTE This takes &mut self because the read operation is side effectful and will clear +the bit of the read register.

      +

      Checks if counter is enabled

      +

      NOTE This takes &mut self because the read operation is side effectful and can clear the +bit that indicates that the timer has wrapped (cf. SYST.has_wrapped)

      +

      Checks if SysTick interrupt is enabled

      +

      NOTE This takes &mut self because the read operation is side effectful and can clear the +bit that indicates that the timer has wrapped (cf. SYST.has_wrapped)

      +

      Checks if the calibration value is precise

      +

      Returns false if using the reload value returned by +get_ticks_per_10ms() may result in a period significantly deviating +from 10 ms.

      +

      Sets clock source

      +

      Sets reload value

      +

      Valid values are between 1 and 0x00ffffff.

      +

      NOTE To make the timer wrap every N ticks set the reload value to N - 1

      +

      impl SYST
      [src]

      Returns a pointer to the register block

      +

      Trait Implementations

      impl Send for SYST
      [src]

      impl Deref for SYST
      [src]

      +

      The resulting type after dereferencing.

      +

      Dereferences the value.

      +

      Auto Trait Implementations

      impl !Sync for SYST

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/struct.TPIU.html b/cortex_m/peripheral/struct.TPIU.html new file mode 100644 index 0000000..8c46eef --- /dev/null +++ b/cortex_m/peripheral/struct.TPIU.html @@ -0,0 +1,18 @@ +cortex_m::peripheral::TPIU - Rust

      [−][src]Struct cortex_m::peripheral::TPIU

      pub struct TPIU { /* fields omitted */ }

      Trace Port Interface Unit

      +

      Methods

      impl TPIU
      [src]

      Returns a pointer to the register block

      +

      Trait Implementations

      impl Send for TPIU
      [src]

      impl Deref for TPIU
      [src]

      +

      The resulting type after dereferencing.

      +

      Dereferences the value.

      +

      Auto Trait Implementations

      impl !Sync for TPIU

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/syst/RegisterBlock.t.html b/cortex_m/peripheral/syst/RegisterBlock.t.html new file mode 100644 index 0000000..95870c5 --- /dev/null +++ b/cortex_m/peripheral/syst/RegisterBlock.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.RegisterBlock.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/syst/SystClkSource.t.html b/cortex_m/peripheral/syst/SystClkSource.t.html new file mode 100644 index 0000000..74b40f8 --- /dev/null +++ b/cortex_m/peripheral/syst/SystClkSource.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to enum.SystClkSource.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/syst/enum.SystClkSource.html b/cortex_m/peripheral/syst/enum.SystClkSource.html new file mode 100644 index 0000000..07e3098 --- /dev/null +++ b/cortex_m/peripheral/syst/enum.SystClkSource.html @@ -0,0 +1,24 @@ +cortex_m::peripheral::syst::SystClkSource - Rust

      [−][src]Enum cortex_m::peripheral::syst::SystClkSource

      pub enum SystClkSource {
+    Core,
+    External,
+}

      SysTick clock source

      +

      + Variants

      +

      Core-provided clock

      +

      External reference clock

      +

      Trait Implementations

      impl Clone for SystClkSource
      [src]

      Returns a copy of the value. Read more

      +

      Performs copy-assignment from source. Read more

      +

      impl Copy for SystClkSource
      [src]

      impl Debug for SystClkSource
      [src]

      Formats the value using the given formatter. Read more

      +

      Auto Trait Implementations

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/syst/index.html b/cortex_m/peripheral/syst/index.html new file mode 100644 index 0000000..212da1f --- /dev/null +++ b/cortex_m/peripheral/syst/index.html @@ -0,0 +1,20 @@ +cortex_m::peripheral::syst - Rust

      [−][src]Module cortex_m::peripheral::syst

      SysTick: System Timer

      +

      Structs

      + + + + +
      RegisterBlock +

      Register block

      + +

      Enums

      + + + + +
      SystClkSource +

      SysTick clock source

      + +
      \ No newline at end of file diff --git a/cortex_m/peripheral/syst/sidebar-items.js b/cortex_m/peripheral/syst/sidebar-items.js new file mode 100644 index 0000000..34035cd --- /dev/null +++ b/cortex_m/peripheral/syst/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"enum":[["SystClkSource","SysTick clock source"]],"struct":[["RegisterBlock","Register block"]]}); \ No newline at end of file diff --git a/cortex_m/peripheral/syst/struct.RegisterBlock.html b/cortex_m/peripheral/syst/struct.RegisterBlock.html new file mode 100644 index 0000000..78b9b8e --- /dev/null +++ b/cortex_m/peripheral/syst/struct.RegisterBlock.html @@ -0,0 +1,41 @@ +cortex_m::peripheral::syst::RegisterBlock - Rust

      [−][src]Struct cortex_m::peripheral::syst::RegisterBlock

      #[repr(C)]
+
      pub struct RegisterBlock {
+    pub csr: RW<u32>,
+    pub rvr: RW<u32>,
+    pub cvr: RW<u32>,
+    pub calib: RO<u32>,
+}

      Register block

      +

      + Fields

      + +

      Control and Status

      +
      + +

      Reload Value

      +
      + +

      Current Value

      +
      + +

      Calibration Value

      +

      Auto Trait Implementations

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/peripheral/tpiu/RegisterBlock.t.html b/cortex_m/peripheral/tpiu/RegisterBlock.t.html new file mode 100644 index 0000000..95870c5 --- /dev/null +++ b/cortex_m/peripheral/tpiu/RegisterBlock.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.RegisterBlock.html...

      + + + \ No newline at end of file diff --git a/cortex_m/peripheral/tpiu/index.html b/cortex_m/peripheral/tpiu/index.html new file mode 100644 index 0000000..c46a076 --- /dev/null +++ b/cortex_m/peripheral/tpiu/index.html @@ -0,0 +1,12 @@ +cortex_m::peripheral::tpiu - Rust

      [−][src]Module cortex_m::peripheral::tpiu

      Trace Port Interface Unit;

      +

      NOTE Available only on ARMv7-M (thumbv7*m-none-eabi*)

      +

      Structs

      + + + + +
      RegisterBlock +

      Register block

      + +
      \ No newline at end of file diff --git a/cortex_m/peripheral/tpiu/sidebar-items.js b/cortex_m/peripheral/tpiu/sidebar-items.js new file mode 100644 index 0000000..9e664d0 --- /dev/null +++ b/cortex_m/peripheral/tpiu/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"struct":[["RegisterBlock","Register block"]]}); \ No newline at end of file diff --git a/cortex_m/peripheral/tpiu/struct.RegisterBlock.html b/cortex_m/peripheral/tpiu/struct.RegisterBlock.html new file mode 100644 index 0000000..78e05ca --- /dev/null +++ b/cortex_m/peripheral/tpiu/struct.RegisterBlock.html @@ -0,0 +1,66 @@ +cortex_m::peripheral::tpiu::RegisterBlock - Rust

      [−][src]Struct cortex_m::peripheral::tpiu::RegisterBlock

      #[repr(C)]
+
      pub struct RegisterBlock {
+    pub sspsr: RO<u32>,
+    pub cspsr: RW<u32>,
+    pub acpr: RW<u32>,
+    pub sppr: RW<u32>,
+    pub ffcr: RW<u32>,
+    pub lar: WO<u32>,
+    pub lsr: RO<u32>,
+    pub _type: RO<u32>,
+    // some fields omitted
+}

      Register block

      +

      + Fields

      + +

      Supported Parallel Port Sizes

      +
      + +

      Current Parallel Port Size

      +
      + +

      Asynchronous Clock Prescaler

      +
      + +

      Selected Pin Control

      +
      + +

      Formatter and Flush Control

      +
      + +

      Lock Access

      +
      + +

      Lock Status

      +
      + +

      TPIU Type

      +

      Auto Trait Implementations

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/register/apsr/Apsr.t.html b/cortex_m/register/apsr/Apsr.t.html new file mode 100644 index 0000000..623de99 --- /dev/null +++ b/cortex_m/register/apsr/Apsr.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.Apsr.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/apsr/fn.read.html b/cortex_m/register/apsr/fn.read.html new file mode 100644 index 0000000..aa6036d --- /dev/null +++ b/cortex_m/register/apsr/fn.read.html @@ -0,0 +1,3 @@ +cortex_m::register::apsr::read - Rust

      [−][src]Function cortex_m::register::apsr::read

      pub fn read() -> Apsr

      Reads the CPU register

      +

      NOTE This function is available if cortex-m is built with the "inline-asm" feature.

      +
      \ No newline at end of file diff --git a/cortex_m/register/apsr/index.html b/cortex_m/register/apsr/index.html new file mode 100644 index 0000000..568ab26 --- /dev/null +++ b/cortex_m/register/apsr/index.html @@ -0,0 +1,20 @@ +cortex_m::register::apsr - Rust

      [−][src]Module cortex_m::register::apsr

      Application Program Status Register

      +

      Structs

      + + + + +
      Apsr +

      Application Program Status Register

      + +

      Functions

      + + + + +
      read +

      Reads the CPU register

      + +
      \ No newline at end of file diff --git a/cortex_m/register/apsr/read.v.html b/cortex_m/register/apsr/read.v.html new file mode 100644 index 0000000..63c2ad7 --- /dev/null +++ b/cortex_m/register/apsr/read.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.read.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/apsr/sidebar-items.js b/cortex_m/register/apsr/sidebar-items.js new file mode 100644 index 0000000..69e3c8e --- /dev/null +++ b/cortex_m/register/apsr/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"fn":[["read","Reads the CPU register"]],"struct":[["Apsr","Application Program Status Register"]]}); \ No newline at end of file diff --git a/cortex_m/register/apsr/struct.Apsr.html b/cortex_m/register/apsr/struct.Apsr.html new file mode 100644 index 0000000..02929b3 --- /dev/null +++ b/cortex_m/register/apsr/struct.Apsr.html @@ -0,0 +1,23 @@ +cortex_m::register::apsr::Apsr - Rust

      [−][src]Struct cortex_m::register::apsr::Apsr

      pub struct Apsr { /* fields omitted */ }

      Application Program Status Register

      +

      Methods

      impl Apsr
      [src]

      Returns the contents of the register as raw bits

      +

      DSP overflow and saturation flag

      +

      Overflow flag

      +

      Carry or borrow flag

      +

      Zero flag

      +

      Negative flag

      +

      Trait Implementations

      impl Clone for Apsr
      [src]

      Returns a copy of the value. Read more

      +

      Performs copy-assignment from source. Read more

      +

      impl Copy for Apsr
      [src]

      impl Debug for Apsr
      [src]

      Formats the value using the given formatter. Read more

      +

      Auto Trait Implementations

      impl Send for Apsr

      impl Sync for Apsr

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/register/basepri/fn.read.html b/cortex_m/register/basepri/fn.read.html new file mode 100644 index 0000000..9e0e873 --- /dev/null +++ b/cortex_m/register/basepri/fn.read.html @@ -0,0 +1,2 @@ +cortex_m::register::basepri::read - Rust

      [−][src]Function cortex_m::register::basepri::read

      pub fn read() -> u8

      Reads the CPU register

      +
      \ No newline at end of file diff --git a/cortex_m/register/basepri/fn.write.html b/cortex_m/register/basepri/fn.write.html new file mode 100644 index 0000000..2d9aba4 --- /dev/null +++ b/cortex_m/register/basepri/fn.write.html @@ -0,0 +1,4 @@ +cortex_m::register::basepri::write - Rust

      [−][src]Function cortex_m::register::basepri::write

      pub unsafe fn write(_basepri: u8)

      Writes to the CPU register

      +

      IMPORTANT If you are using a Cortex-M7 device with revision r0p1 you MUST enable the +cm7-r0p1 Cargo feature or this function WILL misbehave.

      +
      \ No newline at end of file diff --git a/cortex_m/register/basepri/index.html b/cortex_m/register/basepri/index.html new file mode 100644 index 0000000..6e53421 --- /dev/null +++ b/cortex_m/register/basepri/index.html @@ -0,0 +1,19 @@ +cortex_m::register::basepri - Rust

      [−][src]Module cortex_m::register::basepri

      Base Priority Mask Register

      +

      Functions

      + + + + + + + + +
      read +

      Reads the CPU register

      + +
      write⚠ +

      Writes to the CPU register

      + +
      \ No newline at end of file diff --git a/cortex_m/register/basepri/read.v.html b/cortex_m/register/basepri/read.v.html new file mode 100644 index 0000000..63c2ad7 --- /dev/null +++ b/cortex_m/register/basepri/read.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.read.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/basepri/sidebar-items.js b/cortex_m/register/basepri/sidebar-items.js new file mode 100644 index 0000000..ae04947 --- /dev/null +++ b/cortex_m/register/basepri/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"fn":[["read","Reads the CPU register"],["write","Writes to the CPU register"]]}); \ No newline at end of file diff --git a/cortex_m/register/basepri/write.v.html b/cortex_m/register/basepri/write.v.html new file mode 100644 index 0000000..93ddfc2 --- /dev/null +++ b/cortex_m/register/basepri/write.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.write.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/basepri_max/fn.write.html b/cortex_m/register/basepri_max/fn.write.html new file mode 100644 index 0000000..7b7038f --- /dev/null +++ b/cortex_m/register/basepri_max/fn.write.html @@ -0,0 +1,8 @@ +cortex_m::register::basepri_max::write - Rust

      [−][src]Function cortex_m::register::basepri_max::write

      pub fn write(_basepri: u8)

      Writes to BASEPRI if

      +
        +
      • basepri != 0 AND basepri::read() == 0, OR
        • +
      • basepri != 0 AND basepri < basepri::read()
        • +
      +

      IMPORTANT If you are using a Cortex-M7 device with revision r0p1 you MUST enable the +cm7-r0p1 Cargo feature or this function WILL misbehave.

      +
      \ No newline at end of file diff --git a/cortex_m/register/basepri_max/index.html b/cortex_m/register/basepri_max/index.html new file mode 100644 index 0000000..3660d92 --- /dev/null +++ b/cortex_m/register/basepri_max/index.html @@ -0,0 +1,11 @@ +cortex_m::register::basepri_max - Rust

      [−][src]Module cortex_m::register::basepri_max

      Base Priority Mask Register (conditional write)

      +

      Functions

      + + + + +
      write +

      Writes to BASEPRI if

      + +
      \ No newline at end of file diff --git a/cortex_m/register/basepri_max/sidebar-items.js b/cortex_m/register/basepri_max/sidebar-items.js new file mode 100644 index 0000000..6d735ff --- /dev/null +++ b/cortex_m/register/basepri_max/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"fn":[["write","Writes to BASEPRI if"]]}); \ No newline at end of file diff --git a/cortex_m/register/basepri_max/write.v.html b/cortex_m/register/basepri_max/write.v.html new file mode 100644 index 0000000..93ddfc2 --- /dev/null +++ b/cortex_m/register/basepri_max/write.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.write.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/control/Control.t.html b/cortex_m/register/control/Control.t.html new file mode 100644 index 0000000..dbcfb1e --- /dev/null +++ b/cortex_m/register/control/Control.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.Control.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/control/Fpca.t.html b/cortex_m/register/control/Fpca.t.html new file mode 100644 index 0000000..3448163 --- /dev/null +++ b/cortex_m/register/control/Fpca.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to enum.Fpca.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/control/Npriv.t.html b/cortex_m/register/control/Npriv.t.html new file mode 100644 index 0000000..ddb3e60 --- /dev/null +++ b/cortex_m/register/control/Npriv.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to enum.Npriv.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/control/Spsel.t.html b/cortex_m/register/control/Spsel.t.html new file mode 100644 index 0000000..63db005 --- /dev/null +++ b/cortex_m/register/control/Spsel.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to enum.Spsel.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/control/enum.Fpca.html b/cortex_m/register/control/enum.Fpca.html new file mode 100644 index 0000000..862339c --- /dev/null +++ b/cortex_m/register/control/enum.Fpca.html @@ -0,0 +1,29 @@ +cortex_m::register::control::Fpca - Rust

      [−][src]Enum cortex_m::register::control::Fpca

      pub enum Fpca {
+    Active,
+    NotActive,
+}

      Whether context floating-point is currently active

      +

      + Variants

      +

      Floating-point context active.

      +

      No floating-point context active

      +

      Methods

      impl Fpca
      [src]

      Is a floating-point context active?

      +

      Is a floating-point context not active?

      +

      Trait Implementations

      impl Clone for Fpca
      [src]

      Returns a copy of the value. Read more

      +

      Performs copy-assignment from source. Read more

      +

      impl Copy for Fpca
      [src]

      impl Debug for Fpca
      [src]

      Formats the value using the given formatter. Read more

      +

      impl Eq for Fpca
      [src]

      impl PartialEq for Fpca
      [src]

      This method tests for self and other values to be equal, and is used by ==. Read more

      +

      This method tests for !=.

      +

      Auto Trait Implementations

      impl Send for Fpca

      impl Sync for Fpca

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/register/control/enum.Npriv.html b/cortex_m/register/control/enum.Npriv.html new file mode 100644 index 0000000..baf42b5 --- /dev/null +++ b/cortex_m/register/control/enum.Npriv.html @@ -0,0 +1,29 @@ +cortex_m::register::control::Npriv - Rust

      [−][src]Enum cortex_m::register::control::Npriv

      pub enum Npriv {
+    Privileged,
+    Unprivileged,
+}

      Thread mode privilege level

      +

      + Variants

      +

      Privileged

      +

      Unprivileged

      +

      Methods

      impl Npriv
      [src]

      Is in privileged thread mode?

      +

      Is in unprivileged thread mode?

      +

      Trait Implementations

      impl Clone for Npriv
      [src]

      Returns a copy of the value. Read more

      +

      Performs copy-assignment from source. Read more

      +

      impl Copy for Npriv
      [src]

      impl Debug for Npriv
      [src]

      Formats the value using the given formatter. Read more

      +

      impl Eq for Npriv
      [src]

      impl PartialEq for Npriv
      [src]

      This method tests for self and other values to be equal, and is used by ==. Read more

      +

      This method tests for !=.

      +

      Auto Trait Implementations

      impl Send for Npriv

      impl Sync for Npriv

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/register/control/enum.Spsel.html b/cortex_m/register/control/enum.Spsel.html new file mode 100644 index 0000000..9245d17 --- /dev/null +++ b/cortex_m/register/control/enum.Spsel.html @@ -0,0 +1,29 @@ +cortex_m::register::control::Spsel - Rust

      [−][src]Enum cortex_m::register::control::Spsel

      pub enum Spsel {
+    Msp,
+    Psp,
+}

      Currently active stack pointer

      +

      + Variants

      +

      MSP is the current stack pointer

      +

      PSP is the current stack pointer

      +

      Methods

      impl Spsel
      [src]

      Is MSP the current stack pointer?

      +

      Is PSP the current stack pointer?

      +

      Trait Implementations

      impl Clone for Spsel
      [src]

      Returns a copy of the value. Read more

      +

      Performs copy-assignment from source. Read more

      +

      impl Copy for Spsel
      [src]

      impl Debug for Spsel
      [src]

      Formats the value using the given formatter. Read more

      +

      impl Eq for Spsel
      [src]

      impl PartialEq for Spsel
      [src]

      This method tests for self and other values to be equal, and is used by ==. Read more

      +

      This method tests for !=.

      +

      Auto Trait Implementations

      impl Send for Spsel

      impl Sync for Spsel

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/register/control/fn.read.html b/cortex_m/register/control/fn.read.html new file mode 100644 index 0000000..c8da41e --- /dev/null +++ b/cortex_m/register/control/fn.read.html @@ -0,0 +1,2 @@ +cortex_m::register::control::read - Rust

      [−][src]Function cortex_m::register::control::read

      pub fn read() -> Control

      Reads the CPU register

      +
      \ No newline at end of file diff --git a/cortex_m/register/control/index.html b/cortex_m/register/control/index.html new file mode 100644 index 0000000..3cb25d0 --- /dev/null +++ b/cortex_m/register/control/index.html @@ -0,0 +1,45 @@ +cortex_m::register::control - Rust

      [−][src]Module cortex_m::register::control

      Control register

      +

      Structs

      + + + + +
      Control +

      Control register

      + +

      Enums

      + + + + + + + + + + + + +
      Fpca +

      Whether context floating-point is currently active

      + +
      Npriv +

      Thread mode privilege level

      + +
      Spsel +

      Currently active stack pointer

      + +

      Functions

      + + + + +
      read +

      Reads the CPU register

      + +
      \ No newline at end of file diff --git a/cortex_m/register/control/read.v.html b/cortex_m/register/control/read.v.html new file mode 100644 index 0000000..63c2ad7 --- /dev/null +++ b/cortex_m/register/control/read.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.read.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/control/sidebar-items.js b/cortex_m/register/control/sidebar-items.js new file mode 100644 index 0000000..d0e7d2c --- /dev/null +++ b/cortex_m/register/control/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"enum":[["Fpca","Whether context floating-point is currently active"],["Npriv","Thread mode privilege level"],["Spsel","Currently active stack pointer"]],"fn":[["read","Reads the CPU register"]],"struct":[["Control","Control register"]]}); \ No newline at end of file diff --git a/cortex_m/register/control/struct.Control.html b/cortex_m/register/control/struct.Control.html new file mode 100644 index 0000000..d022645 --- /dev/null +++ b/cortex_m/register/control/struct.Control.html @@ -0,0 +1,21 @@ +cortex_m::register::control::Control - Rust

      [−][src]Struct cortex_m::register::control::Control

      pub struct Control { /* fields omitted */ }

      Control register

      +

      Methods

      impl Control
      [src]

      Returns the contents of the register as raw bits

      +

      Thread mode privilege level

      +

      Currently active stack pointer

      +

      Whether context floating-point is currently active

      +

      Trait Implementations

      impl Clone for Control
      [src]

      Returns a copy of the value. Read more

      +

      Performs copy-assignment from source. Read more

      +

      impl Copy for Control
      [src]

      impl Debug for Control
      [src]

      Formats the value using the given formatter. Read more

      +

      Auto Trait Implementations

      impl Send for Control

      impl Sync for Control

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/register/faultmask/Faultmask.t.html b/cortex_m/register/faultmask/Faultmask.t.html new file mode 100644 index 0000000..5b9707e --- /dev/null +++ b/cortex_m/register/faultmask/Faultmask.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to enum.Faultmask.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/faultmask/enum.Faultmask.html b/cortex_m/register/faultmask/enum.Faultmask.html new file mode 100644 index 0000000..769192a --- /dev/null +++ b/cortex_m/register/faultmask/enum.Faultmask.html @@ -0,0 +1,29 @@ +cortex_m::register::faultmask::Faultmask - Rust

      [−][src]Enum cortex_m::register::faultmask::Faultmask

      pub enum Faultmask {
+    Active,
+    Inactive,
+}

      All exceptions are ...

      +

      + Variants

      +

      Active

      +

      Inactive, expect for NMI

      +

      Methods

      impl Faultmask
      [src]

      All exceptions are active

      +

      All exceptions, except for NMI, are inactive

      +

      Trait Implementations

      impl Clone for Faultmask
      [src]

      Returns a copy of the value. Read more

      +

      Performs copy-assignment from source. Read more

      +

      impl Copy for Faultmask
      [src]

      impl Debug for Faultmask
      [src]

      Formats the value using the given formatter. Read more

      +

      impl Eq for Faultmask
      [src]

      impl PartialEq for Faultmask
      [src]

      This method tests for self and other values to be equal, and is used by ==. Read more

      +

      This method tests for !=.

      +

      Auto Trait Implementations

      impl Send for Faultmask

      impl Sync for Faultmask

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/register/faultmask/fn.read.html b/cortex_m/register/faultmask/fn.read.html new file mode 100644 index 0000000..8cd526d --- /dev/null +++ b/cortex_m/register/faultmask/fn.read.html @@ -0,0 +1,2 @@ +cortex_m::register::faultmask::read - Rust

      [−][src]Function cortex_m::register::faultmask::read

      pub fn read() -> Faultmask

      Reads the CPU register

      +
      \ No newline at end of file diff --git a/cortex_m/register/faultmask/index.html b/cortex_m/register/faultmask/index.html new file mode 100644 index 0000000..f20c410 --- /dev/null +++ b/cortex_m/register/faultmask/index.html @@ -0,0 +1,20 @@ +cortex_m::register::faultmask - Rust

      [−][src]Module cortex_m::register::faultmask

      Fault Mask Register

      +

      Enums

      + + + + +
      Faultmask +

      All exceptions are ...

      + +

      Functions

      + + + + +
      read +

      Reads the CPU register

      + +
      \ No newline at end of file diff --git a/cortex_m/register/faultmask/read.v.html b/cortex_m/register/faultmask/read.v.html new file mode 100644 index 0000000..63c2ad7 --- /dev/null +++ b/cortex_m/register/faultmask/read.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.read.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/faultmask/sidebar-items.js b/cortex_m/register/faultmask/sidebar-items.js new file mode 100644 index 0000000..0ed9352 --- /dev/null +++ b/cortex_m/register/faultmask/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"enum":[["Faultmask","All exceptions are ..."]],"fn":[["read","Reads the CPU register"]]}); \ No newline at end of file diff --git a/cortex_m/register/index.html b/cortex_m/register/index.html new file mode 100644 index 0000000..c68c49f --- /dev/null +++ b/cortex_m/register/index.html @@ -0,0 +1,109 @@ +cortex_m::register - Rust

      [−][src]Module cortex_m::register

      Processor core registers

      +

      The following registers can only be accessed in PRIVILEGED mode:

      +
        +
      • BASEPRI
        • +
      • CONTROL
        • +
      • FAULTMASK
        • +
      • MSP
        • +
      • PRIMASK
        • +
      +

      The rest of registers (see list below) can be accessed in either, PRIVILEGED +or UNPRIVILEGED, mode.

      +
        +
      • APSR
        • +
      • LR
        • +
      • PC
        • +
      • PSP
        • +
      +

      The following registers are NOT available on ARMv6-M devices +(thumbv6m-none-eabi):

      +
        +
      • BASEPRI
        • +
      • FAULTMASK
        • +
      +

      References

      +
        +
      • Cortex-M* Devices Generic User Guide - Section 2.1.3 Core registers
        • +
      +

      Modules

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      apsr +

      Application Program Status Register

      + +
      basepri +

      Base Priority Mask Register

      + +
      basepri_max +

      Base Priority Mask Register (conditional write)

      + +
      control +

      Control register

      + +
      faultmask +

      Fault Mask Register

      + +
      lr +

      Link register

      + +
      msp +

      Main Stack Pointer

      + +
      pc +

      Program counter

      + +
      primask +

      Priority mask register

      + +
      psp +

      Process Stack Pointer

      + +
      \ No newline at end of file diff --git a/cortex_m/register/lr/fn.read.html b/cortex_m/register/lr/fn.read.html new file mode 100644 index 0000000..9b85246 --- /dev/null +++ b/cortex_m/register/lr/fn.read.html @@ -0,0 +1,3 @@ +cortex_m::register::lr::read - Rust

      [−][src]Function cortex_m::register::lr::read

      pub fn read() -> u32

      Reads the CPU register

      +

      NOTE This function is available if cortex-m is built with the "inline-asm" feature.

      +
      \ No newline at end of file diff --git a/cortex_m/register/lr/fn.write.html b/cortex_m/register/lr/fn.write.html new file mode 100644 index 0000000..7897be4 --- /dev/null +++ b/cortex_m/register/lr/fn.write.html @@ -0,0 +1,3 @@ +cortex_m::register::lr::write - Rust

      [−][src]Function cortex_m::register::lr::write

      pub unsafe fn write(_bits: u32)

      Writes bits to the CPU register

      +

      NOTE This function is available if cortex-m is built with the "inline-asm" feature.

      +
      \ No newline at end of file diff --git a/cortex_m/register/lr/index.html b/cortex_m/register/lr/index.html new file mode 100644 index 0000000..0537d24 --- /dev/null +++ b/cortex_m/register/lr/index.html @@ -0,0 +1,19 @@ +cortex_m::register::lr - Rust

      [−][src]Module cortex_m::register::lr

      Link register

      +

      Functions

      + + + + + + + + +
      read +

      Reads the CPU register

      + +
      write⚠ +

      Writes bits to the CPU register

      + +
      \ No newline at end of file diff --git a/cortex_m/register/lr/read.v.html b/cortex_m/register/lr/read.v.html new file mode 100644 index 0000000..63c2ad7 --- /dev/null +++ b/cortex_m/register/lr/read.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.read.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/lr/sidebar-items.js b/cortex_m/register/lr/sidebar-items.js new file mode 100644 index 0000000..e42ae2c --- /dev/null +++ b/cortex_m/register/lr/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"fn":[["read","Reads the CPU register"],["write","Writes `bits` to the CPU register"]]}); \ No newline at end of file diff --git a/cortex_m/register/lr/write.v.html b/cortex_m/register/lr/write.v.html new file mode 100644 index 0000000..93ddfc2 --- /dev/null +++ b/cortex_m/register/lr/write.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.write.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/msp/fn.read.html b/cortex_m/register/msp/fn.read.html new file mode 100644 index 0000000..f280fe0 --- /dev/null +++ b/cortex_m/register/msp/fn.read.html @@ -0,0 +1,2 @@ +cortex_m::register::msp::read - Rust

      [−][src]Function cortex_m::register::msp::read

      pub fn read() -> u32

      Reads the CPU register

      +
      \ No newline at end of file diff --git a/cortex_m/register/msp/fn.write.html b/cortex_m/register/msp/fn.write.html new file mode 100644 index 0000000..14610de --- /dev/null +++ b/cortex_m/register/msp/fn.write.html @@ -0,0 +1,2 @@ +cortex_m::register::msp::write - Rust

      [−][src]Function cortex_m::register::msp::write

      pub unsafe fn write(_bits: u32)

      Writes bits to the CPU register

      +
      \ No newline at end of file diff --git a/cortex_m/register/msp/index.html b/cortex_m/register/msp/index.html new file mode 100644 index 0000000..597feff --- /dev/null +++ b/cortex_m/register/msp/index.html @@ -0,0 +1,19 @@ +cortex_m::register::msp - Rust

      [−][src]Module cortex_m::register::msp

      Main Stack Pointer

      +

      Functions

      + + + + + + + + +
      read +

      Reads the CPU register

      + +
      write⚠ +

      Writes bits to the CPU register

      + +
      \ No newline at end of file diff --git a/cortex_m/register/msp/read.v.html b/cortex_m/register/msp/read.v.html new file mode 100644 index 0000000..63c2ad7 --- /dev/null +++ b/cortex_m/register/msp/read.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.read.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/msp/sidebar-items.js b/cortex_m/register/msp/sidebar-items.js new file mode 100644 index 0000000..e42ae2c --- /dev/null +++ b/cortex_m/register/msp/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"fn":[["read","Reads the CPU register"],["write","Writes `bits` to the CPU register"]]}); \ No newline at end of file diff --git a/cortex_m/register/msp/write.v.html b/cortex_m/register/msp/write.v.html new file mode 100644 index 0000000..93ddfc2 --- /dev/null +++ b/cortex_m/register/msp/write.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.write.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/pc/fn.read.html b/cortex_m/register/pc/fn.read.html new file mode 100644 index 0000000..0b736ca --- /dev/null +++ b/cortex_m/register/pc/fn.read.html @@ -0,0 +1,3 @@ +cortex_m::register::pc::read - Rust

      [−][src]Function cortex_m::register::pc::read

      pub fn read() -> u32

      Reads the CPU register

      +

      NOTE This function is available if cortex-m is built with the "inline-asm" feature.

      +
      \ No newline at end of file diff --git a/cortex_m/register/pc/fn.write.html b/cortex_m/register/pc/fn.write.html new file mode 100644 index 0000000..4992578 --- /dev/null +++ b/cortex_m/register/pc/fn.write.html @@ -0,0 +1,3 @@ +cortex_m::register::pc::write - Rust

      [−][src]Function cortex_m::register::pc::write

      pub unsafe fn write(_bits: u32)

      Writes bits to the CPU register

      +

      NOTE This function is available if cortex-m is built with the "inline-asm" feature.

      +
      \ No newline at end of file diff --git a/cortex_m/register/pc/index.html b/cortex_m/register/pc/index.html new file mode 100644 index 0000000..f9b0738 --- /dev/null +++ b/cortex_m/register/pc/index.html @@ -0,0 +1,19 @@ +cortex_m::register::pc - Rust

      [−][src]Module cortex_m::register::pc

      Program counter

      +

      Functions

      + + + + + + + + +
      read +

      Reads the CPU register

      + +
      write⚠ +

      Writes bits to the CPU register

      + +
      \ No newline at end of file diff --git a/cortex_m/register/pc/read.v.html b/cortex_m/register/pc/read.v.html new file mode 100644 index 0000000..63c2ad7 --- /dev/null +++ b/cortex_m/register/pc/read.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.read.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/pc/sidebar-items.js b/cortex_m/register/pc/sidebar-items.js new file mode 100644 index 0000000..e42ae2c --- /dev/null +++ b/cortex_m/register/pc/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"fn":[["read","Reads the CPU register"],["write","Writes `bits` to the CPU register"]]}); \ No newline at end of file diff --git a/cortex_m/register/pc/write.v.html b/cortex_m/register/pc/write.v.html new file mode 100644 index 0000000..93ddfc2 --- /dev/null +++ b/cortex_m/register/pc/write.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.write.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/primask/Primask.t.html b/cortex_m/register/primask/Primask.t.html new file mode 100644 index 0000000..5448ff7 --- /dev/null +++ b/cortex_m/register/primask/Primask.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to enum.Primask.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/primask/enum.Primask.html b/cortex_m/register/primask/enum.Primask.html new file mode 100644 index 0000000..d2f7f8f --- /dev/null +++ b/cortex_m/register/primask/enum.Primask.html @@ -0,0 +1,29 @@ +cortex_m::register::primask::Primask - Rust

      [−][src]Enum cortex_m::register::primask::Primask

      pub enum Primask {
+    Active,
+    Inactive,
+}

      All exceptions with configurable priority are ...

      +

      + Variants

      +

      Active

      +

      Inactive

      +

      Methods

      impl Primask
      [src]

      All exceptions with configurable priority are active

      +

      All exceptions with configurable priority are inactive

      +

      Trait Implementations

      impl Clone for Primask
      [src]

      Returns a copy of the value. Read more

      +

      Performs copy-assignment from source. Read more

      +

      impl Copy for Primask
      [src]

      impl Debug for Primask
      [src]

      Formats the value using the given formatter. Read more

      +

      impl Eq for Primask
      [src]

      impl PartialEq for Primask
      [src]

      This method tests for self and other values to be equal, and is used by ==. Read more

      +

      This method tests for !=.

      +

      Auto Trait Implementations

      impl Send for Primask

      impl Sync for Primask

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m/register/primask/fn.read.html b/cortex_m/register/primask/fn.read.html new file mode 100644 index 0000000..c3513db --- /dev/null +++ b/cortex_m/register/primask/fn.read.html @@ -0,0 +1,2 @@ +cortex_m::register::primask::read - Rust

      [−][src]Function cortex_m::register::primask::read

      pub fn read() -> Primask

      Reads the CPU register

      +
      \ No newline at end of file diff --git a/cortex_m/register/primask/index.html b/cortex_m/register/primask/index.html new file mode 100644 index 0000000..4e89d28 --- /dev/null +++ b/cortex_m/register/primask/index.html @@ -0,0 +1,20 @@ +cortex_m::register::primask - Rust

      [−][src]Module cortex_m::register::primask

      Priority mask register

      +

      Enums

      + + + + +
      Primask +

      All exceptions with configurable priority are ...

      + +

      Functions

      + + + + +
      read +

      Reads the CPU register

      + +
      \ No newline at end of file diff --git a/cortex_m/register/primask/read.v.html b/cortex_m/register/primask/read.v.html new file mode 100644 index 0000000..63c2ad7 --- /dev/null +++ b/cortex_m/register/primask/read.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.read.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/primask/sidebar-items.js b/cortex_m/register/primask/sidebar-items.js new file mode 100644 index 0000000..a6ea15b --- /dev/null +++ b/cortex_m/register/primask/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"enum":[["Primask","All exceptions with configurable priority are ..."]],"fn":[["read","Reads the CPU register"]]}); \ No newline at end of file diff --git a/cortex_m/register/psp/fn.read.html b/cortex_m/register/psp/fn.read.html new file mode 100644 index 0000000..2ad6d9d --- /dev/null +++ b/cortex_m/register/psp/fn.read.html @@ -0,0 +1,2 @@ +cortex_m::register::psp::read - Rust

      [−][src]Function cortex_m::register::psp::read

      pub fn read() -> u32

      Reads the CPU register

      +
      \ No newline at end of file diff --git a/cortex_m/register/psp/fn.write.html b/cortex_m/register/psp/fn.write.html new file mode 100644 index 0000000..6540d53 --- /dev/null +++ b/cortex_m/register/psp/fn.write.html @@ -0,0 +1,2 @@ +cortex_m::register::psp::write - Rust

      [−][src]Function cortex_m::register::psp::write

      pub unsafe fn write(_bits: u32)

      Writes bits to the CPU register

      +
      \ No newline at end of file diff --git a/cortex_m/register/psp/index.html b/cortex_m/register/psp/index.html new file mode 100644 index 0000000..530f0f0 --- /dev/null +++ b/cortex_m/register/psp/index.html @@ -0,0 +1,19 @@ +cortex_m::register::psp - Rust

      [−][src]Module cortex_m::register::psp

      Process Stack Pointer

      +

      Functions

      + + + + + + + + +
      read +

      Reads the CPU register

      + +
      write⚠ +

      Writes bits to the CPU register

      + +
      \ No newline at end of file diff --git a/cortex_m/register/psp/read.v.html b/cortex_m/register/psp/read.v.html new file mode 100644 index 0000000..63c2ad7 --- /dev/null +++ b/cortex_m/register/psp/read.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.read.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/psp/sidebar-items.js b/cortex_m/register/psp/sidebar-items.js new file mode 100644 index 0000000..e42ae2c --- /dev/null +++ b/cortex_m/register/psp/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"fn":[["read","Reads the CPU register"],["write","Writes `bits` to the CPU register"]]}); \ No newline at end of file diff --git a/cortex_m/register/psp/write.v.html b/cortex_m/register/psp/write.v.html new file mode 100644 index 0000000..93ddfc2 --- /dev/null +++ b/cortex_m/register/psp/write.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.write.html...

      + + + \ No newline at end of file diff --git a/cortex_m/register/sidebar-items.js b/cortex_m/register/sidebar-items.js new file mode 100644 index 0000000..97c8fed --- /dev/null +++ b/cortex_m/register/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"mod":[["apsr","Application Program Status Register"],["basepri","Base Priority Mask Register"],["basepri_max","Base Priority Mask Register (conditional write)"],["control","Control register"],["faultmask","Fault Mask Register"],["lr","Link register"],["msp","Main Stack Pointer"],["pc","Program counter"],["primask","Priority mask register"],["psp","Process Stack Pointer"]]}); \ No newline at end of file diff --git a/cortex_m/sidebar-items.js b/cortex_m/sidebar-items.js new file mode 100644 index 0000000..54b96f2 --- /dev/null +++ b/cortex_m/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"macro":[["iprint","Macro for sending a formatted string through an ITM channel"],["iprintln","Macro for sending a formatted string through an ITM channel, with a newline."],["singleton","Macro to create a mutable reference to a statically allocated value"]],"mod":[["asm","Miscellaneous assembly instructions"],["interrupt","Interrupts"],["itm","Instrumentation Trace Macrocell"],["peripheral","Core peripherals"],["register","Processor core registers"]]}); \ No newline at end of file diff --git a/cortex_m/singleton.m.html b/cortex_m/singleton.m.html new file mode 100644 index 0000000..67106d0 --- /dev/null +++ b/cortex_m/singleton.m.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.singleton.html...

      + + + \ No newline at end of file diff --git a/cortex_m_quickstart/all.html b/cortex_m_quickstart/all.html new file mode 100644 index 0000000..5ccc9f1 --- /dev/null +++ b/cortex_m_quickstart/all.html @@ -0,0 +1,3 @@ +List of all items in this crate

      [−] + + List of all items

      \ No newline at end of file diff --git a/cortex_m_quickstart/examples/_0_minimal/index.html b/cortex_m_quickstart/examples/_0_minimal/index.html new file mode 100644 index 0000000..be53c21 --- /dev/null +++ b/cortex_m_quickstart/examples/_0_minimal/index.html @@ -0,0 +1,65 @@ +cortex_m_quickstart::examples::_0_minimal - Rust

      [−][src]Module cortex_m_quickstart::examples::_0_minimal

      Minimal Cortex-M program

      +

      When executed this program will hit the breakpoint set in main.

      +

      All Cortex-M programs need to:

      +
        +
      • +

        Contain the #![no_main] and #![no_std] attributes. Embedded programs don't use the +standard Rust main interface or the Rust standard (std) library.

        +
        • +
      • +

        Define their entry point using entry! macro.

        +
        • +
      +
        +
      • Define their panicking behavior, i.e. what happens when panic! is called. The easiest way to +define a panicking behavior is to link to a panic handler crate
        • +
      +
        +
      • Define the HardFault handler using the exception! macro. This handler (function) is +called when a hard fault exception is raised by the hardware.
        • +
      +
        +
      • Define a default handler using the exception! macro. This function will be used to handle +all interrupts and exceptions which have not been assigned a specific handler.
        • +
      + +
      +
+#![no_main] // <- IMPORTANT!
+#![no_std]
+
+extern crate cortex_m;
+
+#[macro_use(entry, exception)]
+extern crate cortex_m_rt as rt;
+
+// makes `panic!` print messages to the host stderr using semihosting
+extern crate panic_semihosting;
+
+use cortex_m::asm;
+use rt::ExceptionFrame;
+
+// the program entry point is ...
+entry!(main);
+
+// ... this never ending function
+fn main() -> ! {
+    loop {
+        asm::bkpt();
+    }
+}
+
+// define the hard fault handler
+exception!(HardFault, hard_fault);
+
+fn hard_fault(ef: &ExceptionFrame) -> ! {
+    panic!("HardFault at {:#?}", ef);
+}
+
+// define the default exception handler
+exception!(*, default_handler);
+
+fn default_handler(irqn: i16) {
+    panic!("Unhandled exception (IRQn = {})", irqn);
+}
      +
      \ No newline at end of file diff --git a/cortex_m_quickstart/examples/_0_minimal/sidebar-items.js b/cortex_m_quickstart/examples/_0_minimal/sidebar-items.js new file mode 100644 index 0000000..48333d3 --- /dev/null +++ b/cortex_m_quickstart/examples/_0_minimal/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({}); \ No newline at end of file diff --git a/cortex_m_quickstart/examples/_1_hello/index.html b/cortex_m_quickstart/examples/_1_hello/index.html new file mode 100644 index 0000000..deba466 --- /dev/null +++ b/cortex_m_quickstart/examples/_1_hello/index.html @@ -0,0 +1,39 @@ +cortex_m_quickstart::examples::_1_hello - Rust

      [−][src]Module cortex_m_quickstart::examples::_1_hello

      Prints "Hello, world!" on the OpenOCD console using semihosting

      +
      + +
      +
+#![no_main]
+#![no_std]
+
+#[macro_use]
+extern crate cortex_m_rt as rt;
+extern crate cortex_m_semihosting as sh;
+extern crate panic_semihosting;
+
+use core::fmt::Write;
+
+use rt::ExceptionFrame;
+use sh::hio;
+
+entry!(main);
+
+fn main() -> ! {
+    let mut stdout = hio::hstdout().unwrap();
+    writeln!(stdout, "Hello, world!").unwrap();
+
+    loop {}
+}
+
+exception!(HardFault, hard_fault);
+
+fn hard_fault(ef: &ExceptionFrame) -> ! {
+    panic!("HardFault at {:#?}", ef);
+}
+
+exception!(*, default_handler);
+
+fn default_handler(irqn: i16) {
+    panic!("Unhandled exception (IRQn = {})", irqn);
+}
      +
      \ No newline at end of file diff --git a/cortex_m_quickstart/examples/_1_hello/sidebar-items.js b/cortex_m_quickstart/examples/_1_hello/sidebar-items.js new file mode 100644 index 0000000..48333d3 --- /dev/null +++ b/cortex_m_quickstart/examples/_1_hello/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({}); \ No newline at end of file diff --git a/cortex_m_quickstart/examples/_2_itm/index.html b/cortex_m_quickstart/examples/_2_itm/index.html new file mode 100644 index 0000000..6afa7df --- /dev/null +++ b/cortex_m_quickstart/examples/_2_itm/index.html @@ -0,0 +1,50 @@ +cortex_m_quickstart::examples::_2_itm - Rust

      [−][src]Module cortex_m_quickstart::examples::_2_itm

      Sends "Hello, world!" through the ITM port 0

      +

      ITM is much faster than semihosting. Like 4 orders of magnitude or so.

      +

      NOTE Cortex-M0 chips don't support ITM.

      +

      You'll have to connect the microcontroller's SWO pin to the SWD interface. Note that some +development boards don't provide this option.

      +

      You'll need itmdump to receive the message on the host plus you'll need to uncomment two +monitor commands in the .gdbinit file.

      +
      + +
      +
+#![no_main]
+#![no_std]
+
+#[macro_use]
+extern crate cortex_m;
+#[macro_use]
+extern crate cortex_m_rt as rt;
+extern crate panic_semihosting;
+
+use cortex_m::{asm, Peripherals};
+use rt::ExceptionFrame;
+
+entry!(main);
+
+fn main() -> ! {
+    let mut p = Peripherals::take().unwrap();
+    let stim = &mut p.ITM.stim[0];
+
+    iprintln!(stim, "Hello, world!");
+
+    loop {
+        asm::bkpt();
+    }
+}
+
+// define the hard fault handler
+exception!(HardFault, hard_fault);
+
+fn hard_fault(ef: &ExceptionFrame) -> ! {
+    panic!("HardFault at {:#?}", ef);
+}
+
+// define the default exception handler
+exception!(*, default_handler);
+
+fn default_handler(irqn: i16) {
+    panic!("Unhandled exception (IRQn = {})", irqn);
+}
      +
      \ No newline at end of file diff --git a/cortex_m_quickstart/examples/_2_itm/sidebar-items.js b/cortex_m_quickstart/examples/_2_itm/sidebar-items.js new file mode 100644 index 0000000..48333d3 --- /dev/null +++ b/cortex_m_quickstart/examples/_2_itm/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({}); \ No newline at end of file diff --git a/cortex_m_quickstart/examples/_3_panic/index.html b/cortex_m_quickstart/examples/_3_panic/index.html new file mode 100644 index 0000000..b94eb9e --- /dev/null +++ b/cortex_m_quickstart/examples/_3_panic/index.html @@ -0,0 +1,42 @@ +cortex_m_quickstart::examples::_3_panic - Rust

      [−][src]Module cortex_m_quickstart::examples::_3_panic

      Changing the panic handler

      +

      The easiest way to change the panic handler is to use a different panic handler crate.

      +
      + +
      +
+#![no_main]
+#![no_std]
+
+#[macro_use]
+extern crate cortex_m_rt as rt;
+
+// Pick one of these two panic handlers:
+
+// Reports panic messages to the host stderr using semihosting
+extern crate panic_semihosting;
+
+// Logs panic messages using the ITM (Instrumentation Trace Macrocell)
+// extern crate panic_itm;
+
+use rt::ExceptionFrame;
+
+entry!(main);
+
+fn main() -> ! {
+    panic!("Oops")
+}
+
+// define the hard fault handler
+exception!(HardFault, hard_fault);
+
+fn hard_fault(ef: &ExceptionFrame) -> ! {
+    panic!("HardFault at {:#?}", ef);
+}
+
+// define the default exception handler
+exception!(*, default_handler);
+
+fn default_handler(irqn: i16) {
+    panic!("Unhandled exception (IRQn = {})", irqn);
+}
      +
      \ No newline at end of file diff --git a/cortex_m_quickstart/examples/_3_panic/sidebar-items.js b/cortex_m_quickstart/examples/_3_panic/sidebar-items.js new file mode 100644 index 0000000..48333d3 --- /dev/null +++ b/cortex_m_quickstart/examples/_3_panic/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({}); \ No newline at end of file diff --git a/cortex_m_quickstart/examples/_4_crash/index.html b/cortex_m_quickstart/examples/_4_crash/index.html new file mode 100644 index 0000000..4a95302 --- /dev/null +++ b/cortex_m_quickstart/examples/_4_crash/index.html @@ -0,0 +1,105 @@ +cortex_m_quickstart::examples::_4_crash - Rust

      [−][src]Module cortex_m_quickstart::examples::_4_crash

      Debugging a crash (exception)

      +

      Most crash conditions trigger a hard fault exception, whose handler is defined via +exception!(HardFault, ..). The HardFault handler has access to the exception frame, a +snapshot of the CPU registers at the moment of the exception.

      +

      This program crashes and the HardFault handler prints to the console the contents of the +ExceptionFrame and then triggers a breakpoint. From that breakpoint one can see the backtrace +that led to the exception.

      +
      (gdb) continue
+Program received signal SIGTRAP, Trace/breakpoint trap.
+__bkpt () at asm/bkpt.s:3
+3         bkpt
+
+(gdb) backtrace
+#0  __bkpt () at asm/bkpt.s:3
+#1  0x080030b4 in cortex_m::asm::bkpt () at $$/cortex-m-0.5.0/src/asm.rs:19
+#2  rust_begin_unwind (args=..., file=..., line=99, col=5) at $$/panic-semihosting-0.2.0/src/lib.rs:87
+#3  0x08001d06 in core::panicking::panic_fmt () at libcore/panicking.rs:71
+#4  0x080004a6 in crash::hard_fault (ef=0x20004fa0) at examples/crash.rs:99
+#5  0x08000548 in UserHardFault (ef=0x20004fa0) at <exception macros>:10
+#6  0x0800093a in HardFault () at asm.s:5
+Backtrace stopped: previous frame identical to this frame (corrupt stack?)
+
      +

      In the console output one will find the state of the Program Counter (PC) register at the time +of the exception.

      +
      panicked at 'HardFault at ExceptionFrame {
+    r0: 0x2fffffff,
+    r1: 0x2fffffff,
+    r2: 0x080051d4,
+    r3: 0x080051d4,
+    r12: 0x20000000,
+    lr: 0x08000435,
+    pc: 0x08000ab6,
+    xpsr: 0x61000000
+}', examples/crash.rs:106:5
+
      +

      This register contains the address of the instruction that caused the exception. In GDB one can +disassemble the program around this address to observe the instruction that caused the +exception.

      +
      (gdb) disassemble/m 0x08000ab6
+Dump of assembler code for function core::ptr::read_volatile:
+451     pub unsafe fn read_volatile<T>(src: *const T) -> T {
+   0x08000aae <+0>:     sub     sp, #16
+   0x08000ab0 <+2>:     mov     r1, r0
+   0x08000ab2 <+4>:     str     r0, [sp, #8]
+
+452         intrinsics::volatile_load(src)
+   0x08000ab4 <+6>:     ldr     r0, [sp, #8]
+-> 0x08000ab6 <+8>:     ldr     r0, [r0, #0]
+   0x08000ab8 <+10>:    str     r0, [sp, #12]
+   0x08000aba <+12>:    ldr     r0, [sp, #12]
+   0x08000abc <+14>:    str     r1, [sp, #4]
+   0x08000abe <+16>:    str     r0, [sp, #0]
+   0x08000ac0 <+18>:    b.n     0x8000ac2 <core::ptr::read_volatile+20>
+
+453     }
+   0x08000ac2 <+20>:    ldr     r0, [sp, #0]
+   0x08000ac4 <+22>:    add     sp, #16
+   0x08000ac6 <+24>:    bx      lr
+
+End of assembler dump.
+
      +

      ldr r0, [r0, #0] caused the exception. This instruction tried to load (read) a 32-bit word +from the address stored in the register r0. Looking again at the contents of ExceptionFrame +we see that the r0 contained the address 0x2FFF_FFFF when this instruction was executed.

      +
      + +
      +
+#![no_main]
+#![no_std]
+
+extern crate cortex_m;
+#[macro_use]
+extern crate cortex_m_rt as rt;
+extern crate panic_semihosting;
+
+use core::ptr;
+
+use rt::ExceptionFrame;
+
+entry!(main);
+
+fn main() -> ! {
+    unsafe {
+        // read an address outside of the RAM region; causes a HardFault exception
+        ptr::read_volatile(0x2FFF_FFFF as *const u32);
+    }
+
+    loop {}
+}
+
+// define the hard fault handler
+exception!(HardFault, hard_fault);
+
+fn hard_fault(ef: &ExceptionFrame) -> ! {
+    panic!("HardFault at {:#?}", ef);
+}
+
+// define the default exception handler
+exception!(*, default_handler);
+
+fn default_handler(irqn: i16) {
+    panic!("Unhandled exception (IRQn = {})", irqn);
+}
      +
      \ No newline at end of file diff --git a/cortex_m_quickstart/examples/_4_crash/sidebar-items.js b/cortex_m_quickstart/examples/_4_crash/sidebar-items.js new file mode 100644 index 0000000..48333d3 --- /dev/null +++ b/cortex_m_quickstart/examples/_4_crash/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({}); \ No newline at end of file diff --git a/cortex_m_quickstart/examples/_5_exception/index.html b/cortex_m_quickstart/examples/_5_exception/index.html new file mode 100644 index 0000000..fffe1a1 --- /dev/null +++ b/cortex_m_quickstart/examples/_5_exception/index.html @@ -0,0 +1,63 @@ +cortex_m_quickstart::examples::_5_exception - Rust

      [−][src]Module cortex_m_quickstart::examples::_5_exception

      Overriding an exception handler

      +

      You can override an exception handler using the exception! macro.

      +
      + +
      +
+#![deny(unsafe_code)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m;
+#[macro_use]
+extern crate cortex_m_rt as rt;
+extern crate cortex_m_semihosting as sh;
+extern crate panic_semihosting;
+
+use core::fmt::Write;
+
+use cortex_m::peripheral::syst::SystClkSource;
+use cortex_m::Peripherals;
+use rt::ExceptionFrame;
+use sh::hio::{self, HStdout};
+
+entry!(main);
+
+fn main() -> ! {
+    let p = Peripherals::take().unwrap();
+    let mut syst = p.SYST;
+
+    // configures the system timer to trigger a SysTick exception every second
+    syst.set_clock_source(SystClkSource::Core);
+    syst.set_reload(8_000_000); // period = 1s
+    syst.enable_counter();
+    syst.enable_interrupt();
+
+    loop {}
+}
+
+// try commenting out this line: you'll end in `default_handler` instead of in `sys_tick`
+exception!(SysTick, sys_tick, state: Option<HStdout> = None);
+
+fn sys_tick(state: &mut Option<HStdout>) {
+    if state.is_none() {
+        *state = Some(hio::hstdout().unwrap());
+    }
+
+    if let Some(hstdout) = state.as_mut() {
+        hstdout.write_str(".").unwrap();
+    }
+}
+
+exception!(HardFault, hard_fault);
+
+fn hard_fault(ef: &ExceptionFrame) -> ! {
+    panic!("HardFault at {:#?}", ef);
+}
+
+exception!(*, default_handler);
+
+fn default_handler(irqn: i16) {
+    panic!("Unhandled exception (IRQn = {})", irqn);
+}
      +
      \ No newline at end of file diff --git a/cortex_m_quickstart/examples/_5_exception/sidebar-items.js b/cortex_m_quickstart/examples/_5_exception/sidebar-items.js new file mode 100644 index 0000000..48333d3 --- /dev/null +++ b/cortex_m_quickstart/examples/_5_exception/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({}); \ No newline at end of file diff --git a/cortex_m_quickstart/examples/_6_allocator/index.html b/cortex_m_quickstart/examples/_6_allocator/index.html new file mode 100644 index 0000000..c404fda --- /dev/null +++ b/cortex_m_quickstart/examples/_6_allocator/index.html @@ -0,0 +1,74 @@ +cortex_m_quickstart::examples::_6_allocator - Rust

      [−][src]Module cortex_m_quickstart::examples::_6_allocator

      How to use the heap and a dynamic memory allocator

      +

      This example depends on the alloc-cortex-m crate so you'll have to add it to your Cargo.toml:

      +
      # or edit the Cargo.toml file manually
+$ cargo add alloc-cortex-m
+
      +
      + +
      +
+#![feature(alloc)]
+#![feature(global_allocator)]
+#![feature(lang_items)]
+#![no_main]
+#![no_std]
+
+// This is the allocator crate; you can use a different one
+extern crate alloc_cortex_m;
+#[macro_use]
+extern crate alloc;
+extern crate cortex_m;
+#[macro_use]
+extern crate cortex_m_rt as rt;
+extern crate cortex_m_semihosting as sh;
+extern crate panic_semihosting;
+
+use core::fmt::Write;
+
+use alloc_cortex_m::CortexMHeap;
+use cortex_m::asm;
+use rt::ExceptionFrame;
+use sh::hio;
+
+// this is the allocator the application will use
+#[global_allocator]
+static ALLOCATOR: CortexMHeap = CortexMHeap::empty();
+
+const HEAP_SIZE: usize = 1024; // in bytes
+
+entry!(main);
+
+fn main() -> ! {
+    // Initialize the allocator BEFORE you use it
+    unsafe { ALLOCATOR.init(rt::heap_start() as usize, HEAP_SIZE) }
+
+    // Growable array allocated on the heap
+    let xs = vec![0, 1, 2];
+
+    let mut stdout = hio::hstdout().unwrap();
+    writeln!(stdout, "{:?}", xs).unwrap();
+
+    loop {}
+}
+
+// define what happens in an Out Of Memory (OOM) condition
+#[lang = "oom"]
+#[no_mangle]
+pub fn rust_oom() -> ! {
+    asm::bkpt();
+
+    loop {}
+}
+
+exception!(HardFault, hard_fault);
+
+fn hard_fault(ef: &ExceptionFrame) -> ! {
+    panic!("HardFault at {:#?}", ef);
+}
+
+exception!(*, default_handler);
+
+fn default_handler(irqn: i16) {
+    panic!("Unhandled exception (IRQn = {})", irqn);
+}
      +
      \ No newline at end of file diff --git a/cortex_m_quickstart/examples/_6_allocator/sidebar-items.js b/cortex_m_quickstart/examples/_6_allocator/sidebar-items.js new file mode 100644 index 0000000..48333d3 --- /dev/null +++ b/cortex_m_quickstart/examples/_6_allocator/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({}); \ No newline at end of file diff --git a/cortex_m_quickstart/examples/_7_device/index.html b/cortex_m_quickstart/examples/_7_device/index.html new file mode 100644 index 0000000..1d9f535 --- /dev/null +++ b/cortex_m_quickstart/examples/_7_device/index.html @@ -0,0 +1,83 @@ +cortex_m_quickstart::examples::_7_device - Rust

      [−][src]Module cortex_m_quickstart::examples::_7_device

      Using a device crate

      +

      Crates generated using svd2rust are referred to as device crates. These crates provide an +API to access the peripherals of a device.

      +

      Device crates also provide an interrupt! macro (behind the "rt" feature) to register interrupt +handlers.

      +

      This example depends on the stm32f103xx crate so you'll have to add it to your Cargo.toml.

      + +
      +$ edit Cargo.toml && tail $_
+[dependencies.stm32f103xx]
+features = ["rt"]
+version = "0.10.0"
      +
      + +
      +
+#![no_main]
+#![no_std]
+
+extern crate cortex_m;
+#[macro_use]
+extern crate cortex_m_rt as rt;
+extern crate cortex_m_semihosting as sh;
+#[macro_use]
+extern crate stm32f103xx;
+extern crate panic_semihosting;
+
+use core::fmt::Write;
+
+use cortex_m::peripheral::syst::SystClkSource;
+use rt::ExceptionFrame;
+use sh::hio::{self, HStdout};
+use stm32f103xx::Interrupt;
+
+entry!(main);
+
+fn main() -> ! {
+    let p = cortex_m::Peripherals::take().unwrap();
+
+    let mut syst = p.SYST;
+    let mut nvic = p.NVIC;
+
+    nvic.enable(Interrupt::EXTI0);
+
+    // configure the system timer to wrap around every second
+    syst.set_clock_source(SystClkSource::Core);
+    syst.set_reload(8_000_000); // 1s
+    syst.enable_counter();
+
+    loop {
+        // busy wait until the timer wraps around
+        while !syst.has_wrapped() {}
+
+        // trigger the `EXTI0` interrupt
+        nvic.set_pending(Interrupt::EXTI0);
+    }
+}
+
+// try commenting out this line: you'll end in `default_handler` instead of in `exti0`
+interrupt!(EXTI0, exti0, state: Option<HStdout> = None);
+
+fn exti0(state: &mut Option<HStdout>) {
+    if state.is_none() {
+        *state = Some(hio::hstdout().unwrap());
+    }
+
+    if let Some(hstdout) = state.as_mut() {
+        hstdout.write_str(".").unwrap();
+    }
+}
+
+exception!(HardFault, hard_fault);
+
+fn hard_fault(ef: &ExceptionFrame) -> ! {
+    panic!("HardFault at {:#?}", ef);
+}
+
+exception!(*, default_handler);
+
+fn default_handler(irqn: i16) {
+    panic!("Unhandled exception (IRQn = {})", irqn);
+}
      +
      \ No newline at end of file diff --git a/cortex_m_quickstart/examples/_7_device/sidebar-items.js b/cortex_m_quickstart/examples/_7_device/sidebar-items.js new file mode 100644 index 0000000..48333d3 --- /dev/null +++ b/cortex_m_quickstart/examples/_7_device/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({}); \ No newline at end of file diff --git a/cortex_m_quickstart/examples/index.html b/cortex_m_quickstart/examples/index.html new file mode 100644 index 0000000..a59494d --- /dev/null +++ b/cortex_m_quickstart/examples/index.html @@ -0,0 +1,67 @@ +cortex_m_quickstart::examples - Rust

      [−][src]Module cortex_m_quickstart::examples

      Examples sorted in increasing degree of complexity

      +

      Modules

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      _0_minimal +

      Minimal Cortex-M program

      + +
      _1_hello +

      Prints "Hello, world!" on the OpenOCD console using semihosting

      + +
      _2_itm +

      Sends "Hello, world!" through the ITM port 0

      + +
      _3_panic +

      Changing the panic handler

      + +
      _4_crash +

      Debugging a crash (exception)

      + +
      _5_exception +

      Overriding an exception handler

      + +
      _6_allocator +

      How to use the heap and a dynamic memory allocator

      + +
      _7_device +

      Using a device crate

      + +
      \ No newline at end of file diff --git a/cortex_m_quickstart/examples/sidebar-items.js b/cortex_m_quickstart/examples/sidebar-items.js new file mode 100644 index 0000000..538c2ca --- /dev/null +++ b/cortex_m_quickstart/examples/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"mod":[["_0_minimal","Minimal Cortex-M program"],["_1_hello","Prints \"Hello, world!\" on the OpenOCD console using semihosting"],["_2_itm","Sends \"Hello, world!\" through the ITM port 0"],["_3_panic","Changing the panic handler"],["_4_crash","Debugging a crash (exception)"],["_5_exception","Overriding an exception handler"],["_6_allocator","How to use the heap and a dynamic memory allocator"],["_7_device","Using a device crate"]]}); \ No newline at end of file diff --git a/cortex_m_quickstart/index.html b/cortex_m_quickstart/index.html new file mode 100644 index 0000000..9318683 --- /dev/null +++ b/cortex_m_quickstart/index.html @@ -0,0 +1,276 @@ +cortex_m_quickstart - Rust

      [−][src]Crate cortex_m_quickstart

      A template for building applications for ARM Cortex-M microcontrollers

      +

      Dependencies

      +
        +
      • Nightly Rust toolchain from 2018-08-28 or newer: rustup default nightly
        • +
      • Cargo clone subcommand: cargo install cargo-clone
        • +
      • GDB: sudo apt-get install gdb-arm-none-eabi (on Ubuntu)
        • +
      • OpenOCD: sudo apt-get install OpenOCD (on Ubuntu)
        • +
      • [Optional] Cargo add subcommand: cargo install cargo-edit
        • +
      +

      Usage

      +
        +
      1. +

        Figure out the cross compilation target to use.

        +
        2. +
      +
        +
      • +

        Use thumbv6m-none-eabi for ARM Cortex-M0 and Cortex-M0+

        +
        • +
      • +

        Use thumbv7m-none-eabi for ARM Cortex-M3

        +
        • +
      • +

        Use thumbv7em-none-eabi for ARM Cortex-M4 and Cortex-M7 (no FPU support)

        +
        • +
      • +

        Use thumbv7em-none-eabihf for ARM Cortex-M4F and Cortex-M7F (with FPU support)

        +
        • +
      +
        +
      1. Install the rust-std component for your target, if you haven't done so already
        2. +
      +
      $ rustup target add thumbv7em-none-eabihf
+
      +
        +
      1. Clone this crate
        2. +
      +
      $ cargo clone cortex-m-quickstart --vers 0.3.4
+
      +
        +
      1. Change the crate name, author and version
        2. +
      +
      $ edit Cargo.toml && head $_
+[package]
+authors = ["Jorge Aparicio <jorge@japaric.io>"]
+name = "demo"
+version = "0.1.0"
+
      +
        +
      1. Specify the memory layout of the target device
        2. +
      +

      NOTE board support crates sometimes provide this file for you (check the crate +documentation). If you are using one that does then remove both memory.x and build.rs from +the root of this crate.

      +
      $ cat >memory.x <<'EOF'
+MEMORY
+{
+  /* NOTE K = KiBi = 1024 bytes */
+  FLASH : ORIGIN = 0x08000000, LENGTH = 256K
+  RAM : ORIGIN = 0x20000000, LENGTH = 40K
+}
+EOF
+
      +
        +
      1. Optionally, set a default build target. This way you don't have to pass --target to each +Cargo invocation.
        2. +
      +
      $ cat >>.cargo/config <<'EOF'
+[build]
+target = "thumbv7em-none-eabihf"
+EOF
+
      +
        +
      1. Optionally, depend on a device, HAL implementation or a board support crate.
        2. +
      +
      $ # add a device crate, OR
+$ cargo add stm32f30x
+
+$ # add a HAL implementation crate, OR
+$ cargo add stm32f30x-hal
+
+$ # add a board support crate
+$ cargo add f3
+
      +
        +
      1. Write the application or start from one of the examples
        2. +
      +
      $ rm -r src/* && cp examples/hello.rs src/main.rs
+
      +
        +
      1. Build the application
        2. +
      +
      $ cargo build --release
+
+$ # sanity check
+$ arm-none-eabi-readelf -A target/thumbv7em-none-eabihf/release/demo
+Attribute Section: aeabi
+File Attributes
+  Tag_conformance: "2.09"
+  Tag_CPU_arch: v7E-M
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4-D16
+  Tag_ABI_PCS_GOT_use: direct
+  Tag_ABI_FP_denormal: Needed
+  Tag_ABI_FP_exceptions: Needed
+  Tag_ABI_FP_number_model: IEEE 754
+  Tag_ABI_align_needed: 8-byte
+  Tag_ABI_align_preserved: 8-byte, except leaf SP
+  Tag_ABI_HardFP_use: SP only
+  Tag_ABI_VFP_args: VFP registers
+  Tag_ABI_optimization_goals: Aggressive Speed
+  Tag_CPU_unaligned_access: v6
+  Tag_FP_HP_extension: Allowed
+  Tag_ABI_FP_16bit_format: IEEE 754
+
      +
        +
      1. Flash and debug the program
        2. +
      +
      $ # Launch OpenOCD on a terminal
+$ openocd -f (..)
+
      +
      $ # Start a debug session in another terminal
+$ arm-none-eabi-gdb target/thumbv7em-none-eabihf/release/demo
+
      +

      Alternatively, you can use cargo run to build, flash and debug the program in a single step.

      +
      $ cargo run --example hello
+> # drops you into a GDB session
+
      +

      Examples

      +

      Check the examples module

      +

      Troubleshooting

      +

      This section contains fixes for common errors encountered when the +cortex-m-quickstart template is misused.

      +

      Used the standard main interface

      +

      Error message:

      +
      $ cargo build
+   Compiling demo v0.1.0 (file:///home/japaric/tmp/demo)
+
+error: requires `start` lang_item
+
      +

      Solution: Use #![no_main] and entry! as shown in the examples.

      +

      Forgot to launch an OpenOCD instance

      +

      Error message:

      +
      $ arm-none-eabi-gdb target/..
+Reading symbols from hello...done.
+.gdbinit:1: Error in sourced command file:
+:3333: Connection timed out.
+
      +

      Solution: Launch OpenOCD on other terminal. See Usage section.

      +

      Didn't modify the memory.x linker script

      +

      Error message:

      +
      $ cargo build
+Compiling demo v0.1.0 (file:///home/japaric/tmp/demo)
+error: linking with `rust-lld` failed: exit code: 1
+|
+= note: "rust-lld" "-flavor" "gnu" "-L" (..)
+(..)
+ = note: rust-lld: error: section '.vector_table' will not fit in region 'FLASH': overflowed by X bytes
+         rust-lld: error: section '.vector_table' will not fit in region 'FLASH': overflowed by Y bytes
+(..)
+
      +

      Solution: Specify your device memory layout in the memory.x linker script. See Usage +section.

      +

      Didn't set a default build target and forgot to pass --target to Cargo

      +

      Error message:

      +
      $ cargo build
+(..)
+error: language item required, but not found: `eh_personality`
+
+error: aborting due to previous error
+
      +

      Solution: Set a default build target in the .cargo/config file (see Usage section), or call +Cargo with --target flag: cargo build --target thumbv7em-none-eabi.

      +

      Overwrote the original .cargo/config file

      +

      You won't get an error message but the output binary will be empty

      +
      $ cargo build && echo OK
+OK
+
+$ size target/thumbv7m-none-eabi/debug/app
+   text    data     bss     dec     hex filename
+      0       0       0       0       0 target/thumbv7m-none-eabi/debug/app
+
      +

      Solution: You probably overwrote the original .cargo/config instead of appending the default +build target (e.g. cat > instead of cat >>). The less error prone way to fix this is to +remove the .cargo directory, clone a new copy of the template and then copy the .cargo +directory from that fresh template into your current project. Don't forget to append the +default build target to .cargo/config.

      +

      Called OpenOCD with wrong arguments

      +

      Error message:

      +
      $ openocd -f ..
+(..)
+Error: open failed
+in procedure 'init'
+in procedure 'ocd_bouncer'
+
      +

      Solution: Correct the OpenOCD arguments. Check the /usr/share/openocd/scripts directory (exact +location varies per distribution / OS) for a list of scripts that can be used.

      +

      Forgot to install the rust-std component

      +

      Error message:

      +
      $ cargo build
+error[E0463]: can't find crate for `core`
+  |
+  = note: the `thumbv7m-none-eabi` target may not be installed
+
      +

      Solution: call rustup target add thumbv7m-none-eabi but with the name of your target

      +

      Used an old nightly

      +

      Error message:

      +
      $ cargo build
+Compiling cortex-m-rt v0.2.0
+error[E0463]: can't find crate for `core`
+|
+= note: the `thumbv7em-none-eabihf` target may not be installed
+
+error: aborting due to previous error
+
      +

      Solution: Use a more recent nightly

      +

      Used the stable toolchain

      +

      Error message:

      +
      $ cargo build
+error[E0463]: can't find crate for `core`
+  |
+  = note: the `thumbv7em-none-eabihf` target may not be installed
+
      +

      Solution: We are not there yet! Switch to the nightly toolchain with rustup default nightly.

      +

      Used gdb instead of arm-none-eabi-gdb

      +

      Error message:

      +
      $ gdb target/..
+Reading symbols from hello...done.
+warning: Architecture rejected target-supplied description
+warning: Cannot convert floating-point register value to ..
+value has been optimized out
+Cannot write the dashboard
+Traceback (most recent call last):
+File "<string>", line 353, in render
+File "<string>", line 846, in lines
+gdb.error: Frame is invalid.
+0x00000000 in ?? ()
+semihosting is enabled
+Loading section .text, size 0xd88 lma 0x8000000
+Start address 0x8000000, load size 3464
+.gdbinit:6: Error in sourced command file:
+Remote connection closed
+
      +

      Solution: Use arm-none-eabi-gdb target/..

      +

      Used a named piped for itm.fifo

      +

      Error message:

      +
      $ cargo run [--example ..]
+
+Reading symbols from target/thumbv7em-none-eabihf/debug/cortex-m-quickstart...done.
+cortex_m_rt::reset_handler ()
+    at $REGISTRY/cortex-m-rt-0.3.12/src/lib.rs:330
+330     unsafe extern "C" fn reset_handler() -> ! {
+semihosting is enabled
+Ignoring packet error, continuing...
+Ignoring packet error, continuing...
+
      +

      Note that when you reach this point OpenOCD will become unresponsive and you'll have to kill it +and start a new OpenOCD process before you can invoke cargo run / start GDB.

      +

      Cause: You uncommented the monitor tpiu .. line in .gdbinit and are using a named pipe to +receive the ITM data (i.e. you ran mkfifo itm.fifo). This error occurs when itmdump -f itm.fifo (or equivalent, e.g. cat itm.fifo) is not running.

      +

      Solution: Run itmdump -f itm.fifo (or equivalently cat itm.fifo) before invoking cargo run / starting GDB. Note that sometimes itmdump will exit when the GDB session ends. In that +case you'll have to run itmdump before you start the next GDB session.

      +

      Alternative solution: Use a plain text file instead of a named pipe. In this scenario you omit +the mkfifo itm.dump command. You can use itmdump's follow mode (-F) to get named pipe like +output.

      +

      Modules

      + + + + +
      examples +

      Examples sorted in increasing degree of complexity

      + +
      \ No newline at end of file diff --git a/cortex_m_quickstart/sidebar-items.js b/cortex_m_quickstart/sidebar-items.js new file mode 100644 index 0000000..40ec17c --- /dev/null +++ b/cortex_m_quickstart/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"mod":[["examples","Examples sorted in increasing degree of complexity"]]}); \ No newline at end of file diff --git a/cortex_m_rt/ExceptionFrame.t.html b/cortex_m_rt/ExceptionFrame.t.html new file mode 100644 index 0000000..2a366d1 --- /dev/null +++ b/cortex_m_rt/ExceptionFrame.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.ExceptionFrame.html...

      + + + \ No newline at end of file diff --git a/cortex_m_rt/all.html b/cortex_m_rt/all.html new file mode 100644 index 0000000..fbb8951 --- /dev/null +++ b/cortex_m_rt/all.html @@ -0,0 +1,3 @@ +List of all items in this crate

      [−] + + List of all items

      Structs

      Macros

      Functions

      \ No newline at end of file diff --git a/cortex_m_rt/entry.m.html b/cortex_m_rt/entry.m.html new file mode 100644 index 0000000..c26a44c --- /dev/null +++ b/cortex_m_rt/entry.m.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.entry.html...

      + + + \ No newline at end of file diff --git a/cortex_m_rt/exception.m.html b/cortex_m_rt/exception.m.html new file mode 100644 index 0000000..ae4e88e --- /dev/null +++ b/cortex_m_rt/exception.m.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.exception.html...

      + + + \ No newline at end of file diff --git a/cortex_m_rt/fn.heap_start.html b/cortex_m_rt/fn.heap_start.html new file mode 100644 index 0000000..3ad09f1 --- /dev/null +++ b/cortex_m_rt/fn.heap_start.html @@ -0,0 +1,3 @@ +cortex_m_rt::heap_start - Rust

      [−][src]Function cortex_m_rt::heap_start

      pub fn heap_start() -> *mut u32

      Returns a pointer to the start of the heap

      +

      The returned pointer is guaranteed to be 4-byte aligned.

      +
      \ No newline at end of file diff --git a/cortex_m_rt/heap_start.v.html b/cortex_m_rt/heap_start.v.html new file mode 100644 index 0000000..3c69e5e --- /dev/null +++ b/cortex_m_rt/heap_start.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.heap_start.html...

      + + + \ No newline at end of file diff --git a/cortex_m_rt/index.html b/cortex_m_rt/index.html new file mode 100644 index 0000000..565d425 --- /dev/null +++ b/cortex_m_rt/index.html @@ -0,0 +1,374 @@ +cortex_m_rt - Rust

      [−][src]Crate cortex_m_rt

      Minimal startup / runtime for Cortex-M microcontrollers

      +

      This crate contains all the required parts to build a no_std application (binary crate) that +targets a Cortex-M microcontroller.

      +

      Features

      +

      This crates takes care of:

      +
        +
      • +

        The memory layout of the program. In particular, it populates the vector table so the device +can boot correctly, and properly dispatch exceptions and interrupts.

        +
        • +
      • +

        Initializing static variables before the program entry point.

        +
        • +
      • +

        Enabling the FPU before the program entry point if the target is thumbv7em-none-eabihf.

        +
        • +
      +

      This crate also provides a mechanism to set exception handlers: see the exception! macro.

      +

      Requirements

      memory.x

      +

      This crate expects the user, or some other crate, to provide the memory layout of the target +device via a linker script named memory.x. This section covers the contents of memory.x

      +

      MEMORY

      +

      The linker script must specify the memory available in the device as, at least, two MEMORY +regions: one named FLASH and one named RAM. The .text and .rodata sections of the +program will be placed in the FLASH region, whereas the .bss and .data sections, as well +as the heap,will be placed in the RAM region.

      +
      /* Linker script for the STM32F103C8T6 */
+MEMORY
+{
+  FLASH : ORIGIN = 0x08000000, LENGTH = 64K
+  RAM : ORIGIN = 0x20000000, LENGTH = 20K
+}
+
      +

      _stack_start

      +

      This optional symbol can be used to indicate where the call stack of the program should be +placed. If this symbol is not used then the stack will be placed at the end of the RAM +region -- the stack grows downwards towards smaller address. This symbol can be used to place +the stack in a different memory region, for example:

      +
      /* Linker script for the STM32F303VCT6 */
+MEMORY
+{
+    FLASH : ORIGIN = 0x08000000, LENGTH = 256K
+
+    /* .bss, .data and the heap go in this region */
+    RAM : ORIGIN = 0x20000000, LENGTH = 40K
+
+    /* Core coupled (faster) RAM dedicated to hold the stack */
+    CCRAM : ORIGIN = 0x10000000, LENGTH = 8K
+}
+
+_stack_start = ORIGIN(CCRAM) + LENGTH(CCRAM);
+
      +

      _stext

      +

      This optional symbol can be used to control where the .text section is placed. If omitted the +.text section will be placed right after the vector table, which is placed at the beginning of +FLASH. Some devices store settings like Flash configuration right after the vector table; +for these devices one must place the .text section after this configuration section -- +_stext can be used for this purpose.

      +
      MEMORY
+{
+  /* .. */
+}
+
+/* The device stores Flash configuration in 0x400-0x40C so we place .text after that */
+_stext = ORIGIN(FLASH) + 0x40C
+
      +

      An example

      +

      This section presents a minimal application built on top of cortex-m-rt. Apart from the +mandatory memory.x linker script describing the memory layout of the device, the hard fault +handler and the default exception handler must also be defined somewhere in the dependency +graph (cf. exception!). In this example we define them in the binary crate:

      + +
      ⓘThis example is not tested
      +// IMPORTANT the standard `main` interface is not used because it requires nightly
+#![no_main]
+#![no_std]
+
+#[macro_use(entry, exception)]
+extern crate cortex_m_rt as rt;
+
+// makes `panic!` print messages to the host stderr using semihosting
+extern crate panic_semihosting;
+
+use rt::ExceptionFrame;
+
+// use `main` as the entry point of this application
+entry!(main);
+
+// `main` is not allowed to return
+fn main() -> ! {
+    // initialization
+
+    loop {
+        // application logic
+    }
+}
+
+// define the hard fault handler
+exception!(HardFault, hard_fault);
+
+fn hard_fault(ef: &ExceptionFrame) -> ! {
+    panic!("{:#?}", ef);
+}
+
+// define the default exception handler
+exception!(*, default_handler);
+
+fn default_handler(irqn: i16) {
+    panic!("unhandled exception (IRQn={})", irqn);
+}
      +

      To actually build this program you need to place a memory.x linker script somewhere the linker +can find it, e.g. in the current directory; and then link the program using cortex-m-rt's +linker script: link.x. The required steps are shown below:

      +
      $ cat > memory.x <<EOF
+/* Linker script for the STM32F103C8T6 */
+MEMORY
+{
+  FLASH : ORIGIN = 0x08000000, LENGTH = 64K
+  RAM : ORIGIN = 0x20000000, LENGTH = 20K
+}
+EOF
+
+$ cargo rustc --target thumbv7m-none-eabi -- \
+      -C link-arg=-nostartfiles -C link-arg=-Tlink.x
+
+$ file target/thumbv7m-none-eabi/debug/app
+app: ELF 32-bit LSB executable, ARM, EABI5 version 1 (SYSV), statically linked, (..)
+
      +

      Optional features

      device

      +

      If this feature is disabled then this crate populates the whole vector table. All the interrupts +in the vector table, even the ones unused by the target device, will be bound to the default +exception handler. This makes the final application device agnostic: you will be able to run it +on any Cortex-M device -- provided that you correctly specified its memory layout in memory.x +-- without hitting undefined behavior.

      +

      If this feature is enabled then the interrupts section of the vector table is left unpopulated +and some other crate, or the user, will have to populate it. This mode is meant to be used in +conjunction with crates generated using svd2rust. Those device crates will populate the +missing part of the vector table when their "rt" feature is enabled.

      +

      Inspection

      +

      This section covers how to inspect a binary that builds on top of cortex-m-rt.

      +

      Sections (size)

      +

      cortex-m-rt uses standard sections like .text, .rodata, .bss and .data as one would +expect. cortex-m-rt separates the vector table in its own section, named .vector_table. This +lets you distinguish how much space is taking the vector table in Flash vs how much is being +used by actual instructions (.text) and constants (.rodata).

      + +
      +$ size -Ax target/thumbv7m-none-eabi/examples/app
+target/thumbv7m-none-eabi/release/examples/app  :
+section             size         addr
+.vector_table      0x400    0x8000000
+.text               0x88    0x8000400
+.rodata              0x0    0x8000488
+.data                0x0   0x20000000
+.bss                 0x0   0x20000000
      +

      Without the -A argument size reports the sum of the sizes of .text, .rodata and +.vector_table under "text".

      + +
      +$ size target/thumbv7m-none-eabi/examples/app
+  text    data     bss     dec     hex filename
+  1160       0       0    1660     67c target/thumbv7m-none-eabi/release/app
      +

      Symbols (objdump, nm)

      +

      One will always find the following (unmangled) symbols in cortex-m-rt applications:

      +
        +
      • Reset. This is the reset handler. The microcontroller will executed this function upon +booting. This function will call the user program entry point (cf. entry!) using the main +symbol so you may also find that symbol in your program; if you do, main will contain your +application code. Some other times main gets inlined into Reset so you won't find it.
        • +
      +
        +
      • +

        DefaultHandler. This is the default handler. This function will contain, or call, the +function you declared in the second argument of exception!(*, ..).

        +
        • +
      • +

        HardFault. This is the hard fault handler. This function is simply a trampoline that jumps +into the user defined hard fault handler: UserHardFault. The trampoline is required to set up +the pointer to the stacked exception frame.

        +
        • +
      • +

        UserHardFault. This is the user defined hard fault handler. This function will contain, or +call, the function you declared in the second argument of exception!(HardFault, ..)

        +
        • +
      • +

        __STACK_START. This is the first entry in the .vector_table section. This symbol contains +the initial value of the stack pointer; this is where the stack will be located -- the stack +grows downwards towards smaller addresses.

        +
        • +
      • +

        __RESET_VECTOR. This is the reset vector, a pointer into the Reset handler. This vector is +located in the .vector_table section after __STACK_START.

        +
        • +
      • +

        __EXCEPTIONS. This is the core exceptions portion of the vector table; it's an array of 14 +exception vectors, which includes exceptions like HardFault and SysTick. This array is +located after __RESET_VECTOR in the .vector_table section.

        +
        • +
      • +

        __EXCEPTIONS. This is the device specific interrupt portion of the vector table; its exact +size depends on the target device but if the "device" feature has not been enabled it will +have a size of 32 vectors (on ARMv6-M) or 240 vectors (on ARMv7-M). This array is located after +__EXCEPTIONS in the .vector_table section.

        +
        • +
      • +

        __pre_init. This is a function to be run before RAM is initialized. It defaults to an empty +function. The function called can be changed by calling the pre_init! macro. The empty +function is not optimized out by default, but if an empty function is passed to pre_init! the +function call will be optimized out.

        +
        • +
      +

      If you override any exception handler you'll find it as an unmangled symbol, e.g. SysTick or +SVCall, in the output of objdump,

      +

      If you are targeting the thumbv7em-none-eabihf target you'll also see a ResetTrampoline +symbol in the output. To avoid the compiler placing FPU instructions before the FPU has been +enabled (cf. vpush) Reset calls the function ResetTrampoline which is marked as +#[inline(never)] and ResetTrampoline calls main. The compiler is free to inline main +into ResetTrampoline but it can't inline ResetTrampoline into Reset -- the FPU is enabled +in Reset.

      +

      Advanced usage

      Setting the program entry point

      +

      This section describes how entry! is implemented. This information is useful to developers who +want to provide an alternative to entry! that provides extra guarantees.

      +

      The Reset handler will call a symbol named main (unmangled) after initializing .bss and +.data, and enabling the FPU (if the target is thumbv7em-none-eabihf). entry! provides this +symbol in its expansion:

      + +
      ⓘThis example is not tested
      +entry!(path::to::main);
+
+// expands into
+
+#[export_name = "main"]
+pub extern "C" fn __impl_main() -> ! {
+    // validate the signature of the program entry point
+    let f: fn() -> ! = path::to::main;
+
+    f()
+}
      +

      The unmangled main symbol must have signature extern "C" fn() -> ! or its invocation from +Reset will result in undefined behavior.

      +

      Incorporating device specific interrupts

      +

      This section covers how an external crate can insert device specific interrupt handlers into the +vector table. Most users don't need to concern themselves with these details, but if you are +interested in how device crates generated using svd2rust integrate with cortex-m-rt read on.

      +

      The information in this section applies when the "device" feature has been enabled.

      +

      __INTERRUPTS

      +

      The external crate must provide the interrupts portion of the vector table via a static +variable named__INTERRUPTS (unmangled) that must be placed in the .vector_table.interrupts +section of its object file.

      +

      This static variable will be placed at ORIGIN(FLASH) + 0x40. This address corresponds to the +spot where IRQ0 (IRQ number 0) is located.

      +

      To conform to the Cortex-M ABI __INTERRUPTS must be an array of function pointers; some spots +in this array may need to be set to 0 if they are marked as reserved in the data sheet / +reference manual. We recommend using a union to set the reserved spots to 0; None +(Option<fn()>) may also work but it's not guaranteed that the None variant will always be +represented by the value 0.

      +

      Let's illustrate with an artificial example where a device only has two interrupt: Foo, with +IRQ number = 2, and Bar, with IRQ number = 4.

      + +
      ⓘThis example is not tested
      +union Vector {
+    handler: extern "C" fn(),
+    reserved: usize,
+}
+
+extern "C" {
+    fn Foo();
+    fn Bar();
+}
+
+#[link_section = ".vector_table.interrupts"]
+#[no_mangle]
+pub static __INTERRUPTS: [Vector; 5] = [
+    // 0-1: Reserved
+    Vector { reserved: 0 },
+    Vector { reserved: 0 },
+
+    // 2: Foo
+    Vector { handler: Foo },
+
+    // 3: Reserved
+    Vector { reserved: 0 },
+
+    // 4: Bar
+    Vector { handler: Bar },
+];
      +

      device.x

      +

      Linking in __INTERRUPTS creates a bunch of undefined references. If the user doesn't set a +handler for all the device specific interrupts then linking will fail with "undefined reference" errors.

      +

      We want to provide a default handler for all the interrupts while still letting the user +individually override each interrupt handler. In C projects, this is usually accomplished using +weak aliases declared in external assembly files. In Rust, we could achieve something similar +using global_asm!, but that's an unstable feature.

      +

      A solution that doesn't require global_asm! or external assembly files is to use the PROVIDE +command in a linker script to create the weak aliases. This is the approach that cortex-m-rt +uses; when the "device" feature is enabled cortex-m-rt's linker script (link.x) depends on +a linker script named device.x. The crate that provides __INTERRUPTS must also provide this +file.

      +

      For our running example the device.x linker script looks like this:

      +
      /* device.x */
+PROVIDE(Foo = DefaultHandler);
+PROVIDE(Bar = DefaultHandler);
+
      +

      This weakly aliases both Foo and Bar. DefaultHandler is the default exception handler that +the user provides via exception!(*, ..) and that the core exceptions use unless overridden.

      +

      Because this linker script is provided by a dependency of the final application the dependency +must contain build script that puts device.x somewhere the linker can find. An example of such +build script is shown below:

      + +
      ⓘThis example is not tested
      +use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+
+fn main() {
+    // Put the linker script somewhere the linker can find it
+    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    File::create(out.join("device.x"))
+        .unwrap()
+        .write_all(include_bytes!("device.x"))
+        .unwrap();
+    println!("cargo:rustc-link-search={}", out.display());
+}
      +

      pre_init!

      +

      A user-defined function can be run at the start of the reset handler, before RAM is +initialized. The macro pre_init! can be called to set the function to be run. The function is +intended to perform actions that cannot wait the time it takes for RAM to be initialized, such +as disabling a watchdog. As the function is called before RAM is initialized, any access of +static variables will result in undefined behavior.

      +

      Macros

      + + + + + + + + + + + + +
      entry +

      Macro to define the entry point of the program

      + +
      exception +

      Macro to set or override a processor core exception handler

      + +
      pre_init +

      Macro to set the function to be called at the beginning of the reset handler.

      + +

      Structs

      + + + + +
      ExceptionFrame +

      Registers stacked (pushed into the stack) during an exception

      + +

      Functions

      + + + + +
      heap_start +

      Returns a pointer to the start of the heap

      + +
      \ No newline at end of file diff --git a/cortex_m_rt/macro.entry!.html b/cortex_m_rt/macro.entry!.html new file mode 100644 index 0000000..c26a44c --- /dev/null +++ b/cortex_m_rt/macro.entry!.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.entry.html...

      + + + \ No newline at end of file diff --git a/cortex_m_rt/macro.entry.html b/cortex_m_rt/macro.entry.html new file mode 100644 index 0000000..428b435 --- /dev/null +++ b/cortex_m_rt/macro.entry.html @@ -0,0 +1,13 @@ +cortex_m_rt::entry - Rust

      [−][src]Macro cortex_m_rt::entry

      +macro_rules! entry {
+    ($path:expr) => { ... };
+}
      +

      Macro to define the entry point of the program

      +

      NOTE This macro must be invoked once and must be invoked from an accessible module, ideally +from the root of the crate.

      +

      Usage: entry!(path::to::entry::point)

      +

      The specified function will be called by the reset handler after RAM has been initialized. In +the case of the thumbv7em-none-eabihf target the FPU will also be enabled before the function +is called.

      +

      The signature of the specified function must be fn() -> ! (never ending function)

      +
      \ No newline at end of file diff --git a/cortex_m_rt/macro.exception!.html b/cortex_m_rt/macro.exception!.html new file mode 100644 index 0000000..ae4e88e --- /dev/null +++ b/cortex_m_rt/macro.exception!.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.exception.html...

      + + + \ No newline at end of file diff --git a/cortex_m_rt/macro.exception.html b/cortex_m_rt/macro.exception.html new file mode 100644 index 0000000..373cf35 --- /dev/null +++ b/cortex_m_rt/macro.exception.html @@ -0,0 +1,100 @@ +cortex_m_rt::exception - Rust

      [−][src]Macro cortex_m_rt::exception

      +macro_rules! exception {
+    (* , $handler:expr) => { ... };
+    (HardFault, $handler:expr) => { ... };
+    ($Name:ident, $handler:expr,state: $State:ty = $initial_state:expr) => { ... };
+    ($Name:ident, $handler:expr) => { ... };
+}
      +

      Macro to set or override a processor core exception handler

      +

      NOTE This macro must be invoked from an accessible module, ideally from the root of the +crate.

      +

      Syntax

      +
      ⓘThis example is not tested
      +exception!(
+    // Name of the exception
+    $Name:ident,
+
+    // Path to the exception handler (a function)
+    $handler:expr,
+
+    // Optional, state preserved across invocations of the handler
+    state: $State:ty = $initial_state:expr,
+);
      +

      where $Name can be one of:

      +
        +
      • *
        • +
      • NonMaskableInt
        • +
      • HardFault
        • +
      • MemoryManagement (a)
        • +
      • BusFault (a)
        • +
      • UsageFault (a)
        • +
      • SecureFault (b)
        • +
      • SVCall
        • +
      • DebugMonitor (a)
        • +
      • PendSV
        • +
      • SysTick
        • +
      +

      (a) Not available on Cortex-M0 variants (thumbv6m-none-eabi)

      +

      (b) Only available on ARMv8-M

      +

      Usage

      +

      exception!(HardFault, ..) sets the hard fault handler. The handler must have signature +fn(&ExceptionFrame) -> !. This handler is not allowed to return as that can cause undefined +behavior. It's mandatory to set the HardFault handler somewhere in the dependency graph of an +application.

      +

      exception!(*, ..) sets the default handler. All exceptions which have not been assigned a +handler will be serviced by this handler. This handler must have signature fn(irqn: i16). +irqn is the IRQ number (cf. CMSIS); irqn will be a negative number when the handler is +servicing a core exception; irqn will be a positive number when the handler is servicing a +device specific exception (interrupt). It's mandatory to set the default handler somewhere +in the dependency graph of an application.

      +

      exception!($Exception, ..) overrides the default handler for $Exception. All exceptions, +except for HardFault, can be assigned some $State.

      +

      Examples

      +
        +
      • Setting the HardFault handler
        • +
      + +
      +#[macro_use(exception)]
+extern crate cortex_m_rt as rt;
+
+use rt::ExceptionFrame;
+
+exception!(HardFault, hard_fault);
+
+fn hard_fault(ef: &ExceptionFrame) -> ! {
+    // prints the exception frame as a panic message
+    panic!("{:#?}", ef);
+}
+
      +
        +
      • Setting the default handler
        • +
      + +
      +#[macro_use(exception)]
+extern crate cortex_m_rt as rt;
+
+exception!(*, default_handler);
+
+fn default_handler(irqn: i16) {
+    println!("IRQn = {}", irqn);
+}
+
      +
        +
      • Overriding the SysTick handler
        • +
      + +
      +#[macro_use(exception)]
+extern crate cortex_m_rt as rt;
+
+exception!(SysTick, sys_tick, state: u32 = 0);
+
+fn sys_tick(count: &mut u32) {
+    println!("count = {}", *count);
+
+    *count += 1;
+}
+
      +
      \ No newline at end of file diff --git a/cortex_m_rt/macro.pre_init!.html b/cortex_m_rt/macro.pre_init!.html new file mode 100644 index 0000000..3bea5da --- /dev/null +++ b/cortex_m_rt/macro.pre_init!.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.pre_init.html...

      + + + \ No newline at end of file diff --git a/cortex_m_rt/macro.pre_init.html b/cortex_m_rt/macro.pre_init.html new file mode 100644 index 0000000..290508e --- /dev/null +++ b/cortex_m_rt/macro.pre_init.html @@ -0,0 +1,18 @@ +cortex_m_rt::pre_init - Rust

      [−][src]Macro cortex_m_rt::pre_init

      +macro_rules! pre_init {
+    ($handler:path) => { ... };
+}
      +

      Macro to set the function to be called at the beginning of the reset handler.

      +

      The function must have the signature of unsafe fn().

      +

      The function passed will be called before static variables are initialized. Any access of static +variables will result in undefined behavior.

      +

      Examples

      +
      ⓘThis example is not tested
      +pre_init!(foo::bar);
+
+mod foo {
+    pub unsafe fn bar() {
+        // do something here
+    }
+}
      +
      \ No newline at end of file diff --git a/cortex_m_rt/pre_init.m.html b/cortex_m_rt/pre_init.m.html new file mode 100644 index 0000000..3bea5da --- /dev/null +++ b/cortex_m_rt/pre_init.m.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.pre_init.html...

      + + + \ No newline at end of file diff --git a/cortex_m_rt/sidebar-items.js b/cortex_m_rt/sidebar-items.js new file mode 100644 index 0000000..d769cfa --- /dev/null +++ b/cortex_m_rt/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"fn":[["heap_start","Returns a pointer to the start of the heap"]],"macro":[["entry","Macro to define the entry point of the program"],["exception","Macro to set or override a processor core exception handler"],["pre_init","Macro to set the function to be called at the beginning of the reset handler."]],"struct":[["ExceptionFrame","Registers stacked (pushed into the stack) during an exception"]]}); \ No newline at end of file diff --git a/cortex_m_rt/struct.ExceptionFrame.html b/cortex_m_rt/struct.ExceptionFrame.html new file mode 100644 index 0000000..f157386 --- /dev/null +++ b/cortex_m_rt/struct.ExceptionFrame.html @@ -0,0 +1,68 @@ +cortex_m_rt::ExceptionFrame - Rust

      [−][src]Struct cortex_m_rt::ExceptionFrame

      #[repr(C)]
+
      pub struct ExceptionFrame {
+    pub r0: u32,
+    pub r1: u32,
+    pub r2: u32,
+    pub r3: u32,
+    pub r12: u32,
+    pub lr: u32,
+    pub pc: u32,
+    pub xpsr: u32,
+}

      Registers stacked (pushed into the stack) during an exception

      +

      + Fields

      + +

      (General purpose) Register 0

      +
      + +

      (General purpose) Register 1

      +
      + +

      (General purpose) Register 2

      +
      + +

      (General purpose) Register 3

      +
      + +

      (General purpose) Register 12

      +
      + +

      Linker Register

      +
      + +

      Program Counter

      +
      + +

      Program Status Register

      +

      Trait Implementations

      impl Clone for ExceptionFrame
      [src]

      Returns a copy of the value. Read more

      +

      Performs copy-assignment from source. Read more

      +

      impl Copy for ExceptionFrame
      [src]

      impl Debug for ExceptionFrame
      [src]

      Formats the value using the given formatter. Read more

      +

      Auto Trait Implementations

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/all.html b/cortex_m_semihosting/all.html new file mode 100644 index 0000000..fb24f0f --- /dev/null +++ b/cortex_m_semihosting/all.html @@ -0,0 +1,3 @@ +List of all items in this crate

      [−] + + List of all items

      Structs

      Enums

      Macros

      Functions

      Typedefs

      Constants

      \ No newline at end of file diff --git a/cortex_m_semihosting/debug/EXIT_FAILURE.v.html b/cortex_m_semihosting/debug/EXIT_FAILURE.v.html new file mode 100644 index 0000000..4e916b2 --- /dev/null +++ b/cortex_m_semihosting/debug/EXIT_FAILURE.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.EXIT_FAILURE.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/debug/EXIT_SUCCESS.v.html b/cortex_m_semihosting/debug/EXIT_SUCCESS.v.html new file mode 100644 index 0000000..05518bb --- /dev/null +++ b/cortex_m_semihosting/debug/EXIT_SUCCESS.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.EXIT_SUCCESS.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/debug/Exception.t.html b/cortex_m_semihosting/debug/Exception.t.html new file mode 100644 index 0000000..77f30c1 --- /dev/null +++ b/cortex_m_semihosting/debug/Exception.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to enum.Exception.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/debug/ExitStatus.t.html b/cortex_m_semihosting/debug/ExitStatus.t.html new file mode 100644 index 0000000..3cc1181 --- /dev/null +++ b/cortex_m_semihosting/debug/ExitStatus.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to type.ExitStatus.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/debug/constant.EXIT_FAILURE.html b/cortex_m_semihosting/debug/constant.EXIT_FAILURE.html new file mode 100644 index 0000000..8df5bd8 --- /dev/null +++ b/cortex_m_semihosting/debug/constant.EXIT_FAILURE.html @@ -0,0 +1,2 @@ +cortex_m_semihosting::debug::EXIT_FAILURE - Rust

      [−][src]Constant cortex_m_semihosting::debug::EXIT_FAILURE

      pub const EXIT_FAILURE: ExitStatus = Err(())

      Unsuccessful execution of a program.

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/debug/constant.EXIT_SUCCESS.html b/cortex_m_semihosting/debug/constant.EXIT_SUCCESS.html new file mode 100644 index 0000000..e580f86 --- /dev/null +++ b/cortex_m_semihosting/debug/constant.EXIT_SUCCESS.html @@ -0,0 +1,2 @@ +cortex_m_semihosting::debug::EXIT_SUCCESS - Rust

      [−][src]Constant cortex_m_semihosting::debug::EXIT_SUCCESS

      pub const EXIT_SUCCESS: ExitStatus = Ok(())

      Successful execution of a program.

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/debug/enum.Exception.html b/cortex_m_semihosting/debug/enum.Exception.html new file mode 100644 index 0000000..10a65d9 --- /dev/null +++ b/cortex_m_semihosting/debug/enum.Exception.html @@ -0,0 +1,36 @@ +cortex_m_semihosting::debug::Exception - Rust

      [−][src]Enum cortex_m_semihosting::debug::Exception

      pub enum Exception {
+    BranchThroughZero,
+    UndefinedInstr,
+    SoftwareInterrupt,
+    PrefetchAbort,
+    DataAbort,
+    AddressException,
+    IRQ,
+    FIQ,
+    BreakPoint,
+    WatchPoint,
+    StepComplete,
+    RunTimeErrorUnknown,
+    InternalError,
+    UserInterruption,
+    ApplicationExit,
+    StackOverflow,
+    DivisionByZero,
+    OSSpecific,
+}

      This values are taken from section 5.5.2 of +ADS Debug Target Guide (DUI0058).

      +

      + Variants

      +

      Auto Trait Implementations

      impl Send for Exception

      impl Sync for Exception

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/debug/exit.v.html b/cortex_m_semihosting/debug/exit.v.html new file mode 100644 index 0000000..bd2c853 --- /dev/null +++ b/cortex_m_semihosting/debug/exit.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.exit.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/debug/fn.exit.html b/cortex_m_semihosting/debug/fn.exit.html new file mode 100644 index 0000000..9dbe92b --- /dev/null +++ b/cortex_m_semihosting/debug/fn.exit.html @@ -0,0 +1,8 @@ +cortex_m_semihosting::debug::exit - Rust

      [−][src]Function cortex_m_semihosting::debug::exit

      pub fn exit(status: ExitStatus)

      Reports to the debugger that the execution has completed.

      +

      This call can be used to terminate QEMU session and report back success +or failure. If you need to pass more than one type of error, consider +using report_exception syscall instead.

      +

      This call should not return. However, it is possible for the debugger +to request that the application continue. In that case this call +returns normally.

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/debug/fn.report_exception.html b/cortex_m_semihosting/debug/fn.report_exception.html new file mode 100644 index 0000000..d99b83e --- /dev/null +++ b/cortex_m_semihosting/debug/fn.report_exception.html @@ -0,0 +1,11 @@ +cortex_m_semihosting::debug::report_exception - Rust

      [−][src]Function cortex_m_semihosting::debug::report_exception

      pub fn report_exception(reason: Exception)

      Report an exception to the debugger directly.

      +

      Exception handlers can use this SWI at the end of handler chains +as the default action, to indicate that the exception has not been handled.

      +

      This call should not return. However, it is possible for the debugger +to request that the application continue. In that case this call +returns normally.

      +

      Arguments

      +
        +
      • reason - A reason code reported back to the debugger.
        • +
      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/debug/index.html b/cortex_m_semihosting/debug/index.html new file mode 100644 index 0000000..7c9195f --- /dev/null +++ b/cortex_m_semihosting/debug/index.html @@ -0,0 +1,75 @@ +cortex_m_semihosting::debug - Rust

      [−][src]Module cortex_m_semihosting::debug

      Interacting with debugging agent

      +

      Example

      +

      This example will show how to terminate the QEMU session. The program +should be running under QEMU with semihosting enabled +(use -semihosting flag).

      +

      Target program:

      + +
      +#[macro_use]
+extern crate cortex_m_semihosting;
+use cortex_m_semihosting::debug::{self, EXIT_SUCCESS, EXIT_FAILURE};
+
+fn main() {
+    if 2 == 2 {
+        // report success
+        debug::exit(EXIT_SUCCESS);
+    } else {
+        // report failure
+        debug::exit(EXIT_FAILURE);
+    }
+}
      +

      Enums

      + + + + +
      Exception +

      This values are taken from section 5.5.2 of +ADS Debug Target Guide (DUI0058).

      + +

      Constants

      + + + + + + + + +
      EXIT_FAILURE +

      Unsuccessful execution of a program.

      + +
      EXIT_SUCCESS +

      Successful execution of a program.

      + +

      Functions

      + + + + + + + + +
      exit +

      Reports to the debugger that the execution has completed.

      + +
      report_exception +

      Report an exception to the debugger directly.

      + +

      Type Definitions

      + + + + +
      ExitStatus +

      Status enum for exit syscall.

      + +
      \ No newline at end of file diff --git a/cortex_m_semihosting/debug/report_exception.v.html b/cortex_m_semihosting/debug/report_exception.v.html new file mode 100644 index 0000000..249c883 --- /dev/null +++ b/cortex_m_semihosting/debug/report_exception.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.report_exception.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/debug/sidebar-items.js b/cortex_m_semihosting/debug/sidebar-items.js new file mode 100644 index 0000000..20428e1 --- /dev/null +++ b/cortex_m_semihosting/debug/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"constant":[["EXIT_FAILURE","Unsuccessful execution of a program."],["EXIT_SUCCESS","Successful execution of a program."]],"enum":[["Exception","This values are taken from section 5.5.2 of ADS Debug Target Guide (DUI0058)."]],"fn":[["exit","Reports to the debugger that the execution has completed."],["report_exception","Report an exception to the debugger directly."]],"type":[["ExitStatus","Status enum for `exit` syscall."]]}); \ No newline at end of file diff --git a/cortex_m_semihosting/debug/type.ExitStatus.html b/cortex_m_semihosting/debug/type.ExitStatus.html new file mode 100644 index 0000000..d6c2969 --- /dev/null +++ b/cortex_m_semihosting/debug/type.ExitStatus.html @@ -0,0 +1,2 @@ +cortex_m_semihosting::debug::ExitStatus - Rust

      [−][src]Type Definition cortex_m_semihosting::debug::ExitStatus

      type ExitStatus = Result<(), ()>;

      Status enum for exit syscall.

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/fn.syscall.html b/cortex_m_semihosting/fn.syscall.html new file mode 100644 index 0000000..068d052 --- /dev/null +++ b/cortex_m_semihosting/fn.syscall.html @@ -0,0 +1,2 @@ +cortex_m_semihosting::syscall - Rust

      [−][src]Function cortex_m_semihosting::syscall

      pub unsafe fn syscall<T>(nr: usize, arg: &T) -> usize

      Performs a semihosting operation, takes a pointer to an argument block

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/fn.syscall1.html b/cortex_m_semihosting/fn.syscall1.html new file mode 100644 index 0000000..1ddf29e --- /dev/null +++ b/cortex_m_semihosting/fn.syscall1.html @@ -0,0 +1,2 @@ +cortex_m_semihosting::syscall1 - Rust

      [−][src]Function cortex_m_semihosting::syscall1

      pub unsafe fn syscall1(_nr: usize, _arg: usize) -> usize

      Performs a semihosting operation, takes one integer as an argument

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/hio/HStderr.t.html b/cortex_m_semihosting/hio/HStderr.t.html new file mode 100644 index 0000000..978c0dc --- /dev/null +++ b/cortex_m_semihosting/hio/HStderr.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.HStderr.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/hio/HStdout.t.html b/cortex_m_semihosting/hio/HStdout.t.html new file mode 100644 index 0000000..309d6f6 --- /dev/null +++ b/cortex_m_semihosting/hio/HStdout.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.HStdout.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/hio/fn.hstderr.html b/cortex_m_semihosting/hio/fn.hstderr.html new file mode 100644 index 0000000..d5b5d0a --- /dev/null +++ b/cortex_m_semihosting/hio/fn.hstderr.html @@ -0,0 +1,2 @@ +cortex_m_semihosting::hio::hstderr - Rust

      [−][src]Function cortex_m_semihosting::hio::hstderr

      pub fn hstderr() -> Result<HStderr, ()>

      Construct a new handle to the host's standard error.

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/hio/fn.hstdout.html b/cortex_m_semihosting/hio/fn.hstdout.html new file mode 100644 index 0000000..9235cd9 --- /dev/null +++ b/cortex_m_semihosting/hio/fn.hstdout.html @@ -0,0 +1,2 @@ +cortex_m_semihosting::hio::hstdout - Rust

      [−][src]Function cortex_m_semihosting::hio::hstdout

      pub fn hstdout() -> Result<HStdout, ()>

      Construct a new handle to the host's standard output.

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/hio/hstderr.v.html b/cortex_m_semihosting/hio/hstderr.v.html new file mode 100644 index 0000000..08045a3 --- /dev/null +++ b/cortex_m_semihosting/hio/hstderr.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.hstderr.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/hio/hstdout.v.html b/cortex_m_semihosting/hio/hstdout.v.html new file mode 100644 index 0000000..97e8796 --- /dev/null +++ b/cortex_m_semihosting/hio/hstdout.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.hstdout.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/hio/index.html b/cortex_m_semihosting/hio/index.html new file mode 100644 index 0000000..6e34eba --- /dev/null +++ b/cortex_m_semihosting/hio/index.html @@ -0,0 +1,36 @@ +cortex_m_semihosting::hio - Rust

      [−][src]Module cortex_m_semihosting::hio

      Host I/O

      +

      Structs

      + + + + + + + + +
      HStderr +

      Host's standard error

      + +
      HStdout +

      Host's standard output

      + +

      Functions

      + + + + + + + + +
      hstderr +

      Construct a new handle to the host's standard error.

      + +
      hstdout +

      Construct a new handle to the host's standard output.

      + +
      \ No newline at end of file diff --git a/cortex_m_semihosting/hio/sidebar-items.js b/cortex_m_semihosting/hio/sidebar-items.js new file mode 100644 index 0000000..84c54e4 --- /dev/null +++ b/cortex_m_semihosting/hio/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"fn":[["hstderr","Construct a new handle to the host's standard error."],["hstdout","Construct a new handle to the host's standard output."]],"struct":[["HStderr","Host's standard error"],["HStdout","Host's standard output"]]}); \ No newline at end of file diff --git a/cortex_m_semihosting/hio/struct.HStderr.html b/cortex_m_semihosting/hio/struct.HStderr.html new file mode 100644 index 0000000..91eeab7 --- /dev/null +++ b/cortex_m_semihosting/hio/struct.HStderr.html @@ -0,0 +1,18 @@ +cortex_m_semihosting::hio::HStderr - Rust

      [−][src]Struct cortex_m_semihosting::hio::HStderr

      pub struct HStderr { /* fields omitted */ }

      Host's standard error

      +

      Methods

      impl HStderr
      [src]

      Attempts to write an entire buffer into this sink

      +

      Trait Implementations

      impl Write for HStderr
      [src]

      Writes a slice of bytes into this writer, returning whether the write succeeded. Read more

      +

      Writes a [char] into this writer, returning whether the write succeeded. Read more

      +

      Glue for usage of the [write!] macro with implementors of this trait. Read more

      +

      Auto Trait Implementations

      impl Send for HStderr

      impl Sync for HStderr

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/hio/struct.HStdout.html b/cortex_m_semihosting/hio/struct.HStdout.html new file mode 100644 index 0000000..e6c49fe --- /dev/null +++ b/cortex_m_semihosting/hio/struct.HStdout.html @@ -0,0 +1,18 @@ +cortex_m_semihosting::hio::HStdout - Rust

      [−][src]Struct cortex_m_semihosting::hio::HStdout

      pub struct HStdout { /* fields omitted */ }

      Host's standard output

      +

      Methods

      impl HStdout
      [src]

      Attempts to write an entire buffer into this sink

      +

      Trait Implementations

      impl Write for HStdout
      [src]

      Writes a slice of bytes into this writer, returning whether the write succeeded. Read more

      +

      Writes a [char] into this writer, returning whether the write succeeded. Read more

      +

      Glue for usage of the [write!] macro with implementors of this trait. Read more

      +

      Auto Trait Implementations

      impl Send for HStdout

      impl Sync for HStdout

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/index.html b/cortex_m_semihosting/index.html new file mode 100644 index 0000000..176861c --- /dev/null +++ b/cortex_m_semihosting/index.html @@ -0,0 +1,162 @@ +cortex_m_semihosting - Rust

      [−][src]Crate cortex_m_semihosting

      Semihosting for ARM Cortex-M processors

      +

      What is semihosting?

      +

      "Semihosting is a mechanism that enables code running on an ARM target to communicate and use +the Input/Output facilities on a host computer that is running a debugger." - ARM

      +

      Interface

      +

      This crate provides implementations of +core::fmt::Write, so you can use it, +in conjunction with +core::format_args! or the write! macro, for user-friendly construction and printing of formatted strings.

      +

      Since semihosting operations are modeled as system calls, this crate exposes an untyped +syscall! interface just like the sc crate does.

      +

      Forewarning

      +

      Semihosting operations are very slow. Like, each WRITE operation can take hundreds of +milliseconds.

      +

      Example

      Using hio::HStdout

      +

      This example will demonstrate how to print formatted strings.

      + +
      +extern crate cortex_m_semihosting;
+
+use cortex_m_semihosting::hio;
+use core::fmt::Write;
+
+// This function will be called by the application
+fn print() -> Result<(), core::fmt::Error> {
+    let mut stdout = match hio::hstdout() {
+        Ok(fd) => fd,
+        Err(()) => return Err(core::fmt::Error),
+    };
+
+    let language = "Rust";
+    let ranking = 1;
+
+    write!(stdout, "{} on embedded is #{}!", language, ranking)?;
+
+    Ok(())
+}
      +

      On the host side:

      +
      $ openocd -f $INTERFACE -f $TARGET -l /tmp/openocd.log
+Open On-Chip Debugger 0.9.0 (2016-04-27-23:18)
+Licensed under GNU GPL v2
+For bug reports, read
+        http://openocd.org/doc/doxygen/bugs.html
+# the command will block at this point
+
      +

      The OpenOCD logs will be redirected to /tmp/openocd.log. You can view those logs in "real +time" using tail

      +
      $ tail -f /tmp/openocd.log
+Info : Unable to match requested speed 1000 kHz, using 950 kHz
+Info : Unable to match requested speed 1000 kHz, using 950 kHz
+Info : clock speed 950 kHz
+Info : STLINK v1 JTAG v11 API v2 SWIM v0 VID 0x0483 PID 0x3744
+Info : using stlink api v2
+Info : nrf51.cpu: hardware has 4 breakpoints, 2 watchpoints
+
      +

      Alternatively you could omit the -l flag from the openocd call, and the tail -f command +but the OpenOCD output will have intermingled in it logs from its normal operation.

      +

      Then, we run the program:

      +
      $ arm-none-eabi-gdb hello-world
+(gdb) # Connect to OpenOCD
+(gdb) target remote :3333
+
+(gdb) # Enable OpenOCD's semihosting support
+(gdb) monitor arm semihosting enable
+
+(gdb) # Flash the program
+(gdb) load
+
+(gdb) # Run the program
+(gdb) continue
+
      +

      And you'll see the output under OpenOCD's terminal

      +
      # openocd -f $INTERFACE -f $TARGET -l /tmp/openocd.log
+(..)
+Rust on embedded is #1!
+
      +

      Using the syscall interface

      +

      This example will show how to print "Hello, world!" on the host.

      +

      Target program:

      + +
      +extern crate cortex_m_semihosting;
+
+// This function will be called by the application
+fn print() {
+    // File descriptor (on the host)
+    const STDOUT: usize = 1; // NOTE the host stdout may not always be fd 1
+    static MSG: &'static [u8] = b"Hello, world!\n";
+
+    // Signature: fn write(fd: usize, ptr: *const u8, len: usize) -> usize
+    let r = unsafe { syscall!(WRITE, STDOUT, MSG.as_ptr(), MSG.len()) };
+}
      +

      Output and monitoring proceed as in the above example.

      +

      Optional features

      inline-asm

      +

      When this feature is enabled semihosting is implemented using inline assembly (asm!) and +compiling this crate requires nightly.

      +

      When this feature is disabled semihosting is implemented using FFI calls into an external +assembly file and compiling this crate works on stable and beta.

      +

      Reference

      +

      For documentation about the semihosting operations, check:

      +

      'Chapter 8 - Semihosting' of the 'ARM Compiler toolchain Version 5.0' +manual.

      +

      Modules

      + + + + + + + + + + + + +
      debug +

      Interacting with debugging agent

      + +
      hio +

      Host I/O

      + +
      nr +

      Semihosting operations

      + +

      Macros

      + + + + + + + + +
      syscall +

      Variable argument version of syscall

      + +
      syscall1 +

      Macro version of syscall1

      + +

      Functions

      + + + + + + + + +
      syscall⚠ +

      Performs a semihosting operation, takes a pointer to an argument block

      + +
      syscall1⚠ +

      Performs a semihosting operation, takes one integer as an argument

      + +
      \ No newline at end of file diff --git a/cortex_m_semihosting/macro.syscall!.html b/cortex_m_semihosting/macro.syscall!.html new file mode 100644 index 0000000..d07c264 --- /dev/null +++ b/cortex_m_semihosting/macro.syscall!.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.syscall.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/macro.syscall.html b/cortex_m_semihosting/macro.syscall.html new file mode 100644 index 0000000..a433d92 --- /dev/null +++ b/cortex_m_semihosting/macro.syscall.html @@ -0,0 +1,10 @@ +cortex_m_semihosting::syscall - Rust

      [−][src]Macro cortex_m_semihosting::syscall

      +macro_rules! syscall {
+    ($nr:ident) => { ... };
+    ($nr:ident, $a1:expr) => { ... };
+    ($nr:ident, $a1:expr, $a2:expr) => { ... };
+    ($nr:ident, $a1:expr, $a2:expr, $a3:expr) => { ... };
+    ($nr:ident, $a1:expr, $a2:expr, $a3:expr, $a4:expr) => { ... };
+}
      +

      Variable argument version of syscall

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/macro.syscall1!.html b/cortex_m_semihosting/macro.syscall1!.html new file mode 100644 index 0000000..85af6b1 --- /dev/null +++ b/cortex_m_semihosting/macro.syscall1!.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.syscall1.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/macro.syscall1.html b/cortex_m_semihosting/macro.syscall1.html new file mode 100644 index 0000000..dc12b26 --- /dev/null +++ b/cortex_m_semihosting/macro.syscall1.html @@ -0,0 +1,6 @@ +cortex_m_semihosting::syscall1 - Rust

      [−][src]Macro cortex_m_semihosting::syscall1

      +macro_rules! syscall1 {
+    ($nr:ident, $a1:expr) => { ... };
+}
      +

      Macro version of syscall1

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/CLOCK.v.html b/cortex_m_semihosting/nr/CLOCK.v.html new file mode 100644 index 0000000..fc94f35 --- /dev/null +++ b/cortex_m_semihosting/nr/CLOCK.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.CLOCK.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/CLOSE.v.html b/cortex_m_semihosting/nr/CLOSE.v.html new file mode 100644 index 0000000..6e3e5d7 --- /dev/null +++ b/cortex_m_semihosting/nr/CLOSE.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.CLOSE.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/ELAPSED.v.html b/cortex_m_semihosting/nr/ELAPSED.v.html new file mode 100644 index 0000000..e83012c --- /dev/null +++ b/cortex_m_semihosting/nr/ELAPSED.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.ELAPSED.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/ENTER_SVC.v.html b/cortex_m_semihosting/nr/ENTER_SVC.v.html new file mode 100644 index 0000000..ff3cb5b --- /dev/null +++ b/cortex_m_semihosting/nr/ENTER_SVC.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.ENTER_SVC.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/ERRNO.v.html b/cortex_m_semihosting/nr/ERRNO.v.html new file mode 100644 index 0000000..59229b6 --- /dev/null +++ b/cortex_m_semihosting/nr/ERRNO.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.ERRNO.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/FLEN.v.html b/cortex_m_semihosting/nr/FLEN.v.html new file mode 100644 index 0000000..de0b0b4 --- /dev/null +++ b/cortex_m_semihosting/nr/FLEN.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.FLEN.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/GET_CMDLINE.v.html b/cortex_m_semihosting/nr/GET_CMDLINE.v.html new file mode 100644 index 0000000..87348d8 --- /dev/null +++ b/cortex_m_semihosting/nr/GET_CMDLINE.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.GET_CMDLINE.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/HEAPINFO.v.html b/cortex_m_semihosting/nr/HEAPINFO.v.html new file mode 100644 index 0000000..3ba63a8 --- /dev/null +++ b/cortex_m_semihosting/nr/HEAPINFO.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.HEAPINFO.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/ISERROR.v.html b/cortex_m_semihosting/nr/ISERROR.v.html new file mode 100644 index 0000000..92c63d0 --- /dev/null +++ b/cortex_m_semihosting/nr/ISERROR.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.ISERROR.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/ISTTY.v.html b/cortex_m_semihosting/nr/ISTTY.v.html new file mode 100644 index 0000000..869d353 --- /dev/null +++ b/cortex_m_semihosting/nr/ISTTY.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.ISTTY.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/OPEN.v.html b/cortex_m_semihosting/nr/OPEN.v.html new file mode 100644 index 0000000..4c374b6 --- /dev/null +++ b/cortex_m_semihosting/nr/OPEN.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.OPEN.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/READ.v.html b/cortex_m_semihosting/nr/READ.v.html new file mode 100644 index 0000000..4eeb6a7 --- /dev/null +++ b/cortex_m_semihosting/nr/READ.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.READ.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/READC.v.html b/cortex_m_semihosting/nr/READC.v.html new file mode 100644 index 0000000..9c0ec31 --- /dev/null +++ b/cortex_m_semihosting/nr/READC.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.READC.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/REMOVE.v.html b/cortex_m_semihosting/nr/REMOVE.v.html new file mode 100644 index 0000000..d1d0032 --- /dev/null +++ b/cortex_m_semihosting/nr/REMOVE.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.REMOVE.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/RENAME.v.html b/cortex_m_semihosting/nr/RENAME.v.html new file mode 100644 index 0000000..bc19680 --- /dev/null +++ b/cortex_m_semihosting/nr/RENAME.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.RENAME.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/REPORT_EXCEPTION.v.html b/cortex_m_semihosting/nr/REPORT_EXCEPTION.v.html new file mode 100644 index 0000000..779a3ef --- /dev/null +++ b/cortex_m_semihosting/nr/REPORT_EXCEPTION.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.REPORT_EXCEPTION.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/SEEK.v.html b/cortex_m_semihosting/nr/SEEK.v.html new file mode 100644 index 0000000..e6da56e --- /dev/null +++ b/cortex_m_semihosting/nr/SEEK.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.SEEK.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/SYSTEM.v.html b/cortex_m_semihosting/nr/SYSTEM.v.html new file mode 100644 index 0000000..1060d32 --- /dev/null +++ b/cortex_m_semihosting/nr/SYSTEM.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.SYSTEM.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/TICKFREQ.v.html b/cortex_m_semihosting/nr/TICKFREQ.v.html new file mode 100644 index 0000000..335b717 --- /dev/null +++ b/cortex_m_semihosting/nr/TICKFREQ.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.TICKFREQ.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/TIME.v.html b/cortex_m_semihosting/nr/TIME.v.html new file mode 100644 index 0000000..58f62ff --- /dev/null +++ b/cortex_m_semihosting/nr/TIME.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.TIME.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/TMPNAM.v.html b/cortex_m_semihosting/nr/TMPNAM.v.html new file mode 100644 index 0000000..45ae619 --- /dev/null +++ b/cortex_m_semihosting/nr/TMPNAM.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.TMPNAM.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/WRITE.v.html b/cortex_m_semihosting/nr/WRITE.v.html new file mode 100644 index 0000000..232864c --- /dev/null +++ b/cortex_m_semihosting/nr/WRITE.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.WRITE.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/WRITE0.v.html b/cortex_m_semihosting/nr/WRITE0.v.html new file mode 100644 index 0000000..e635771 --- /dev/null +++ b/cortex_m_semihosting/nr/WRITE0.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.WRITE0.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/WRITEC.v.html b/cortex_m_semihosting/nr/WRITEC.v.html new file mode 100644 index 0000000..ac6ba56 --- /dev/null +++ b/cortex_m_semihosting/nr/WRITEC.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.WRITEC.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.CLOCK.html b/cortex_m_semihosting/nr/constant.CLOCK.html new file mode 100644 index 0000000..7b8a4b2 --- /dev/null +++ b/cortex_m_semihosting/nr/constant.CLOCK.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::CLOCK - Rust

      [−][src]Constant cortex_m_semihosting::nr::CLOCK

      pub const CLOCK: usize = 16
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.CLOSE.html b/cortex_m_semihosting/nr/constant.CLOSE.html new file mode 100644 index 0000000..9be2647 --- /dev/null +++ b/cortex_m_semihosting/nr/constant.CLOSE.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::CLOSE - Rust

      [−][src]Constant cortex_m_semihosting::nr::CLOSE

      pub const CLOSE: usize = 2
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.ELAPSED.html b/cortex_m_semihosting/nr/constant.ELAPSED.html new file mode 100644 index 0000000..1ab1508 --- /dev/null +++ b/cortex_m_semihosting/nr/constant.ELAPSED.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::ELAPSED - Rust

      [−][src]Constant cortex_m_semihosting::nr::ELAPSED

      pub const ELAPSED: usize = 48
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.ENTER_SVC.html b/cortex_m_semihosting/nr/constant.ENTER_SVC.html new file mode 100644 index 0000000..389e9e7 --- /dev/null +++ b/cortex_m_semihosting/nr/constant.ENTER_SVC.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::ENTER_SVC - Rust

      [−][src]Constant cortex_m_semihosting::nr::ENTER_SVC

      pub const ENTER_SVC: usize = 23
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.ERRNO.html b/cortex_m_semihosting/nr/constant.ERRNO.html new file mode 100644 index 0000000..3b28467 --- /dev/null +++ b/cortex_m_semihosting/nr/constant.ERRNO.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::ERRNO - Rust

      [−][src]Constant cortex_m_semihosting::nr::ERRNO

      pub const ERRNO: usize = 19
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.FLEN.html b/cortex_m_semihosting/nr/constant.FLEN.html new file mode 100644 index 0000000..7ddfe3b --- /dev/null +++ b/cortex_m_semihosting/nr/constant.FLEN.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::FLEN - Rust

      [−][src]Constant cortex_m_semihosting::nr::FLEN

      pub const FLEN: usize = 12
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.GET_CMDLINE.html b/cortex_m_semihosting/nr/constant.GET_CMDLINE.html new file mode 100644 index 0000000..3bee925 --- /dev/null +++ b/cortex_m_semihosting/nr/constant.GET_CMDLINE.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::GET_CMDLINE - Rust

      [−][src]Constant cortex_m_semihosting::nr::GET_CMDLINE

      pub const GET_CMDLINE: usize = 21
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.HEAPINFO.html b/cortex_m_semihosting/nr/constant.HEAPINFO.html new file mode 100644 index 0000000..a1cbce4 --- /dev/null +++ b/cortex_m_semihosting/nr/constant.HEAPINFO.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::HEAPINFO - Rust

      [−][src]Constant cortex_m_semihosting::nr::HEAPINFO

      pub const HEAPINFO: usize = 22
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.ISERROR.html b/cortex_m_semihosting/nr/constant.ISERROR.html new file mode 100644 index 0000000..ea0bb75 --- /dev/null +++ b/cortex_m_semihosting/nr/constant.ISERROR.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::ISERROR - Rust

      [−][src]Constant cortex_m_semihosting::nr::ISERROR

      pub const ISERROR: usize = 8
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.ISTTY.html b/cortex_m_semihosting/nr/constant.ISTTY.html new file mode 100644 index 0000000..7d773f9 --- /dev/null +++ b/cortex_m_semihosting/nr/constant.ISTTY.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::ISTTY - Rust

      [−][src]Constant cortex_m_semihosting::nr::ISTTY

      pub const ISTTY: usize = 9
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.OPEN.html b/cortex_m_semihosting/nr/constant.OPEN.html new file mode 100644 index 0000000..77b74ec --- /dev/null +++ b/cortex_m_semihosting/nr/constant.OPEN.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::OPEN - Rust

      [−][src]Constant cortex_m_semihosting::nr::OPEN

      pub const OPEN: usize = 1
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.READ.html b/cortex_m_semihosting/nr/constant.READ.html new file mode 100644 index 0000000..e538deb --- /dev/null +++ b/cortex_m_semihosting/nr/constant.READ.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::READ - Rust

      [−][src]Constant cortex_m_semihosting::nr::READ

      pub const READ: usize = 6
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.READC.html b/cortex_m_semihosting/nr/constant.READC.html new file mode 100644 index 0000000..dcbaa4d --- /dev/null +++ b/cortex_m_semihosting/nr/constant.READC.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::READC - Rust

      [−][src]Constant cortex_m_semihosting::nr::READC

      pub const READC: usize = 7
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.REMOVE.html b/cortex_m_semihosting/nr/constant.REMOVE.html new file mode 100644 index 0000000..d7d89d6 --- /dev/null +++ b/cortex_m_semihosting/nr/constant.REMOVE.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::REMOVE - Rust

      [−][src]Constant cortex_m_semihosting::nr::REMOVE

      pub const REMOVE: usize = 14
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.RENAME.html b/cortex_m_semihosting/nr/constant.RENAME.html new file mode 100644 index 0000000..cf32f5b --- /dev/null +++ b/cortex_m_semihosting/nr/constant.RENAME.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::RENAME - Rust

      [−][src]Constant cortex_m_semihosting::nr::RENAME

      pub const RENAME: usize = 15
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.REPORT_EXCEPTION.html b/cortex_m_semihosting/nr/constant.REPORT_EXCEPTION.html new file mode 100644 index 0000000..d4bceba --- /dev/null +++ b/cortex_m_semihosting/nr/constant.REPORT_EXCEPTION.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::REPORT_EXCEPTION - Rust

      [−][src]Constant cortex_m_semihosting::nr::REPORT_EXCEPTION

      pub const REPORT_EXCEPTION: usize = 24
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.SEEK.html b/cortex_m_semihosting/nr/constant.SEEK.html new file mode 100644 index 0000000..08bb7ee --- /dev/null +++ b/cortex_m_semihosting/nr/constant.SEEK.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::SEEK - Rust

      [−][src]Constant cortex_m_semihosting::nr::SEEK

      pub const SEEK: usize = 10
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.SYSTEM.html b/cortex_m_semihosting/nr/constant.SYSTEM.html new file mode 100644 index 0000000..fd0039d --- /dev/null +++ b/cortex_m_semihosting/nr/constant.SYSTEM.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::SYSTEM - Rust

      [−][src]Constant cortex_m_semihosting::nr::SYSTEM

      pub const SYSTEM: usize = 18
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.TICKFREQ.html b/cortex_m_semihosting/nr/constant.TICKFREQ.html new file mode 100644 index 0000000..1687c04 --- /dev/null +++ b/cortex_m_semihosting/nr/constant.TICKFREQ.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::TICKFREQ - Rust

      [−][src]Constant cortex_m_semihosting::nr::TICKFREQ

      pub const TICKFREQ: usize = 49
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.TIME.html b/cortex_m_semihosting/nr/constant.TIME.html new file mode 100644 index 0000000..86e549a --- /dev/null +++ b/cortex_m_semihosting/nr/constant.TIME.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::TIME - Rust

      [−][src]Constant cortex_m_semihosting::nr::TIME

      pub const TIME: usize = 17
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.TMPNAM.html b/cortex_m_semihosting/nr/constant.TMPNAM.html new file mode 100644 index 0000000..981644d --- /dev/null +++ b/cortex_m_semihosting/nr/constant.TMPNAM.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::TMPNAM - Rust

      [−][src]Constant cortex_m_semihosting::nr::TMPNAM

      pub const TMPNAM: usize = 13
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.WRITE.html b/cortex_m_semihosting/nr/constant.WRITE.html new file mode 100644 index 0000000..fd4ab87 --- /dev/null +++ b/cortex_m_semihosting/nr/constant.WRITE.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::WRITE - Rust

      [−][src]Constant cortex_m_semihosting::nr::WRITE

      pub const WRITE: usize = 5
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.WRITE0.html b/cortex_m_semihosting/nr/constant.WRITE0.html new file mode 100644 index 0000000..2ffb7ea --- /dev/null +++ b/cortex_m_semihosting/nr/constant.WRITE0.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::WRITE0 - Rust

      [−][src]Constant cortex_m_semihosting::nr::WRITE0

      pub const WRITE0: usize = 4
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/constant.WRITEC.html b/cortex_m_semihosting/nr/constant.WRITEC.html new file mode 100644 index 0000000..3bdcd5f --- /dev/null +++ b/cortex_m_semihosting/nr/constant.WRITEC.html @@ -0,0 +1 @@ +cortex_m_semihosting::nr::WRITEC - Rust

      [−][src]Constant cortex_m_semihosting::nr::WRITEC

      pub const WRITEC: usize = 3
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/index.html b/cortex_m_semihosting/nr/index.html new file mode 100644 index 0000000..947966b --- /dev/null +++ b/cortex_m_semihosting/nr/index.html @@ -0,0 +1,180 @@ +cortex_m_semihosting::nr - Rust

      [−][src]Module cortex_m_semihosting::nr

      Semihosting operations

      +

      Modules

      + + + + +
      open +

      Values for the mode parameter of the OPEN syscall.

      + +

      Constants

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      CLOCK + +
      CLOSE + +
      ELAPSED + +
      ENTER_SVC + +
      ERRNO + +
      FLEN + +
      GET_CMDLINE + +
      HEAPINFO + +
      ISERROR + +
      ISTTY + +
      OPEN + +
      READ + +
      READC + +
      REMOVE + +
      RENAME + +
      REPORT_EXCEPTION + +
      SEEK + +
      SYSTEM + +
      TICKFREQ + +
      TIME + +
      TMPNAM + +
      WRITE + +
      WRITE0 + +
      WRITEC + +
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/R.v.html b/cortex_m_semihosting/nr/open/R.v.html new file mode 100644 index 0000000..ffcad0f --- /dev/null +++ b/cortex_m_semihosting/nr/open/R.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.R.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/RW.v.html b/cortex_m_semihosting/nr/open/RW.v.html new file mode 100644 index 0000000..45e7529 --- /dev/null +++ b/cortex_m_semihosting/nr/open/RW.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.RW.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/RW_APPEND.v.html b/cortex_m_semihosting/nr/open/RW_APPEND.v.html new file mode 100644 index 0000000..5f05df4 --- /dev/null +++ b/cortex_m_semihosting/nr/open/RW_APPEND.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.RW_APPEND.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/RW_APPEND_BINARY.v.html b/cortex_m_semihosting/nr/open/RW_APPEND_BINARY.v.html new file mode 100644 index 0000000..78c7330 --- /dev/null +++ b/cortex_m_semihosting/nr/open/RW_APPEND_BINARY.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.RW_APPEND_BINARY.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/RW_BINARY.v.html b/cortex_m_semihosting/nr/open/RW_BINARY.v.html new file mode 100644 index 0000000..08108e8 --- /dev/null +++ b/cortex_m_semihosting/nr/open/RW_BINARY.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.RW_BINARY.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/RW_TRUNC.v.html b/cortex_m_semihosting/nr/open/RW_TRUNC.v.html new file mode 100644 index 0000000..ca9a7fc --- /dev/null +++ b/cortex_m_semihosting/nr/open/RW_TRUNC.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.RW_TRUNC.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/RW_TRUNC_BINARY.v.html b/cortex_m_semihosting/nr/open/RW_TRUNC_BINARY.v.html new file mode 100644 index 0000000..248b54d --- /dev/null +++ b/cortex_m_semihosting/nr/open/RW_TRUNC_BINARY.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.RW_TRUNC_BINARY.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/R_BINARY.v.html b/cortex_m_semihosting/nr/open/R_BINARY.v.html new file mode 100644 index 0000000..a97914b --- /dev/null +++ b/cortex_m_semihosting/nr/open/R_BINARY.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.R_BINARY.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/W_APPEND.v.html b/cortex_m_semihosting/nr/open/W_APPEND.v.html new file mode 100644 index 0000000..d91abfb --- /dev/null +++ b/cortex_m_semihosting/nr/open/W_APPEND.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.W_APPEND.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/W_APPEND_BINARY.v.html b/cortex_m_semihosting/nr/open/W_APPEND_BINARY.v.html new file mode 100644 index 0000000..bcc93db --- /dev/null +++ b/cortex_m_semihosting/nr/open/W_APPEND_BINARY.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.W_APPEND_BINARY.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/W_TRUNC.v.html b/cortex_m_semihosting/nr/open/W_TRUNC.v.html new file mode 100644 index 0000000..7ea1a71 --- /dev/null +++ b/cortex_m_semihosting/nr/open/W_TRUNC.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.W_TRUNC.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/W_TRUNC_BINARY.v.html b/cortex_m_semihosting/nr/open/W_TRUNC_BINARY.v.html new file mode 100644 index 0000000..6527609 --- /dev/null +++ b/cortex_m_semihosting/nr/open/W_TRUNC_BINARY.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to constant.W_TRUNC_BINARY.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/constant.R.html b/cortex_m_semihosting/nr/open/constant.R.html new file mode 100644 index 0000000..cb976b9 --- /dev/null +++ b/cortex_m_semihosting/nr/open/constant.R.html @@ -0,0 +1,2 @@ +cortex_m_semihosting::nr::open::R - Rust

      [−][src]Constant cortex_m_semihosting::nr::open::R

      pub const R: usize = 0

      Mode corresponding to fopen "r" mode.

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/constant.RW.html b/cortex_m_semihosting/nr/open/constant.RW.html new file mode 100644 index 0000000..5a627c0 --- /dev/null +++ b/cortex_m_semihosting/nr/open/constant.RW.html @@ -0,0 +1,2 @@ +cortex_m_semihosting::nr::open::RW - Rust

      [−][src]Constant cortex_m_semihosting::nr::open::RW

      pub const RW: usize = 2

      Mode corresponding to fopen "r+" mode.

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/constant.RW_APPEND.html b/cortex_m_semihosting/nr/open/constant.RW_APPEND.html new file mode 100644 index 0000000..cf7545e --- /dev/null +++ b/cortex_m_semihosting/nr/open/constant.RW_APPEND.html @@ -0,0 +1,2 @@ +cortex_m_semihosting::nr::open::RW_APPEND - Rust

      [−][src]Constant cortex_m_semihosting::nr::open::RW_APPEND

      pub const RW_APPEND: usize = 10

      Mode corresponding to fopen "a+" mode.

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/constant.RW_APPEND_BINARY.html b/cortex_m_semihosting/nr/open/constant.RW_APPEND_BINARY.html new file mode 100644 index 0000000..48e4f7b --- /dev/null +++ b/cortex_m_semihosting/nr/open/constant.RW_APPEND_BINARY.html @@ -0,0 +1,2 @@ +cortex_m_semihosting::nr::open::RW_APPEND_BINARY - Rust

      [−][src]Constant cortex_m_semihosting::nr::open::RW_APPEND_BINARY

      pub const RW_APPEND_BINARY: usize = 11

      Mode corresponding to fopen "a+b" mode.

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/constant.RW_BINARY.html b/cortex_m_semihosting/nr/open/constant.RW_BINARY.html new file mode 100644 index 0000000..20454f7 --- /dev/null +++ b/cortex_m_semihosting/nr/open/constant.RW_BINARY.html @@ -0,0 +1,2 @@ +cortex_m_semihosting::nr::open::RW_BINARY - Rust

      [−][src]Constant cortex_m_semihosting::nr::open::RW_BINARY

      pub const RW_BINARY: usize = 3

      Mode corresponding to fopen "r+b" mode.

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/constant.RW_TRUNC.html b/cortex_m_semihosting/nr/open/constant.RW_TRUNC.html new file mode 100644 index 0000000..61ed203 --- /dev/null +++ b/cortex_m_semihosting/nr/open/constant.RW_TRUNC.html @@ -0,0 +1,2 @@ +cortex_m_semihosting::nr::open::RW_TRUNC - Rust

      [−][src]Constant cortex_m_semihosting::nr::open::RW_TRUNC

      pub const RW_TRUNC: usize = 6

      Mode corresponding to fopen "w+" mode.

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/constant.RW_TRUNC_BINARY.html b/cortex_m_semihosting/nr/open/constant.RW_TRUNC_BINARY.html new file mode 100644 index 0000000..cab5909 --- /dev/null +++ b/cortex_m_semihosting/nr/open/constant.RW_TRUNC_BINARY.html @@ -0,0 +1,2 @@ +cortex_m_semihosting::nr::open::RW_TRUNC_BINARY - Rust

      [−][src]Constant cortex_m_semihosting::nr::open::RW_TRUNC_BINARY

      pub const RW_TRUNC_BINARY: usize = 7

      Mode corresponding to fopen "w+b" mode.

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/constant.R_BINARY.html b/cortex_m_semihosting/nr/open/constant.R_BINARY.html new file mode 100644 index 0000000..05d91aa --- /dev/null +++ b/cortex_m_semihosting/nr/open/constant.R_BINARY.html @@ -0,0 +1,2 @@ +cortex_m_semihosting::nr::open::R_BINARY - Rust

      [−][src]Constant cortex_m_semihosting::nr::open::R_BINARY

      pub const R_BINARY: usize = 1

      Mode corresponding to fopen "rb" mode.

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/constant.W_APPEND.html b/cortex_m_semihosting/nr/open/constant.W_APPEND.html new file mode 100644 index 0000000..6fb85d8 --- /dev/null +++ b/cortex_m_semihosting/nr/open/constant.W_APPEND.html @@ -0,0 +1,2 @@ +cortex_m_semihosting::nr::open::W_APPEND - Rust

      [−][src]Constant cortex_m_semihosting::nr::open::W_APPEND

      pub const W_APPEND: usize = 8

      Mode corresponding to fopen "a" mode.

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/constant.W_APPEND_BINARY.html b/cortex_m_semihosting/nr/open/constant.W_APPEND_BINARY.html new file mode 100644 index 0000000..04bdc63 --- /dev/null +++ b/cortex_m_semihosting/nr/open/constant.W_APPEND_BINARY.html @@ -0,0 +1,2 @@ +cortex_m_semihosting::nr::open::W_APPEND_BINARY - Rust

      [−][src]Constant cortex_m_semihosting::nr::open::W_APPEND_BINARY

      pub const W_APPEND_BINARY: usize = 9

      Mode corresponding to fopen "ab" mode.

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/constant.W_TRUNC.html b/cortex_m_semihosting/nr/open/constant.W_TRUNC.html new file mode 100644 index 0000000..acc23ba --- /dev/null +++ b/cortex_m_semihosting/nr/open/constant.W_TRUNC.html @@ -0,0 +1,2 @@ +cortex_m_semihosting::nr::open::W_TRUNC - Rust

      [−][src]Constant cortex_m_semihosting::nr::open::W_TRUNC

      pub const W_TRUNC: usize = 4

      Mode corresponding to fopen "w" mode.

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/constant.W_TRUNC_BINARY.html b/cortex_m_semihosting/nr/open/constant.W_TRUNC_BINARY.html new file mode 100644 index 0000000..85fdf9d --- /dev/null +++ b/cortex_m_semihosting/nr/open/constant.W_TRUNC_BINARY.html @@ -0,0 +1,2 @@ +cortex_m_semihosting::nr::open::W_TRUNC_BINARY - Rust

      [−][src]Constant cortex_m_semihosting::nr::open::W_TRUNC_BINARY

      pub const W_TRUNC_BINARY: usize = 5

      Mode corresponding to fopen "wb" mode.

      +
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/index.html b/cortex_m_semihosting/nr/open/index.html new file mode 100644 index 0000000..cc2fd28 --- /dev/null +++ b/cortex_m_semihosting/nr/open/index.html @@ -0,0 +1,99 @@ +cortex_m_semihosting::nr::open - Rust

      [−][src]Module cortex_m_semihosting::nr::open

      Values for the mode parameter of the OPEN syscall.

      +

      Constants

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      R +

      Mode corresponding to fopen "r" mode.

      + +
      RW +

      Mode corresponding to fopen "r+" mode.

      + +
      RW_APPEND +

      Mode corresponding to fopen "a+" mode.

      + +
      RW_APPEND_BINARY +

      Mode corresponding to fopen "a+b" mode.

      + +
      RW_BINARY +

      Mode corresponding to fopen "r+b" mode.

      + +
      RW_TRUNC +

      Mode corresponding to fopen "w+" mode.

      + +
      RW_TRUNC_BINARY +

      Mode corresponding to fopen "w+b" mode.

      + +
      R_BINARY +

      Mode corresponding to fopen "rb" mode.

      + +
      W_APPEND +

      Mode corresponding to fopen "a" mode.

      + +
      W_APPEND_BINARY +

      Mode corresponding to fopen "ab" mode.

      + +
      W_TRUNC +

      Mode corresponding to fopen "w" mode.

      + +
      W_TRUNC_BINARY +

      Mode corresponding to fopen "wb" mode.

      + +
      \ No newline at end of file diff --git a/cortex_m_semihosting/nr/open/sidebar-items.js b/cortex_m_semihosting/nr/open/sidebar-items.js new file mode 100644 index 0000000..249f2b8 --- /dev/null +++ b/cortex_m_semihosting/nr/open/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"constant":[["R","Mode corresponding to fopen \"r\" mode."],["RW","Mode corresponding to fopen \"r+\" mode."],["RW_APPEND","Mode corresponding to fopen \"a+\" mode."],["RW_APPEND_BINARY","Mode corresponding to fopen \"a+b\" mode."],["RW_BINARY","Mode corresponding to fopen \"r+b\" mode."],["RW_TRUNC","Mode corresponding to fopen \"w+\" mode."],["RW_TRUNC_BINARY","Mode corresponding to fopen \"w+b\" mode."],["R_BINARY","Mode corresponding to fopen \"rb\" mode."],["W_APPEND","Mode corresponding to fopen \"a\" mode."],["W_APPEND_BINARY","Mode corresponding to fopen \"ab\" mode."],["W_TRUNC","Mode corresponding to fopen \"w\" mode."],["W_TRUNC_BINARY","Mode corresponding to fopen \"wb\" mode."]]}); \ No newline at end of file diff --git a/cortex_m_semihosting/nr/sidebar-items.js b/cortex_m_semihosting/nr/sidebar-items.js new file mode 100644 index 0000000..f6aaba9 --- /dev/null +++ b/cortex_m_semihosting/nr/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"constant":[["CLOCK",""],["CLOSE",""],["ELAPSED",""],["ENTER_SVC",""],["ERRNO",""],["FLEN",""],["GET_CMDLINE",""],["HEAPINFO",""],["ISERROR",""],["ISTTY",""],["OPEN",""],["READ",""],["READC",""],["REMOVE",""],["RENAME",""],["REPORT_EXCEPTION",""],["SEEK",""],["SYSTEM",""],["TICKFREQ",""],["TIME",""],["TMPNAM",""],["WRITE",""],["WRITE0",""],["WRITEC",""]],"mod":[["open","Values for the mode parameter of the OPEN syscall."]]}); \ No newline at end of file diff --git a/cortex_m_semihosting/sidebar-items.js b/cortex_m_semihosting/sidebar-items.js new file mode 100644 index 0000000..867df45 --- /dev/null +++ b/cortex_m_semihosting/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"fn":[["syscall","Performs a semihosting operation, takes a pointer to an argument block"],["syscall1","Performs a semihosting operation, takes one integer as an argument"]],"macro":[["syscall","Variable argument version of `syscall`"],["syscall1","Macro version of `syscall1`"]],"mod":[["debug","Interacting with debugging agent"],["hio","Host I/O"],["nr","Semihosting operations"]]}); \ No newline at end of file diff --git a/cortex_m_semihosting/syscall.m.html b/cortex_m_semihosting/syscall.m.html new file mode 100644 index 0000000..d07c264 --- /dev/null +++ b/cortex_m_semihosting/syscall.m.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.syscall.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/syscall.v.html b/cortex_m_semihosting/syscall.v.html new file mode 100644 index 0000000..a0d20df --- /dev/null +++ b/cortex_m_semihosting/syscall.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.syscall.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/syscall1.m.html b/cortex_m_semihosting/syscall1.m.html new file mode 100644 index 0000000..85af6b1 --- /dev/null +++ b/cortex_m_semihosting/syscall1.m.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.syscall1.html...

      + + + \ No newline at end of file diff --git a/cortex_m_semihosting/syscall1.v.html b/cortex_m_semihosting/syscall1.v.html new file mode 100644 index 0000000..2bc4863 --- /dev/null +++ b/cortex_m_semihosting/syscall1.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.syscall1.html...

      + + + \ No newline at end of file diff --git a/dark.css b/dark.css new file mode 100644 index 0000000..272d81d --- /dev/null +++ b/dark.css @@ -0,0 +1,12 @@ +/*! + * Copyright 2015 The Rust Project Developers. See the COPYRIGHT + * file at the top-level directory of this distribution and at + * http://rust-lang.org/COPYRIGHT. + * + * Licensed under the Apache License, Version 2.0 or the MIT license + * , at your + * option. This file may not be copied, modified, or distributed + * except according to those terms. + */ +body{background-color:#353535;color:#ddd;}h1,h2,h3:not(.impl):not(.method):not(.type):not(.tymethod),h4:not(.method):not(.type):not(.tymethod){color:#ddd;}h1.fqn{border-bottom-color:#d2d2d2;}h2,h3:not(.impl):not(.method):not(.type):not(.tymethod),h4:not(.method):not(.type):not(.tymethod){border-bottom-color:#d2d2d2;}.in-band{background-color:#353535;}.invisible{background:rgba(0,0,0,0);}.docblock code,.docblock-short code{background-color:#2A2A2A;}pre{background-color:#2A2A2A;}.sidebar{background-color:#505050;}.sidebar .current{background-color:#333;}.source .sidebar{background-color:#353535;}.sidebar .location{border-color:#fff;background:#575757;color:#DDD;}.sidebar .version{border-bottom-color:#DDD;}.sidebar-title{border-top-color:#777;border-bottom-color:#777;}.block a:hover{background:#444;}.line-numbers span{color:#3B91E2;}.line-numbers .line-highlighted{background-color:#0a042f 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implementors; + } + +})() diff --git a/implementors/core/cmp/trait.Eq.js b/implementors/core/cmp/trait.Eq.js new file mode 100644 index 0000000..45ae4b1 --- /dev/null +++ b/implementors/core/cmp/trait.Eq.js @@ -0,0 +1,10 @@ +(function() {var implementors = {}; +implementors["cortex_m"] = [{text:"impl Eq for Exception",synthetic:false,types:["cortex_m::peripheral::scb::Exception"]},{text:"impl Eq for VectActive",synthetic:false,types:["cortex_m::peripheral::scb::VectActive"]},{text:"impl Eq for Npriv",synthetic:false,types:["cortex_m::register::control::Npriv"]},{text:"impl Eq for Spsel",synthetic:false,types:["cortex_m::register::control::Spsel"]},{text:"impl Eq for Fpca",synthetic:false,types:["cortex_m::register::control::Fpca"]},{text:"impl Eq for Faultmask",synthetic:false,types:["cortex_m::register::faultmask::Faultmask"]},{text:"impl Eq for Primask",synthetic:false,types:["cortex_m::register::primask::Primask"]},]; + + if (window.register_implementors) { + window.register_implementors(implementors); + } else { + window.pending_implementors = implementors; + } + +})() diff --git a/implementors/core/cmp/trait.PartialEq.js b/implementors/core/cmp/trait.PartialEq.js new file mode 100644 index 0000000..dcdd26a --- /dev/null +++ b/implementors/core/cmp/trait.PartialEq.js @@ -0,0 +1,10 @@ +(function() {var implementors = {}; +implementors["cortex_m"] = [{text:"impl PartialEq for Exception",synthetic:false,types:["cortex_m::peripheral::scb::Exception"]},{text:"impl PartialEq for VectActive",synthetic:false,types:["cortex_m::peripheral::scb::VectActive"]},{text:"impl PartialEq for Npriv",synthetic:false,types:["cortex_m::register::control::Npriv"]},{text:"impl PartialEq for Spsel",synthetic:false,types:["cortex_m::register::control::Spsel"]},{text:"impl PartialEq for Fpca",synthetic:false,types:["cortex_m::register::control::Fpca"]},{text:"impl PartialEq for Faultmask",synthetic:false,types:["cortex_m::register::faultmask::Faultmask"]},{text:"impl PartialEq for Primask",synthetic:false,types:["cortex_m::register::primask::Primask"]},]; + + if (window.register_implementors) { + window.register_implementors(implementors); + } else { + window.pending_implementors = implementors; + } + +})() diff --git a/implementors/core/fmt/trait.Debug.js b/implementors/core/fmt/trait.Debug.js new file mode 100644 index 0000000..3fa7cd3 --- /dev/null +++ b/implementors/core/fmt/trait.Debug.js @@ -0,0 +1,12 @@ +(function() {var implementors = {}; +implementors["bare_metal"] = [{text:"impl<T: Debug> Debug for Peripheral<T> where
          T: 'static,       ",synthetic:false,types:["bare_metal::Peripheral"]},]; +implementors["cortex_m"] = [{text:"impl Debug for Exception",synthetic:false,types:["cortex_m::peripheral::scb::Exception"]},{text:"impl Debug for VectActive",synthetic:false,types:["cortex_m::peripheral::scb::VectActive"]},{text:"impl Debug for SystClkSource",synthetic:false,types:["cortex_m::peripheral::syst::SystClkSource"]},{text:"impl Debug for Control",synthetic:false,types:["cortex_m::register::control::Control"]},{text:"impl Debug for Npriv",synthetic:false,types:["cortex_m::register::control::Npriv"]},{text:"impl Debug for Spsel",synthetic:false,types:["cortex_m::register::control::Spsel"]},{text:"impl Debug for Fpca",synthetic:false,types:["cortex_m::register::control::Fpca"]},{text:"impl Debug for Faultmask",synthetic:false,types:["cortex_m::register::faultmask::Faultmask"]},{text:"impl Debug for Primask",synthetic:false,types:["cortex_m::register::primask::Primask"]},{text:"impl Debug for Apsr",synthetic:false,types:["cortex_m::register::apsr::Apsr"]},]; +implementors["cortex_m_rt"] = [{text:"impl Debug for ExceptionFrame",synthetic:false,types:["cortex_m_rt::ExceptionFrame"]},]; + + if (window.register_implementors) { + window.register_implementors(implementors); + } else { + window.pending_implementors = implementors; + } + +})() diff --git a/implementors/core/fmt/trait.Write.js b/implementors/core/fmt/trait.Write.js new file mode 100644 index 0000000..e674a81 --- /dev/null +++ b/implementors/core/fmt/trait.Write.js @@ -0,0 +1,10 @@ +(function() {var implementors = {}; +implementors["cortex_m_semihosting"] = [{text:"impl Write for HStderr",synthetic:false,types:["cortex_m_semihosting::hio::HStderr"]},{text:"impl Write for HStdout",synthetic:false,types:["cortex_m_semihosting::hio::HStdout"]},]; + + if (window.register_implementors) { + window.register_implementors(implementors); + } else { + window.pending_implementors = implementors; + } + +})() diff --git a/implementors/core/marker/trait.Copy.js b/implementors/core/marker/trait.Copy.js new file mode 100644 index 0000000..c313c32 --- /dev/null +++ b/implementors/core/marker/trait.Copy.js @@ -0,0 +1,11 @@ +(function() {var implementors = {}; +implementors["cortex_m"] = [{text:"impl Copy for Exception",synthetic:false,types:["cortex_m::peripheral::scb::Exception"]},{text:"impl Copy for VectActive",synthetic:false,types:["cortex_m::peripheral::scb::VectActive"]},{text:"impl Copy for SystClkSource",synthetic:false,types:["cortex_m::peripheral::syst::SystClkSource"]},{text:"impl Copy for Control",synthetic:false,types:["cortex_m::register::control::Control"]},{text:"impl Copy for Npriv",synthetic:false,types:["cortex_m::register::control::Npriv"]},{text:"impl Copy for Spsel",synthetic:false,types:["cortex_m::register::control::Spsel"]},{text:"impl Copy for Fpca",synthetic:false,types:["cortex_m::register::control::Fpca"]},{text:"impl Copy for Faultmask",synthetic:false,types:["cortex_m::register::faultmask::Faultmask"]},{text:"impl Copy for Primask",synthetic:false,types:["cortex_m::register::primask::Primask"]},{text:"impl Copy for Apsr",synthetic:false,types:["cortex_m::register::apsr::Apsr"]},]; +implementors["cortex_m_rt"] = [{text:"impl Copy for ExceptionFrame",synthetic:false,types:["cortex_m_rt::ExceptionFrame"]},]; + + if (window.register_implementors) { + window.register_implementors(implementors); + } else { + window.pending_implementors = implementors; + } + +})() diff --git a/implementors/core/marker/trait.Send.js b/implementors/core/marker/trait.Send.js new file mode 100644 index 0000000..da587d2 --- /dev/null +++ b/implementors/core/marker/trait.Send.js @@ -0,0 +1,16 @@ +(function() {var implementors = {}; +implementors["aligned"] = [{text:"impl<ALIGNMENT, ARRAY: ?Sized> Send for Aligned<ALIGNMENT, ARRAY> where
          ALIGNMENT: Send,
          ARRAY: Send,       ",synthetic:true,types:["aligned::Aligned"]},]; +implementors["bare_metal"] = [{text:"impl<T> !Send for Peripheral<T>",synthetic:true,types:["bare_metal::Peripheral"]},{text:"impl Send for CriticalSection",synthetic:true,types:["bare_metal::CriticalSection"]},{text:"impl<T> Send for Mutex<T> where
          T: Send,       ",synthetic:true,types:["bare_metal::Mutex"]},]; +implementors["cortex_m"] = [{text:"impl Send for Peripherals",synthetic:true,types:["cortex_m::peripheral::Peripherals"]},{text:"impl Send for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::cbp::RegisterBlock"]},{text:"impl Send for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::cpuid::RegisterBlock"]},{text:"impl Send for CsselrCacheType",synthetic:true,types:["cortex_m::peripheral::cpuid::CsselrCacheType"]},{text:"impl Send for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::dcb::RegisterBlock"]},{text:"impl Send for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::dwt::RegisterBlock"]},{text:"impl Send for Comparator",synthetic:true,types:["cortex_m::peripheral::dwt::Comparator"]},{text:"impl Send for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::fpb::RegisterBlock"]},{text:"impl Send for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::fpu::RegisterBlock"]},{text:"impl Send for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::itm::RegisterBlock"]},{text:"impl Send for Stim",synthetic:true,types:["cortex_m::peripheral::itm::Stim"]},{text:"impl Send for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::mpu::RegisterBlock"]},{text:"impl Send for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::nvic::RegisterBlock"]},{text:"impl Send for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::scb::RegisterBlock"]},{text:"impl Send for Exception",synthetic:true,types:["cortex_m::peripheral::scb::Exception"]},{text:"impl Send for VectActive",synthetic:true,types:["cortex_m::peripheral::scb::VectActive"]},{text:"impl Send for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::syst::RegisterBlock"]},{text:"impl Send for SystClkSource",synthetic:true,types:["cortex_m::peripheral::syst::SystClkSource"]},{text:"impl Send for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::tpiu::RegisterBlock"]},{text:"impl Send for CBP",synthetic:false,types:["cortex_m::peripheral::CBP"]},{text:"impl Send for CPUID",synthetic:false,types:["cortex_m::peripheral::CPUID"]},{text:"impl Send for DCB",synthetic:false,types:["cortex_m::peripheral::DCB"]},{text:"impl Send for DWT",synthetic:false,types:["cortex_m::peripheral::DWT"]},{text:"impl Send for FPB",synthetic:false,types:["cortex_m::peripheral::FPB"]},{text:"impl Send for FPU",synthetic:false,types:["cortex_m::peripheral::FPU"]},{text:"impl Send for ITM",synthetic:false,types:["cortex_m::peripheral::ITM"]},{text:"impl Send for MPU",synthetic:false,types:["cortex_m::peripheral::MPU"]},{text:"impl Send for NVIC",synthetic:false,types:["cortex_m::peripheral::NVIC"]},{text:"impl Send for SCB",synthetic:false,types:["cortex_m::peripheral::SCB"]},{text:"impl Send for SYST",synthetic:false,types:["cortex_m::peripheral::SYST"]},{text:"impl Send for TPIU",synthetic:false,types:["cortex_m::peripheral::TPIU"]},{text:"impl Send for Control",synthetic:true,types:["cortex_m::register::control::Control"]},{text:"impl Send for Npriv",synthetic:true,types:["cortex_m::register::control::Npriv"]},{text:"impl Send for Spsel",synthetic:true,types:["cortex_m::register::control::Spsel"]},{text:"impl Send for Fpca",synthetic:true,types:["cortex_m::register::control::Fpca"]},{text:"impl Send for Faultmask",synthetic:true,types:["cortex_m::register::faultmask::Faultmask"]},{text:"impl Send for Primask",synthetic:true,types:["cortex_m::register::primask::Primask"]},{text:"impl Send for Apsr",synthetic:true,types:["cortex_m::register::apsr::Apsr"]},]; +implementors["cortex_m_rt"] = [{text:"impl Send for ExceptionFrame",synthetic:true,types:["cortex_m_rt::ExceptionFrame"]},]; +implementors["cortex_m_semihosting"] = [{text:"impl Send for Exception",synthetic:true,types:["cortex_m_semihosting::debug::Exception"]},{text:"impl Send for HStderr",synthetic:true,types:["cortex_m_semihosting::hio::HStderr"]},{text:"impl Send for HStdout",synthetic:true,types:["cortex_m_semihosting::hio::HStdout"]},]; +implementors["vcell"] = [{text:"impl<T> Send for VolatileCell<T> where
          T: Send,       ",synthetic:true,types:["vcell::VolatileCell"]},]; +implementors["volatile_register"] = [{text:"impl<T> Send for RO<T> where
          T: Send,       ",synthetic:true,types:["volatile_register::RO"]},{text:"impl<T> Send for RW<T> where
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          T: Send,       ",synthetic:true,types:["volatile_register::WO"]},]; + + if (window.register_implementors) { + window.register_implementors(implementors); + } else { + window.pending_implementors = implementors; + } + +})() diff --git a/implementors/core/marker/trait.Sync.js b/implementors/core/marker/trait.Sync.js new file mode 100644 index 0000000..bb617a3 --- /dev/null +++ b/implementors/core/marker/trait.Sync.js @@ -0,0 +1,16 @@ +(function() {var implementors = {}; +implementors["aligned"] = [{text:"impl<ALIGNMENT, ARRAY: ?Sized> Sync for Aligned<ALIGNMENT, ARRAY> where
          ALIGNMENT: Sync,
          ARRAY: Sync,       ",synthetic:true,types:["aligned::Aligned"]},]; +implementors["bare_metal"] = [{text:"impl<T> !Sync for Peripheral<T>",synthetic:true,types:["bare_metal::Peripheral"]},{text:"impl Sync for CriticalSection",synthetic:true,types:["bare_metal::CriticalSection"]},{text:"impl<T> Sync for Mutex<T> where
          T: Send,       ",synthetic:false,types:["bare_metal::Mutex"]},]; +implementors["cortex_m"] = [{text:"impl !Sync for Peripherals",synthetic:true,types:["cortex_m::peripheral::Peripherals"]},{text:"impl !Sync for CBP",synthetic:true,types:["cortex_m::peripheral::CBP"]},{text:"impl !Sync for CPUID",synthetic:true,types:["cortex_m::peripheral::CPUID"]},{text:"impl !Sync for DCB",synthetic:true,types:["cortex_m::peripheral::DCB"]},{text:"impl !Sync for DWT",synthetic:true,types:["cortex_m::peripheral::DWT"]},{text:"impl !Sync for FPB",synthetic:true,types:["cortex_m::peripheral::FPB"]},{text:"impl !Sync for FPU",synthetic:true,types:["cortex_m::peripheral::FPU"]},{text:"impl !Sync for ITM",synthetic:true,types:["cortex_m::peripheral::ITM"]},{text:"impl !Sync for MPU",synthetic:true,types:["cortex_m::peripheral::MPU"]},{text:"impl !Sync for NVIC",synthetic:true,types:["cortex_m::peripheral::NVIC"]},{text:"impl !Sync for SCB",synthetic:true,types:["cortex_m::peripheral::SCB"]},{text:"impl !Sync for SYST",synthetic:true,types:["cortex_m::peripheral::SYST"]},{text:"impl !Sync for TPIU",synthetic:true,types:["cortex_m::peripheral::TPIU"]},{text:"impl !Sync for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::cbp::RegisterBlock"]},{text:"impl !Sync for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::cpuid::RegisterBlock"]},{text:"impl Sync for CsselrCacheType",synthetic:true,types:["cortex_m::peripheral::cpuid::CsselrCacheType"]},{text:"impl !Sync for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::dcb::RegisterBlock"]},{text:"impl !Sync for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::dwt::RegisterBlock"]},{text:"impl !Sync for Comparator",synthetic:true,types:["cortex_m::peripheral::dwt::Comparator"]},{text:"impl !Sync for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::fpb::RegisterBlock"]},{text:"impl !Sync for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::fpu::RegisterBlock"]},{text:"impl !Sync for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::itm::RegisterBlock"]},{text:"impl !Sync for Stim",synthetic:true,types:["cortex_m::peripheral::itm::Stim"]},{text:"impl !Sync for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::mpu::RegisterBlock"]},{text:"impl !Sync for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::nvic::RegisterBlock"]},{text:"impl !Sync for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::scb::RegisterBlock"]},{text:"impl Sync for Exception",synthetic:true,types:["cortex_m::peripheral::scb::Exception"]},{text:"impl Sync for VectActive",synthetic:true,types:["cortex_m::peripheral::scb::VectActive"]},{text:"impl !Sync for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::syst::RegisterBlock"]},{text:"impl Sync for SystClkSource",synthetic:true,types:["cortex_m::peripheral::syst::SystClkSource"]},{text:"impl !Sync for RegisterBlock",synthetic:true,types:["cortex_m::peripheral::tpiu::RegisterBlock"]},{text:"impl Sync for Control",synthetic:true,types:["cortex_m::register::control::Control"]},{text:"impl Sync for Npriv",synthetic:true,types:["cortex_m::register::control::Npriv"]},{text:"impl Sync for Spsel",synthetic:true,types:["cortex_m::register::control::Spsel"]},{text:"impl Sync for Fpca",synthetic:true,types:["cortex_m::register::control::Fpca"]},{text:"impl Sync for Faultmask",synthetic:true,types:["cortex_m::register::faultmask::Faultmask"]},{text:"impl Sync for Primask",synthetic:true,types:["cortex_m::register::primask::Primask"]},{text:"impl Sync for Apsr",synthetic:true,types:["cortex_m::register::apsr::Apsr"]},]; +implementors["cortex_m_rt"] = [{text:"impl Sync for ExceptionFrame",synthetic:true,types:["cortex_m_rt::ExceptionFrame"]},]; +implementors["cortex_m_semihosting"] = [{text:"impl Sync for Exception",synthetic:true,types:["cortex_m_semihosting::debug::Exception"]},{text:"impl Sync for HStderr",synthetic:true,types:["cortex_m_semihosting::hio::HStderr"]},{text:"impl Sync for HStdout",synthetic:true,types:["cortex_m_semihosting::hio::HStdout"]},]; +implementors["vcell"] = [{text:"impl<T> !Sync for VolatileCell<T>",synthetic:true,types:["vcell::VolatileCell"]},]; +implementors["volatile_register"] = [{text:"impl<T> !Sync for RO<T>",synthetic:true,types:["volatile_register::RO"]},{text:"impl<T> !Sync for RW<T>",synthetic:true,types:["volatile_register::RW"]},{text:"impl<T> !Sync for WO<T>",synthetic:true,types:["volatile_register::WO"]},]; + + if (window.register_implementors) { + window.register_implementors(implementors); + } else { + window.pending_implementors = implementors; + } + +})() diff --git a/implementors/core/ops/deref/trait.Deref.js b/implementors/core/ops/deref/trait.Deref.js new file mode 100644 index 0000000..ba25f86 --- /dev/null +++ b/implementors/core/ops/deref/trait.Deref.js @@ -0,0 +1,11 @@ +(function() {var implementors = {}; +implementors["aligned"] = [{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 0]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 1]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 2]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 3]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 4]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 5]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 6]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 7]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 8]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 9]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 10]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 11]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 12]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 13]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 14]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 15]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 16]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 17]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 18]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 19]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 20]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 21]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 22]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 23]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 24]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 25]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 26]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 27]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 28]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 29]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 30]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 31]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 32]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 64]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 128]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 256]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Deref for Aligned<ALIGNMENT, [T; 1024]>",synthetic:false,types:["aligned::Aligned"]},]; +implementors["cortex_m"] = [{text:"impl Deref for CBP",synthetic:false,types:["cortex_m::peripheral::CBP"]},{text:"impl Deref for CPUID",synthetic:false,types:["cortex_m::peripheral::CPUID"]},{text:"impl Deref for DCB",synthetic:false,types:["cortex_m::peripheral::DCB"]},{text:"impl Deref for DWT",synthetic:false,types:["cortex_m::peripheral::DWT"]},{text:"impl Deref for FPB",synthetic:false,types:["cortex_m::peripheral::FPB"]},{text:"impl Deref for FPU",synthetic:false,types:["cortex_m::peripheral::FPU"]},{text:"impl Deref for ITM",synthetic:false,types:["cortex_m::peripheral::ITM"]},{text:"impl Deref for MPU",synthetic:false,types:["cortex_m::peripheral::MPU"]},{text:"impl Deref for NVIC",synthetic:false,types:["cortex_m::peripheral::NVIC"]},{text:"impl Deref for SCB",synthetic:false,types:["cortex_m::peripheral::SCB"]},{text:"impl Deref for SYST",synthetic:false,types:["cortex_m::peripheral::SYST"]},{text:"impl Deref for TPIU",synthetic:false,types:["cortex_m::peripheral::TPIU"]},]; + + if (window.register_implementors) { + window.register_implementors(implementors); + } else { + window.pending_implementors = implementors; + } + +})() diff --git a/implementors/core/ops/deref/trait.DerefMut.js b/implementors/core/ops/deref/trait.DerefMut.js new file mode 100644 index 0000000..9965dc3 --- /dev/null +++ b/implementors/core/ops/deref/trait.DerefMut.js @@ -0,0 +1,11 @@ +(function() {var implementors = {}; +implementors["aligned"] = [{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 0]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 1]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 2]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 3]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 4]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 5]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 6]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 7]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 8]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 9]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 10]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 11]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 12]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 13]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 14]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 15]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 16]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 17]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 18]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 19]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 20]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 21]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 22]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 23]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 24]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 25]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 26]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 27]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 28]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 29]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 30]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 31]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 32]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 64]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 128]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 256]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> DerefMut for Aligned<ALIGNMENT, [T; 1024]>",synthetic:false,types:["aligned::Aligned"]},]; +implementors["cortex_m"] = [{text:"impl DerefMut for ITM",synthetic:false,types:["cortex_m::peripheral::ITM"]},]; + + if (window.register_implementors) { + window.register_implementors(implementors); + } else { + window.pending_implementors = implementors; + } + +})() diff --git a/implementors/core/ops/index/trait.Index.js b/implementors/core/ops/index/trait.Index.js new file mode 100644 index 0000000..d1a76bc --- /dev/null +++ b/implementors/core/ops/index/trait.Index.js @@ -0,0 +1,10 @@ +(function() {var implementors = {}; +implementors["aligned"] = [{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 0]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 1]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 2]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 3]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 4]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 5]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 6]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 7]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 8]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 9]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 10]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 11]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 12]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 13]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 14]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 15]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 16]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 17]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 18]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 19]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 20]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 21]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 22]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 23]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 24]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 25]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 26]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 27]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 28]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 29]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 30]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 31]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 32]>",synthetic:false,types:["aligned::Aligned"]},{text:"impl<T, ALIGNMENT> Index<RangeTo<usize>> for Aligned<ALIGNMENT, [T; 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      [−] + + List of all items

      \ No newline at end of file diff --git a/panic_semihosting/index.html b/panic_semihosting/index.html new file mode 100644 index 0000000..39b9688 --- /dev/null +++ b/panic_semihosting/index.html @@ -0,0 +1,32 @@ +panic_semihosting - Rust

      [−][src]Crate panic_semihosting

      Report panic messages to the host stderr using semihosting

      +

      This crate contains an implementation of panic_fmt that logs panic messages to the host stderr +using cortex-m-semihosting. Before logging the message the panic handler disables (masks) +the device specific interrupts. After logging the message the panic handler trigger a breakpoint +and then goes into an infinite loop.

      +

      Currently, this crate only supports the ARM Cortex-M architecture.

      +

      Usage

      +
      ⓘThis example is not tested
      +#![no_std]
+
+extern crate panic_semihosting;
+
+fn main() {
+    panic!("FOO")
+}
      +
      (gdb) monitor arm semihosting enable
+(gdb) continue
+Program received signal SIGTRAP, Trace/breakpoint trap.
+rust_begin_unwind (args=..., file=..., line=8, col=5)
+    at $CRATE/src/lib.rs:69
+69          asm::bkpt();
+
      +
      $ openocd -f (..)
+(..)
+panicked at 'FOO', src/main.rs:6:5
+
      +

      Optional features

      inline-asm

      +

      When this feature is enabled semihosting is implemented using inline assembly (asm!) and +compiling this crate requires nightly.

      +

      When this feature is disabled semihosting is implemented using FFI calls into an external +assembly file and compiling this crate works on stable and beta.

      +
      \ No newline at end of file diff --git a/panic_semihosting/sidebar-items.js b/panic_semihosting/sidebar-items.js new file mode 100644 index 0000000..48333d3 --- /dev/null +++ b/panic_semihosting/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({}); \ No newline at end of file diff --git a/r0/all.html b/r0/all.html new file mode 100644 index 0000000..68f6760 --- /dev/null +++ b/r0/all.html @@ -0,0 +1,3 @@ +List of all items in this crate

      [−] + + List of all items

      Macros

      Functions

      \ No newline at end of file diff --git a/r0/fn.init_data.html b/r0/fn.init_data.html new file mode 100644 index 0000000..b2c9f50 --- /dev/null +++ b/r0/fn.init_data.html @@ -0,0 +1,19 @@ +r0::init_data - Rust

      [−][src]Function r0::init_data

      pub unsafe fn init_data<T>(sdata: *mut T, edata: *mut T, sidata: *const T) where
          T: Copy, 

      Initializes the .data section

      +

      Arguments

      +
        +
      • sdata. Pointer to the start of the .data section.
        • +
      • edata. Pointer to the open/non-inclusive end of the .data section. +(The value behind this pointer will not be modified)
        • +
      • sidata. .data section Load Memory Address (LMA)
        • +
      • Use T to indicate the alignment of the .data section and its LMA.
        • +
      +

      Safety

      +
        +
      • Must be called exactly once
        • +
      • mem::size_of::<T>() must be non-zero
        • +
      • edata >= sdata
        • +
      • The sdata -> edata region must not overlap with the sidata -> ... +region
        • +
      • sdata, edata and sidata must be T aligned.
        • +
      +
      \ No newline at end of file diff --git a/r0/fn.run_init_array.html b/r0/fn.run_init_array.html new file mode 100644 index 0000000..7d3989c --- /dev/null +++ b/r0/fn.run_init_array.html @@ -0,0 +1 @@ +r0::run_init_array - Rust

      [−][src]Function r0::run_init_array

      pub unsafe fn run_init_array(
          init_array_start: &extern "C" fn(), 
          init_array_end: &extern "C" fn()
      )
      \ No newline at end of file diff --git a/r0/fn.zero_bss.html b/r0/fn.zero_bss.html new file mode 100644 index 0000000..9bc07c5 --- /dev/null +++ b/r0/fn.zero_bss.html @@ -0,0 +1,16 @@ +r0::zero_bss - Rust

      [−][src]Function r0::zero_bss

      pub unsafe fn zero_bss<T>(sbss: *mut T, ebss: *mut T) where
          T: Copy, 

      Zeroes the .bss section

      +

      Arguments

      +
        +
      • sbss. Pointer to the start of the .bss section.
        • +
      • ebss. Pointer to the open/non-inclusive end of the .bss section. +(The value behind this pointer will not be modified)
        • +
      • Use T to indicate the alignment of the .bss section.
        • +
      +

      Safety

      +
        +
      • Must be called exactly once
        • +
      • mem::size_of::<T>() must be non-zero
        • +
      • ebss >= sbss
        • +
      • sbss and ebss must be T aligned.
        • +
      +
      \ No newline at end of file diff --git a/r0/index.html b/r0/index.html new file mode 100644 index 0000000..581d42e --- /dev/null +++ b/r0/index.html @@ -0,0 +1,124 @@ +r0 - Rust

      [−][src]Crate r0

      Initialization code ("crt0") written in Rust

      +

      This is for bare metal systems where there is no ELF loader or OS to take +care of initializing RAM for the program.

      +

      Initializing RAM

      +

      On the linker script side, we must assign names (symbols) to the boundaries +of the .bss and .data sections.

      +
      .bss : ALIGN(4)
+{
+    _sbss = .;
+    *(.bss.*);
+    _ebss = ALIGN(4);
+} > RAM
+
+.data : ALIGN(4)
+{
+    _sdata = .;
+    *(.data.*);
+    _edata = ALIGN(4);
+} > RAM AT > FLASH
+
+_sidata = LOADADDR(.data);
+
      +

      On the Rust side, we must bind to those symbols using an extern block.

      + +
      +unsafe fn before_main() {
+    // The type, `u32`, indicates that the memory is 4-byte aligned
+    extern "C" {
+        static mut _sbss: u32;
+        static mut _ebss: u32;
+
+        static mut _sdata: u32;
+        static mut _edata: u32;
+
+        static _sidata: u32;
+    }
+
+    zero_bss(&mut _sbss, &mut _ebss);
+    init_data(&mut _sdata, &mut _edata, &_sidata);
+}
      +

      .init_array & .pre_init_array

      +

      This crate also provides an API to add "life before main" functionality to +bare metal systems.

      +

      On the linker script side, instruct the linker to keep the .init_array +sections from input object files. Store the start and end address of the +merged .init_array section.

      +
      .text :
+{
+  /* .. */
+  _init_array_start = ALIGN(4);
+  KEEP(*(.init_array));
+  _init_array_end = ALIGN(4);
+  /* .. */
+}
+
      +

      On the startup code, invoke the run_init_array function before you call +the user main.

      + +
      +unsafe fn start() {
+    extern "C" {
+        static _init_array_start: extern "C" fn();
+        static _init_array_end: extern "C" fn();
+    }
+
+    ::r0::run_init_array(&_init_array_start, &_init_array_end);
+
+    extern "C" {
+        fn main(argc: isize, argv: *const *const u8) -> isize;
+    }
+
+    main();
+}
      +

      Then the user application can use this crate init_array! macro to run code +before main.

      + +
      +init_array!(before_main, {
+    println!("Hello");
+});
+
+fn main() {
+    println!("World");
+}
      +

      Macros

      + + + + + + + + +
      init_array + +
      pre_init_array + +

      Functions

      + + + + + + + + + + + + +
      init_data⚠ +

      Initializes the .data section

      + +
      run_init_array⚠ + +
      zero_bss⚠ +

      Zeroes the .bss section

      + +
      \ No newline at end of file diff --git a/r0/init_array.m.html b/r0/init_array.m.html new file mode 100644 index 0000000..ce00f55 --- /dev/null +++ b/r0/init_array.m.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.init_array.html...

      + + + \ No newline at end of file diff --git a/r0/init_data.v.html b/r0/init_data.v.html new file mode 100644 index 0000000..e743d34 --- /dev/null +++ b/r0/init_data.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.init_data.html...

      + + + \ No newline at end of file diff --git a/r0/macro.init_array!.html b/r0/macro.init_array!.html new file mode 100644 index 0000000..ce00f55 --- /dev/null +++ b/r0/macro.init_array!.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.init_array.html...

      + + + \ No newline at end of file diff --git a/r0/macro.init_array.html b/r0/macro.init_array.html new file mode 100644 index 0000000..4523386 --- /dev/null +++ b/r0/macro.init_array.html @@ -0,0 +1,5 @@ +r0::init_array - Rust

      [−][src]Macro r0::init_array

      +macro_rules! init_array {
+    ($name:ident, $body:expr) => { ... };
+}
      +
      \ No newline at end of file diff --git a/r0/macro.pre_init_array!.html b/r0/macro.pre_init_array!.html new file mode 100644 index 0000000..84ee406 --- /dev/null +++ b/r0/macro.pre_init_array!.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.pre_init_array.html...

      + + + \ No newline at end of file diff --git a/r0/macro.pre_init_array.html b/r0/macro.pre_init_array.html new file mode 100644 index 0000000..a4058f8 --- /dev/null +++ b/r0/macro.pre_init_array.html @@ -0,0 +1,5 @@ +r0::pre_init_array - Rust

      [−][src]Macro r0::pre_init_array

      +macro_rules! pre_init_array {
+    ($name:ident, $body:expr) => { ... };
+}
      +
      \ No newline at end of file diff --git a/r0/pre_init_array.m.html b/r0/pre_init_array.m.html new file mode 100644 index 0000000..84ee406 --- /dev/null +++ b/r0/pre_init_array.m.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to macro.pre_init_array.html...

      + + + \ No newline at end of file diff --git a/r0/run_init_array.v.html b/r0/run_init_array.v.html new file mode 100644 index 0000000..4b0b584 --- /dev/null +++ b/r0/run_init_array.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.run_init_array.html...

      + + + \ No newline at end of file diff --git a/r0/sidebar-items.js b/r0/sidebar-items.js new file mode 100644 index 0000000..1d478ab --- /dev/null +++ b/r0/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"fn":[["init_data","Initializes the `.data` section"],["run_init_array",""],["zero_bss","Zeroes the `.bss` section"]],"macro":[["init_array",""],["pre_init_array",""]]}); \ No newline at end of file diff --git a/r0/zero_bss.v.html b/r0/zero_bss.v.html new file mode 100644 index 0000000..507bcdb --- /dev/null +++ b/r0/zero_bss.v.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to fn.zero_bss.html...

      + + + \ No newline at end of file diff --git a/rustdoc.css b/rustdoc.css new file mode 100644 index 0000000..7537eee --- /dev/null +++ b/rustdoc.css @@ -0,0 +1,12 @@ +/*! + * Copyright 2013 The Rust Project Developers. See the COPYRIGHT + * file at the top-level directory of this distribution and at + * http://rust-lang.org/COPYRIGHT. + * + * Licensed under the Apache License, Version 2.0 or the MIT license + * , at your + * option. This file may not be copied, modified, or distributed + * except according to those terms. + */ +@font-face {font-family:'Fira Sans';font-style:normal;font-weight:400;src:local('Fira Sans'),url("FiraSans-Regular.woff") format('woff');}@font-face {font-family:'Fira Sans';font-style:normal;font-weight:500;src:local('Fira Sans Medium'),url("FiraSans-Medium.woff") format('woff');}@font-face {font-family:'Source Serif Pro';font-style:normal;font-weight:400;src:local('Source Serif Pro'),url("SourceSerifPro-Regular.woff") format('woff');}@font-face {font-family:'Source Serif Pro';font-style:italic;font-weight:400;src:url("Heuristica-Italic.woff") format('woff');}@font-face {font-family:'Source Serif Pro';font-style:normal;font-weight:700;src:local('Source Serif Pro Bold'),url("SourceSerifPro-Bold.woff") format('woff');}@font-face {font-family:'Source Code Pro';font-style:normal;font-weight:400;src:url("SourceCodePro-Regular.woff") format('woff');}@font-face {font-family:'Source Code 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Address",12,N],[12,"fpdscr","","Floating Point Default Status Control",12,N],[12,"mvfr","","Media and FP Feature",12,N],[0,"itm","cortex_m::peripheral","Instrumentation Trace Macrocell",N,N],[3,"RegisterBlock","cortex_m::peripheral::itm","Register block",N,N],[12,"stim","","Stimulus Port",13,N],[12,"ter","","Trace Enable",13,N],[12,"tpr","","Trace Privilege",13,N],[12,"tcr","","Trace Control",13,N],[12,"lar","","Lock Access",13,N],[12,"lsr","","Lock Status",13,N],[3,"Stim","","Stimulus Port",N,N],[11,"write_u8","","Writes an `u8` payload into the stimulus port",14,[[["self"],["u8"]]]],[11,"write_u16","","Writes an `u16` payload into the stimulus port",14,[[["self"],["u16"]]]],[11,"write_u32","","Writes an `u32` payload into the stimulus port",14,[[["self"],["u32"]]]],[11,"is_fifo_ready","","Returns `true` if the stimulus port is ready to accept more data",14,[[["self"]],["bool"]]],[0,"mpu","cortex_m::peripheral","Memory Protection Unit",N,N],[3,"RegisterBlock","cortex_m::peripheral::mpu","Register block",N,N],[12,"_type","","Type",15,N],[12,"ctrl","","Control",15,N],[12,"rnr","","Region Number",15,N],[12,"rbar","","Region Base Address",15,N],[12,"rasr","","Region Attribute and Size",15,N],[12,"rbar_a1","","Alias 1 of RBAR",15,N],[12,"rsar_a1","","Alias 1 of RSAR",15,N],[12,"rbar_a2","","Alias 2 of RBAR",15,N],[12,"rsar_a2","","Alias 2 of RSAR",15,N],[12,"rbar_a3","","Alias 3 of RBAR",15,N],[12,"rsar_a3","","Alias 3 of RSAR",15,N],[0,"nvic","cortex_m::peripheral","Nested Vector Interrupt Controller",N,N],[3,"RegisterBlock","cortex_m::peripheral::nvic","Register block",N,N],[12,"iser","","Interrupt Set-Enable",16,N],[12,"icer","","Interrupt Clear-Enable",16,N],[12,"ispr","","Interrupt Set-Pending",16,N],[12,"icpr","","Interrupt Clear-Pending",16,N],[12,"iabr","","Interrupt Active Bit (not present on Cortex-M0 variants)",16,N],[12,"ipr","","Interrupt Priority",16,N],[11,"clear_pending","cortex_m::peripheral","Clears `interrupt`'s pending state",17,[[["self"],["i"]]]],[11,"disable","","Disables `interrupt`",17,[[["self"],["i"]]]],[11,"enable","","Enables `interrupt`",17,[[["self"],["i"]]]],[11,"get_priority","","Returns the NVIC priority of `interrupt`",17,[[["i"]],["u8"]]],[11,"is_active","","Is `interrupt` active or pre-empted and stacked",17,[[["i"]],["bool"]]],[11,"is_enabled","","Checks if `interrupt` is enabled",17,[[["i"]],["bool"]]],[11,"is_pending","","Checks if `interrupt` is pending",17,[[["i"]],["bool"]]],[11,"set_pending","","Forces `interrupt` into pending state",17,[[["self"],["i"]]]],[11,"set_priority","","Sets the \"priority\" of `interrupt` to `prio`",17,[[["self"],["i"],["u8"]]]],[0,"scb","","System Control Block",N,N],[3,"RegisterBlock","cortex_m::peripheral::scb","Register block",N,N],[12,"icsr","","Interrupt Control and State",18,N],[12,"vtor","","Vector Table Offset (not present on Cortex-M0 variants)",18,N],[12,"aircr","","Application Interrupt and Reset Control",18,N],[12,"scr","","System Control",18,N],[12,"ccr","","Configuration and Control",18,N],[12,"shpr","","System Handler Priority (word accessible only on Cortex-M0 variants)",18,N],[12,"shcrs","","System Handler Control and State",18,N],[12,"cfsr","","Configurable Fault Status (not present on Cortex-M0 variants)",18,N],[12,"hfsr","","HardFault Status (not present on Cortex-M0 variants)",18,N],[12,"dfsr","","Debug Fault Status (not present on Cortex-M0 variants)",18,N],[12,"mmfar","","MemManage Fault Address (not present on Cortex-M0 variants)",18,N],[12,"bfar","","BusFault Address (not present on Cortex-M0 variants)",18,N],[12,"afsr","","Auxiliary Fault Status (not present on Cortex-M0 variants)",18,N],[12,"cpacr","","Coprocessor Access Control (not present on Cortex-M0 variants)",18,N],[4,"Exception","","Processor core exceptions (internal interrupts)",N,N],[13,"NonMaskableInt","","Non maskable interrupt",19,N],[13,"HardFault","","Hard fault interrupt",19,N],[13,"MemoryManagement","","Memory management interrupt (not present on Cortex-M0 variants)",19,N],[13,"BusFault","","Bus fault interrupt (not present on Cortex-M0 variants)",19,N],[13,"UsageFault","","Usage fault interrupt (not present on Cortex-M0 variants)",19,N],[13,"SecureFault","","Secure fault interrupt (only on ARMv8-M)",19,N],[13,"SVCall","","SV call interrupt",19,N],[13,"DebugMonitor","","Debug monitor interrupt (not present on Cortex-M0 variants)",19,N],[13,"PendSV","","Pend SV interrupt",19,N],[13,"SysTick","","System Tick interrupt",19,N],[4,"VectActive","","Active exception number",N,N],[13,"ThreadMode","","Thread mode",20,N],[13,"Exception","","Processor core exception (internal interrupts)",20,N],[13,"Interrupt","","Device specific exception (external interrupts)",20,N],[12,"irqn","cortex_m::peripheral::scb::VectActive","Interrupt number. This number is always within half open range `[0, 240)`",20,N],[11,"vect_active","cortex_m::peripheral","Returns the active exception number",21,[[],["vectactive"]]],[11,"clone","cortex_m::peripheral::scb","",19,[[["self"]],["exception"]]],[11,"fmt","","",19,[[["self"],["formatter"]],["result"]]],[11,"eq","","",19,[[["self"],["exception"]],["bool"]]],[11,"irqn","","Returns the IRQ number of this `Exception`",19,[[["self"]],["i8"]]],[11,"clone","","",20,[[["self"]],["vectactive"]]],[11,"fmt","","",20,[[["self"],["formatter"]],["result"]]],[11,"eq","","",20,[[["self"],["vectactive"]],["bool"]]],[11,"ne","","",20,[[["self"],["vectactive"]],["bool"]]],[11,"from","","Converts a `byte` into `VectActive`",20,[[["u8"]],["option"]]],[11,"enable_icache","cortex_m::peripheral","Enables I-Cache if currently disabled",21,[[["self"]]]],[11,"disable_icache","","Disables I-Cache if currently enabled",21,[[["self"]]]],[11,"icache_enabled","","Returns whether the I-Cache is currently enabled",21,[[],["bool"]]],[11,"invalidate_icache","","Invalidates I-Cache",21,[[["self"]]]],[11,"enable_dcache","","Enables D-cache if currently disabled",21,[[["self"],["cpuid"]]]],[11,"disable_dcache","","Disables D-cache if currently enabled",21,[[["self"],["cpuid"]]]],[11,"dcache_enabled","","Returns whether the D-Cache is currently enabled",21,[[],["bool"]]],[11,"clean_dcache","","Cleans D-cache",21,[[["self"],["cpuid"]]]],[11,"clean_invalidate_dcache","","Cleans and invalidates D-cache",21,[[["self"],["cpuid"]]]],[11,"invalidate_dcache_by_address","","Invalidates D-cache by address",21,[[["self"],["usize"],["usize"]]]],[11,"clean_dcache_by_address","","Cleans D-cache by address",21,[[["self"],["usize"],["usize"]]]],[11,"clean_invalidate_dcache_by_address","","Cleans and invalidates D-cache by address",21,[[["self"],["usize"],["usize"]]]],[11,"set_sleepdeep","","Set the SLEEPDEEP bit in the SCR register",21,[[["self"]]]],[11,"clear_sleepdeep","","Clear the SLEEPDEEP bit in the SCR register",21,[[["self"]]]],[11,"system_reset","","Initiate a system reset request to reset the MCU",21,N],[0,"syst","","SysTick: System Timer",N,N],[3,"RegisterBlock","cortex_m::peripheral::syst","Register block",N,N],[12,"csr","","Control and Status",22,N],[12,"rvr","","Reload Value",22,N],[12,"cvr","","Current Value",22,N],[12,"calib","","Calibration Value",22,N],[4,"SystClkSource","","SysTick clock source",N,N],[13,"Core","","Core-provided clock",23,N],[13,"External","","External reference clock",23,N],[11,"clone","","",23,[[["self"]],["systclksource"]]],[11,"fmt","","",23,[[["self"],["formatter"]],["result"]]],[11,"clear_current","cortex_m::peripheral","Clears current value to 0",24,[[["self"]]]],[11,"disable_counter","","Disables counter",24,[[["self"]]]],[11,"disable_interrupt","","Disables SysTick interrupt",24,[[["self"]]]],[11,"enable_counter","","Enables counter",24,[[["self"]]]],[11,"enable_interrupt","","Enables SysTick interrupt",24,[[["self"]]]],[11,"get_clock_source","","Gets clock source",24,[[["self"]],["systclksource"]]],[11,"get_current","","Gets current value",24,[[],["u32"]]],[11,"get_reload","","Gets reload value",24,[[],["u32"]]],[11,"get_ticks_per_10ms","","Returns the reload value with which the counter would wrap once per 10 ms",24,[[],["u32"]]],[11,"has_reference_clock","","Checks if an external reference clock is available",24,[[],["bool"]]],[11,"has_wrapped","","Checks if the counter wrapped (underflowed) since the last check",24,[[["self"]],["bool"]]],[11,"is_counter_enabled","","Checks if counter is enabled",24,[[["self"]],["bool"]]],[11,"is_interrupt_enabled","","Checks if SysTick interrupt is enabled",24,[[["self"]],["bool"]]],[11,"is_precise","","Checks if the calibration value is precise",24,[[],["bool"]]],[11,"set_clock_source","","Sets clock source",24,[[["self"],["systclksource"]]]],[11,"set_reload","","Sets reload value",24,[[["self"],["u32"]]]],[0,"tpiu","","Trace Port Interface Unit;",N,N],[3,"RegisterBlock","cortex_m::peripheral::tpiu","Register block",N,N],[12,"sspsr","","Supported Parallel Port Sizes",25,N],[12,"cspsr","","Current Parallel Port Size",25,N],[12,"acpr","","Asynchronous Clock Prescaler",25,N],[12,"sppr","","Selected Pin Control",25,N],[12,"ffcr","","Formatter and Flush Control",25,N],[12,"lar","","Lock Access",25,N],[12,"lsr","","Lock Status",25,N],[12,"_type","","TPIU Type",25,N],[11,"take","cortex_m::peripheral","Returns all the core peripherals once",1,[[],["option"]]],[11,"steal","","Unchecked version of `Peripherals::take`",1,[[],["self"]]],[11,"ptr","","Returns a pointer to the register block",3,N],[11,"deref","","",3,N],[11,"ptr","","Returns a pointer to the register block",6,N],[11,"deref","","",6,N],[11,"ptr","","Returns a pointer to the register block",26,N],[11,"deref","","",26,N],[11,"ptr","","Returns a pointer to the register block",10,N],[11,"deref","","",10,N],[11,"ptr","","Returns a pointer to the register block",27,N],[11,"deref","","",27,N],[11,"ptr","","Returns a pointer to the register block",28,N],[11,"deref","","",28,N],[11,"ptr","","Returns a pointer to the register block",29,N],[11,"deref","","",29,N],[11,"deref_mut","","",29,N],[11,"ptr","","Returns a pointer to the register block",30,N],[11,"deref","","",30,N],[11,"ptr","","Returns a pointer to the register block",17,N],[11,"deref","","",17,N],[11,"ptr","","Returns a pointer to the register block",21,N],[11,"deref","","",21,N],[11,"ptr","","Returns a pointer to the register block",24,N],[11,"deref","","",24,N],[11,"ptr","","Returns a pointer to the register block",31,N],[11,"deref","","",31,N],[0,"register","cortex_m","Processor core registers",N,N],[0,"basepri","cortex_m::register","Base Priority Mask Register",N,N],[5,"read","cortex_m::register::basepri","Reads the CPU register",N,[[],["u8"]]],[5,"write","","Writes to the CPU register",N,[[["u8"]]]],[0,"basepri_max","cortex_m::register","Base Priority Mask Register (conditional write)",N,N],[5,"write","cortex_m::register::basepri_max","Writes to BASEPRI if",N,[[["u8"]]]],[0,"control","cortex_m::register","Control register",N,N],[3,"Control","cortex_m::register::control","Control register",N,N],[4,"Npriv","","Thread mode privilege level",N,N],[13,"Privileged","","Privileged",32,N],[13,"Unprivileged","","Unprivileged",32,N],[4,"Spsel","","Currently active stack pointer",N,N],[13,"Msp","","MSP is the current stack pointer",33,N],[13,"Psp","","PSP is the current stack pointer",33,N],[4,"Fpca","","Whether context floating-point is currently active",N,N],[13,"Active","","Floating-point context active.",34,N],[13,"NotActive","","No floating-point context active",34,N],[5,"read","","Reads the CPU register",N,[[],["control"]]],[11,"clone","","",35,[[["self"]],["control"]]],[11,"fmt","","",35,[[["self"],["formatter"]],["result"]]],[11,"bits","","Returns the contents of the register as raw bits",35,[[["self"]],["u32"]]],[11,"npriv","","Thread mode privilege level",35,[[["self"]],["npriv"]]],[11,"spsel","","Currently active stack pointer",35,[[["self"]],["spsel"]]],[11,"fpca","","Whether context floating-point is currently active",35,[[["self"]],["fpca"]]],[11,"clone","","",32,[[["self"]],["npriv"]]],[11,"fmt","","",32,[[["self"],["formatter"]],["result"]]],[11,"eq","","",32,[[["self"],["npriv"]],["bool"]]],[11,"is_privileged","","Is in privileged thread mode?",32,[[["self"]],["bool"]]],[11,"is_unprivileged","","Is in unprivileged thread mode?",32,[[["self"]],["bool"]]],[11,"clone","","",33,[[["self"]],["spsel"]]],[11,"fmt","","",33,[[["self"],["formatter"]],["result"]]],[11,"eq","","",33,[[["self"],["spsel"]],["bool"]]],[11,"is_msp","","Is MSP the current stack pointer?",33,[[["self"]],["bool"]]],[11,"is_psp","","Is PSP the current stack pointer?",33,[[["self"]],["bool"]]],[11,"clone","","",34,[[["self"]],["fpca"]]],[11,"fmt","","",34,[[["self"],["formatter"]],["result"]]],[11,"eq","","",34,[[["self"],["fpca"]],["bool"]]],[11,"is_active","","Is a floating-point context active?",34,[[["self"]],["bool"]]],[11,"is_not_active","","Is a floating-point context not active?",34,[[["self"]],["bool"]]],[0,"faultmask","cortex_m::register","Fault Mask Register",N,N],[4,"Faultmask","cortex_m::register::faultmask","All exceptions are ...",N,N],[13,"Active","","Active",36,N],[13,"Inactive","","Inactive, expect for NMI",36,N],[5,"read","","Reads the CPU register",N,[[],["faultmask"]]],[11,"clone","","",36,[[["self"]],["faultmask"]]],[11,"fmt","","",36,[[["self"],["formatter"]],["result"]]],[11,"eq","","",36,[[["self"],["faultmask"]],["bool"]]],[11,"is_active","","All exceptions are active",36,[[["self"]],["bool"]]],[11,"is_inactive","","All exceptions, except for NMI, are inactive",36,[[["self"]],["bool"]]],[0,"msp","cortex_m::register","Main Stack Pointer",N,N],[5,"read","cortex_m::register::msp","Reads the CPU register",N,[[],["u32"]]],[5,"write","","Writes `bits` to the CPU register",N,[[["u32"]]]],[0,"primask","cortex_m::register","Priority mask register",N,N],[4,"Primask","cortex_m::register::primask","All exceptions with configurable priority are ...",N,N],[13,"Active","","Active",37,N],[13,"Inactive","","Inactive",37,N],[5,"read","","Reads the CPU register",N,[[],["primask"]]],[11,"clone","","",37,[[["self"]],["primask"]]],[11,"fmt","","",37,[[["self"],["formatter"]],["result"]]],[11,"eq","","",37,[[["self"],["primask"]],["bool"]]],[11,"is_active","","All exceptions with configurable priority are active",37,[[["self"]],["bool"]]],[11,"is_inactive","","All exceptions with configurable priority are inactive",37,[[["self"]],["bool"]]],[0,"psp","cortex_m::register","Process Stack Pointer",N,N],[5,"read","cortex_m::register::psp","Reads the CPU register",N,[[],["u32"]]],[5,"write","","Writes `bits` to the CPU register",N,[[["u32"]]]],[0,"apsr","cortex_m::register","Application Program Status Register",N,N],[3,"Apsr","cortex_m::register::apsr","Application Program Status Register",N,N],[5,"read","","Reads the CPU register",N,[[],["apsr"]]],[11,"clone","","",38,[[["self"]],["apsr"]]],[11,"fmt","","",38,[[["self"],["formatter"]],["result"]]],[11,"bits","","Returns the contents of the register as raw bits",38,[[["self"]],["u32"]]],[11,"q","","DSP overflow and saturation flag",38,[[["self"]],["bool"]]],[11,"v","","Overflow flag",38,[[["self"]],["bool"]]],[11,"c","","Carry or borrow flag",38,[[["self"]],["bool"]]],[11,"z","","Zero flag",38,[[["self"]],["bool"]]],[11,"n","","Negative flag",38,[[["self"]],["bool"]]],[0,"lr","cortex_m::register","Link register",N,N],[5,"read","cortex_m::register::lr","Reads the CPU register",N,[[],["u32"]]],[5,"write","","Writes `bits` to the CPU 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+initSearch(searchIndex); diff --git a/settings.css b/settings.css new file mode 100644 index 0000000..11fbf77 --- /dev/null +++ b/settings.css @@ -0,0 +1,12 @@ +/*! + * Copyright 2018 The Rust Project Developers. See the COPYRIGHT + * file at the top-level directory of this distribution and at + * http://rust-lang.org/COPYRIGHT. + * + * Licensed under the Apache License, Version 2.0 or the MIT license + * , at your + * option. This file may not be copied, modified, or distributed + * except according to those terms. + */ +.setting-line{padding:5px;}.setting-line>div{max-width:calc(100% - 74px);display:inline-block;vertical-align:top;font-size:17px;padding-top:2px;}.toggle{position:relative;display:inline-block;width:45px;height:27px;margin-right:20px;}.toggle input{display:none;}.slider{position:absolute;cursor:pointer;top:0;left:0;right:0;bottom:0;background-color:#ccc;-webkit-transition:.3s;transition:.3s;}.slider:before{position:absolute;content:"";height:19px;width:19px;left:4px;bottom:4px;background-color:white;-webkit-transition:.3s;transition:.3s;}input:checked+.slider{background-color:#2196F3;}input:focus+.slider{box-shadow:0 0 1px #2196F3;}input:checked+.slider:before{-webkit-transform:translateX(19px);-ms-transform:translateX(19px);transform:translateX(19px);} \ No newline at end of file diff --git a/settings.html b/settings.html new file mode 100644 index 0000000..32b3d6e --- /dev/null +++ b/settings.html @@ -0,0 +1 @@ +Rustdoc settings

      Rustdoc settings

      Auto-hide item declarations.
      Auto-hide item attributes.
      Auto-hide trait implementations documentation
      Directly go to item in search if there is only one result
      \ No newline at end of file diff --git a/settings.js b/settings.js new file mode 100644 index 0000000..ff9ce17 --- /dev/null +++ b/settings.js @@ -0,0 +1,11 @@ +/*! + * Copyright 2018 The Rust Project Developers. See the COPYRIGHT + * file at the top-level directory of this distribution and at + * http://rust-lang.org/COPYRIGHT. + * + * Licensed under the Apache License, Version 2.0 or the MIT license + * , at your + * option. This file may not be copied, modified, or distributed + * except according to those terms. + */(function(){function changeSetting(settingName,isEnabled){updateLocalStorage('rustdoc-'+settingName,isEnabled);}function getSettingValue(settingName){return getCurrentValue('rustdoc-'+settingName);}function setEvents(){var elems=document.getElementsByClassName("slider");if(!elems||elems.length===0){return;}for(var i=0;ilib.rs.html -- source
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+
      +//! Statically allocated arrays with guaranteed memory alignments
+//!
+//! # Examples
+//!
+//! ```
+//! #![feature(const_fn)]
+//!
+//! use std::mem;
+//!
+//! use aligned::Aligned;
+//!
+//! // Array aligned to a 2 byte boundary
+//! static X: Aligned<u16, [u8; 3]> = Aligned([0; 3]);
+//!
+//! // Array aligned to a 4 byte boundary
+//! static Y: Aligned<u32, [u8; 3]> = Aligned([0; 3]);
+//!
+//! // Unaligned array
+//! static Z: [u8; 3] = [0; 3];
+//!
+//! // You can allocate the aligned arrays on the stack too
+//! let w: Aligned<u64, _> = Aligned([0u8; 3]);
+//!
+//! assert_eq!(mem::align_of_val(&X), 2);
+//! assert_eq!(mem::align_of_val(&Y), 4);
+//! assert_eq!(mem::align_of_val(&Z), 1);
+//! assert_eq!(mem::align_of_val(&w), 8);
+//! ```
+
+#![deny(missing_docs)]
+#![deny(warnings)]
+#![cfg_attr(feature = "const-fn", feature(const_fn))]
+#![no_std]
+
+use core::{mem, ops};
+
+/// An `ARRAY` aligned to `mem::align_of::<ALIGNMENT>()` bytes
+pub struct Aligned<ALIGNMENT, ARRAY>
+where
+    ARRAY: ?Sized,
+{
+    _alignment: [ALIGNMENT; 0],
+    /// The array
+    pub array: ARRAY,
+}
+
+impl<T, ALIGNMENT> ops::Deref for Aligned<ALIGNMENT, [T]> {
+    type Target = [T];
+
+    fn deref(&self) -> &Self::Target {
+        unsafe {
+            mem::transmute(self)
+        }
+    }
+}
+
+impl<T, ALIGNMENT> ops::DerefMut for Aligned<ALIGNMENT, [T]> {
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        unsafe {
+            mem::transmute(self)
+        }
+    }
+}
+
+macro_rules! slice {
+    ($($N:expr),+) => {
+        $(
+            impl<T, ALIGNMENT> ops::Deref for Aligned<ALIGNMENT, [T; $N]> {
+                type Target = Aligned<ALIGNMENT, [T]>;
+
+                fn deref(&self) -> &Self::Target {
+                    unsafe {
+                        mem::transmute(&self.array[..])
+                    }
+                }
+            }
+
+            impl<T, ALIGNMENT> ops::DerefMut for Aligned<ALIGNMENT, [T; $N]> {
+                fn deref_mut(&mut self) -> &mut Self::Target {
+                    unsafe {
+                        mem::transmute(&mut self.array[..])
+                    }
+                }
+            }
+
+            impl<T, ALIGNMENT> ops::Index<ops::RangeTo<usize>>
+                for Aligned<ALIGNMENT, [T; $N]>
+            {
+                type Output = Aligned<ALIGNMENT, [T]>;
+
+                fn index(&self, range: ops::RangeTo<usize>) -> &Self::Output {
+                    unsafe {
+                        mem::transmute(self.array.index(range))
+                    }
+                }
+            }
+
+            impl<T, ALIGNMENT> ops::IndexMut<ops::RangeTo<usize>>
+                for Aligned<ALIGNMENT, [T; $N]>
+            {
+                fn index_mut(
+                    &mut self,
+                    range: ops::RangeTo<usize>,
+                ) -> &mut Self::Output {
+                    unsafe {
+                        mem::transmute(self.array.index_mut(range))
+                    }
+                }
+            }
+        )+
+    }
+}
+
+slice!(
+    0,
+    1,
+    2,
+    3,
+    4,
+    5,
+    6,
+    7,
+    8,
+    9,
+    10,
+    11,
+    12,
+    13,
+    14,
+    15,
+    16,
+    17,
+    18,
+    19,
+    20,
+    21,
+    22,
+    23,
+    24,
+    25,
+    26,
+    27,
+    28,
+    29,
+    30,
+    31,
+    32,
+    64,
+    128,
+    256,
+    1024
+);
+
+/// IMPLEMENTATION DETAIL
+pub unsafe trait Alignment {}
+
+/// 2 byte alignment
+unsafe impl Alignment for u16 {}
+
+/// 4 byte alignment
+unsafe impl Alignment for u32 {}
+
+/// 8 byte alignment
+unsafe impl Alignment for u64 {}
+
+/// `Aligned` constructor
+#[allow(non_snake_case)]
+#[cfg(feature = "const-fn")]
+pub const fn Aligned<ALIGNMENT, ARRAY>(
+    array: ARRAY,
+) -> Aligned<ALIGNMENT, ARRAY>
+where
+    ALIGNMENT: Alignment,
+{
+    Aligned {
+        _alignment: [],
+        array: array,
+    }
+}
+
+/// `Aligned` constructor
+#[allow(non_snake_case)]
+#[cfg(not(feature = "const-fn"))]
+pub fn Aligned<ALIGNMENT, ARRAY>(
+    array: ARRAY,
+) -> Aligned<ALIGNMENT, ARRAY>
+    where
+    ALIGNMENT: Alignment,
+{
+    Aligned {
+        _alignment: [],
+        array: array,
+    }
+}
+
+#[test]
+fn sanity() {
+    use core::mem;
+
+    let x: Aligned<u16, _> = Aligned([0u8; 3]);
+    let y: Aligned<u32, _> = Aligned([0u8; 3]);
+    let z: Aligned<u64, _> = Aligned([0u8; 3]);
+
+    assert_eq!(mem::align_of_val(&x), 2);
+    assert_eq!(mem::align_of_val(&y), 4);
+    assert_eq!(mem::align_of_val(&z), 8);
+
+    assert!(x.as_ptr() as usize % 2 == 0);
+    assert!(y.as_ptr() as usize % 4 == 0);
+    assert!(z.as_ptr() as usize % 8 == 0);
+}
+
      +
      \ No newline at end of file diff --git a/src/bare_metal/lib.rs.html b/src/bare_metal/lib.rs.html new file mode 100644 index 0000000..faa6f79 --- /dev/null +++ b/src/bare_metal/lib.rs.html @@ -0,0 +1,241 @@ +lib.rs.html -- source
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+
      +//! Abstractions common to bare metal systems
+
+#![deny(missing_docs)]
+#![deny(warnings)]
+#![cfg_attr(
+    feature = "const-fn",
+    feature(const_fn)
+)]
+#![no_std]
+
+use core::cell::UnsafeCell;
+
+/// A peripheral
+#[derive(Debug)]
+pub struct Peripheral<T>
+where
+    T: 'static,
+{
+    address: *mut T,
+}
+
+impl<T> Peripheral<T> {
+    /// Creates a new peripheral
+    ///
+    /// `address` is the base address of the register block
+    #[cfg(feature = "const-fn")]
+    pub const unsafe fn new(address: usize) -> Self {
+        Peripheral {
+            address: address as *mut T,
+        }
+    }
+
+    /// Creates a new peripheral
+    ///
+    /// `address` is the base address of the register block
+    #[cfg(not(feature = "const-fn"))]
+    pub unsafe fn new(address: usize) -> Self {
+        Peripheral {
+            address: address as *mut T,
+        }
+    }
+
+    /// Borrows the peripheral for the duration of a critical section
+    pub fn borrow<'cs>(&self, _ctxt: &'cs CriticalSection) -> &'cs T {
+        unsafe { &*self.get() }
+    }
+
+    /// Returns a pointer to the register block
+    pub fn get(&self) -> *mut T {
+        self.address as *mut T
+    }
+}
+
+/// Critical section token
+///
+/// Indicates that you are executing code within a critical section
+pub struct CriticalSection {
+    _0: (),
+}
+
+impl CriticalSection {
+    /// Creates a critical section token
+    ///
+    /// This method is meant to be used to create safe abstractions rather than
+    /// meant to be directly used in applications.
+    pub unsafe fn new() -> Self {
+        CriticalSection { _0: () }
+    }
+}
+
+/// A "mutex" based on critical sections
+pub struct Mutex<T> {
+    inner: UnsafeCell<T>,
+}
+
+impl<T> Mutex<T> {
+    /// Creates a new mutex
+    #[cfg(feature = "const-fn")]
+    pub const fn new(value: T) -> Self {
+        Mutex {
+            inner: UnsafeCell::new(value),
+        }
+    }
+
+    /// Creates a new mutex
+    #[cfg(not(feature = "const-fn"))]
+    pub fn new(value: T) -> Self {
+        Mutex {
+            inner: UnsafeCell::new(value),
+        }
+    }
+}
+
+impl<T> Mutex<T> {
+    /// Borrows the data for the duration of the critical section
+    pub fn borrow<'cs>(&'cs self, _cs: &'cs CriticalSection) -> &'cs T {
+        unsafe { &*self.inner.get() }
+    }
+}
+
+/// ``` compile_fail
+/// fn bad(cs: &bare_metal::CriticalSection) -> &u32 {
+///     let x = bare_metal::Mutex::new(42u32);
+///     x.borrow(cs)
+/// }
+/// ```
+#[allow(dead_code)]
+const GH_6: () = ();
+
+/// Interrupt number
+pub unsafe trait Nr {
+    /// Returns the number associated with an interrupt
+    fn nr(&self) -> u8;
+}
+
+// NOTE A `Mutex` can be used as a channel so the protected data must be `Send`
+// to prevent sending non-Sendable stuff (e.g. access tokens) across different
+// execution contexts (e.g. interrupts)
+unsafe impl<T> Sync for Mutex<T> where T: Send {}
+
      +
      \ No newline at end of file diff --git a/src/cortex_m/asm.rs.html b/src/cortex_m/asm.rs.html new file mode 100644 index 0000000..4f75e12 --- /dev/null +++ b/src/cortex_m/asm.rs.html @@ -0,0 +1,451 @@ +asm.rs.html -- source
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+
      +//! Miscellaneous assembly instructions
+
+/// Puts the processor in Debug state. Debuggers can pick this up as a "breakpoint".
+///
+/// **NOTE** calling `bkpt` when the processor is not connected to a debugger will cause an
+/// exception.
+#[inline(always)]
+pub fn bkpt() {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => unsafe { asm!("bkpt" :::: "volatile") },
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __bkpt();
+            }
+
+            __bkpt();
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// Blocks the program for *at least* `n` instruction cycles
+///
+/// This is implemented in assembly so its execution time is the same regardless of the optimization
+/// level.
+///
+/// NOTE that the delay can take much longer if interrupts are serviced during its execution.
+#[inline]
+pub fn delay(_n: u32) {
+    // NOTE(divide by 4) is easier to compute than `/ 3` is it's just a shift (`>> 2`).
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => unsafe {
+            asm!("1:
+                  nop
+                  subs $0, $$1
+                  bne.n 1b"
+                 : "+r"(_n / 4 + 1)
+                 :
+                 :
+                 : "volatile");
+        },
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __delay(n: u32);
+            }
+
+            __delay(_n / 4 + 1);
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// A no-operation. Useful to prevent delay loops from being optimized away.
+#[inline]
+pub fn nop() {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => unsafe { asm!("nop" :::: "volatile") },
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __nop();
+            }
+
+            __nop()
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// Wait For Event
+#[inline]
+pub fn wfe() {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => unsafe { asm!("wfe" :::: "volatile") },
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __wfe();
+            }
+
+            __wfe()
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// Wait For Interrupt
+#[inline]
+pub fn wfi() {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => unsafe { asm!("wfi" :::: "volatile") },
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __wfi();
+            }
+
+            __wfi()
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// Send Event
+#[inline]
+pub fn sev() {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => unsafe { asm!("sev" :::: "volatile") },
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __sev();
+            }
+
+            __sev()
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// Instruction Synchronization Barrier
+///
+/// Flushes the pipeline in the processor, so that all instructions following the `ISB` are fetched
+/// from cache or memory, after the instruction has been completed.
+#[inline]
+pub fn isb() {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => unsafe { asm!("isb 0xF" ::: "memory" : "volatile") },
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __isb();
+            }
+
+            __isb()
+            // XXX do we need a explicit compiler barrier here?
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// Data Synchronization Barrier
+///
+/// Acts as a special kind of memory barrier. No instruction in program order after this instruction
+/// can execute until this instruction completes. This instruction completes only when both:
+///
+///  * any explicit memory access made before this instruction is complete
+///  * all cache and branch predictor maintenance operations before this instruction complete
+#[inline]
+pub fn dsb() {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => unsafe { asm!("dsb 0xF" ::: "memory" : "volatile") },
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __dsb();
+            }
+
+            __dsb()
+            // XXX do we need a explicit compiler barrier here?
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// Data Memory Barrier
+///
+/// Ensures that all explicit memory accesses that appear in program order before the `DMB`
+/// instruction are observed before any explicit memory accesses that appear in program order
+/// after the `DMB` instruction.
+#[inline]
+pub fn dmb() {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => unsafe { asm!("dmb 0xF" ::: "memory" : "volatile") },
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __dmb();
+            }
+
+            __dmb()
+            // XXX do we need a explicit compiler barrier here?
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
      +
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+
      +//! Interrupts
+
+// use core::sync::atomic::{self, Ordering};
+
+pub use bare_metal::{CriticalSection, Mutex, Nr};
+
+/// Disables all interrupts
+#[inline]
+pub fn disable() {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => unsafe {
+            asm!("cpsid i" ::: "memory" : "volatile");
+        },
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __cpsid();
+            }
+
+            // XXX do we need a explicit compiler barrier here?
+            __cpsid();
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// Enables all the interrupts
+///
+/// # Safety
+///
+/// - Do not call this function inside an `interrupt::free` critical section
+#[inline]
+pub unsafe fn enable() {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => asm!("cpsie i" ::: "memory" : "volatile"),
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => {
+            extern "C" {
+                fn __cpsie();
+            }
+
+            // XXX do we need a explicit compiler barrier here?
+            __cpsie();
+        }
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// Execute closure `f` in an interrupt-free context.
+///
+/// This as also known as a "critical section".
+pub fn free<F, R>(f: F) -> R
+where
+    F: FnOnce(&CriticalSection) -> R,
+{
+    let primask = ::register::primask::read();
+
+    // disable interrupts
+    disable();
+
+    let r = f(unsafe { &CriticalSection::new() });
+
+    // If the interrupts were active before our `disable` call, then re-enable
+    // them. Otherwise, keep them disabled
+    if primask.is_active() {
+        unsafe { enable() }
+    }
+
+    r
+}
+
      +
      \ No newline at end of file diff --git a/src/cortex_m/itm.rs.html b/src/cortex_m/itm.rs.html new file mode 100644 index 0000000..0fc16d0 --- /dev/null +++ b/src/cortex_m/itm.rs.html @@ -0,0 +1,271 @@ +itm.rs.html -- source
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+
      +//! Instrumentation Trace Macrocell
+//!
+//! **NOTE** This module is only available on ARMv7-M and newer
+
+use core::{fmt, mem, ptr, slice};
+
+use aligned::Aligned;
+
+use peripheral::itm::Stim;
+
+// NOTE assumes that `bytes` is 32-bit aligned
+unsafe fn write_words(stim: &mut Stim, bytes: &[u32]) {
+    let mut p = bytes.as_ptr();
+    for _ in 0..bytes.len() {
+        while !stim.is_fifo_ready() {}
+        stim.write_u32(ptr::read(p));
+        p = p.offset(1);
+    }
+}
+
+struct Port<'p>(&'p mut Stim);
+
+impl<'p> fmt::Write for Port<'p> {
+    fn write_str(&mut self, s: &str) -> fmt::Result {
+        write_all(self.0, s.as_bytes());
+        Ok(())
+    }
+}
+
+/// Writes a `buffer` to the ITM `port`
+pub fn write_all(port: &mut Stim, buffer: &[u8]) {
+    unsafe {
+        let mut len = buffer.len();
+        let mut ptr = buffer.as_ptr();
+
+        if len == 0 {
+            return;
+        }
+
+        // 0x01 OR 0x03
+        if ptr as usize % 2 == 1 {
+            while !port.is_fifo_ready() {}
+            port.write_u8(*ptr);
+
+            // 0x02 OR 0x04
+            ptr = ptr.offset(1);
+            len -= 1;
+        }
+
+        // 0x02
+        if ptr as usize % 4 == 2 {
+            if len > 1 {
+                // at least 2 bytes
+                while !port.is_fifo_ready() {}
+                port.write_u16(ptr::read(ptr as *const u16));
+
+                // 0x04
+                ptr = ptr.offset(2);
+                len -= 2;
+            } else {
+                if len == 1 {
+                    // last byte
+                    while !port.is_fifo_ready() {}
+                    port.write_u8(*ptr);
+                }
+
+                return;
+            }
+        }
+
+        write_aligned(port, mem::transmute(slice::from_raw_parts(ptr, len)));
+    }
+}
+
+/// Writes a 4-byte aligned `buffer` to the ITM `port`
+///
+/// # Examples
+///
+/// ``` ignore
+/// let mut buffer: Aligned<u32, _> = Aligned([0; 14]);
+///
+/// buffer.copy_from_slice(b"Hello, world!\n");
+///
+/// itm::write_aligned(&itm.stim[0], &buffer);
+///
+/// // Or equivalently
+/// itm::write_aligned(&itm.stim[0], &Aligned(*b"Hello, world!\n"));
+/// ```
+pub fn write_aligned(port: &mut Stim, buffer: &Aligned<u32, [u8]>) {
+    unsafe {
+        let len = buffer.len();
+
+        if len == 0 {
+            return;
+        }
+
+        let split = len & !0b11;
+        write_words(
+            port,
+            slice::from_raw_parts(buffer.as_ptr() as *const u32, split >> 2),
+        );
+
+        // 3 bytes or less left
+        let mut left = len & 0b11;
+        let mut ptr = buffer.as_ptr().offset(split as isize);
+
+        // at least 2 bytes left
+        if left > 1 {
+            while !port.is_fifo_ready() {}
+            port.write_u16(ptr::read(ptr as *const u16));
+
+            ptr = ptr.offset(2);
+            left -= 2;
+        }
+
+        // final byte
+        if left == 1 {
+            while !port.is_fifo_ready() {}
+            port.write_u8(*ptr);
+        }
+    }
+}
+
+/// Writes `fmt::Arguments` to the ITM `port`
+pub fn write_fmt(port: &mut Stim, args: fmt::Arguments) {
+    use core::fmt::Write;
+
+    Port(port).write_fmt(args).ok();
+}
+
+/// Writes a string to the ITM `port`
+pub fn write_str(port: &mut Stim, string: &str) {
+    write_all(port, string.as_bytes())
+}
+
      +
      \ No newline at end of file diff --git a/src/cortex_m/lib.rs.html b/src/cortex_m/lib.rs.html new file mode 100644 index 0000000..19b0f8c --- /dev/null +++ b/src/cortex_m/lib.rs.html @@ -0,0 +1,107 @@ +lib.rs.html -- source
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+
      +//! Low level access to Cortex-M processors
+//!
+//! This crate provides:
+//!
+//! - Access to core peripherals like NVIC, SCB and SysTick.
+//! - Access to core registers like CONTROL, MSP and PSR.
+//! - Interrupt manipulation mechanisms
+//! - Safe wrappers around Cortex-M specific instructions like `bkpt`
+//!
+//! # Optional features
+//!
+//! ## `inline-asm`
+//!
+//! When this feature is enabled the implementation of all the functions inside the `asm` and
+//! `register` modules use inline assembly (`asm!`) instead of external assembly (FFI into separate
+//! assembly files pre-compiled using `arm-none-eabi-gcc`). The advantages of enabling `inline-asm`
+//! are:
+//!
+//! - Reduced overhead. FFI eliminates the possibility of inlining so all operations include a
+//! function call overhead when `inline-asm` is not enabled.
+//!
+//! - Some of the `register` API only becomes available only when `inline-asm` is enabled. Check the
+//! API docs for details.
+//!
+//! The disadvantage is that `inline-asm` requires a nightly toolchain.
+//!
+//! ## `const-fn`
+//!
+//! Enabling this feature turns the `Mutex.new` constructor into a `const fn`.
+//!
+//! This feature requires a nightly toolchain.
+
+#![cfg_attr(feature = "inline-asm", feature(asm))]
+#![deny(missing_docs)]
+#![deny(warnings)]
+#![no_std]
+
+extern crate aligned;
+extern crate bare_metal;
+extern crate volatile_register;
+
+#[macro_use]
+mod macros;
+
+pub mod asm;
+pub mod interrupt;
+#[cfg(not(armv6m))]
+pub mod itm;
+pub mod peripheral;
+pub mod register;
+
+pub use peripheral::Peripherals;
+
      +
      \ No newline at end of file diff --git a/src/cortex_m/macros.rs.html b/src/cortex_m/macros.rs.html new file mode 100644 index 0000000..94e7c74 --- /dev/null +++ b/src/cortex_m/macros.rs.html @@ -0,0 +1,215 @@ +macros.rs.html -- source
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+
      +/// Macro for sending a formatted string through an ITM channel
+#[macro_export]
+macro_rules! iprint {
+    ($channel:expr, $s:expr) => {
+        $crate::itm::write_str($channel, $s);
+    };
+    ($channel:expr, $($arg:tt)*) => {
+        $crate::itm::write_fmt($channel, format_args!($($arg)*));
+    };
+}
+
+/// Macro for sending a formatted string through an ITM channel, with a newline.
+#[macro_export]
+macro_rules! iprintln {
+    ($channel:expr) => {
+        iprint!($channel, "\n");
+    };
+    ($channel:expr, $fmt:expr) => {
+        iprint!($channel, concat!($fmt, "\n"));
+    };
+    ($channel:expr, $fmt:expr, $($arg:tt)*) => {
+        iprint!($channel, concat!($fmt, "\n"), $($arg)*);
+    };
+}
+
+/// Macro to create a mutable reference to a statically allocated value
+///
+/// This macro returns a value with type `Option<&'static mut $ty>`. `Some($expr)` will be returned
+/// the first time the macro is executed; further calls will return `None`. To avoid `unwrap`ping a
+/// `None` variant the caller must ensure that the macro is called from a function that's executed
+/// at most once in the whole lifetime of the program.
+///
+/// # Example
+///
+/// ``` no_run
+/// #[macro_use(singleton)]
+/// extern crate cortex_m;
+///
+/// fn main() {
+///     // OK if `main` is executed only once
+///     let x: &'static mut bool = singleton!(: bool = false).unwrap();
+///
+///     let y = alias();
+///     // BAD this second call to `alias` will definitively `panic!`
+///     let y_alias = alias();
+/// }
+///
+/// fn alias() -> &'static mut bool {
+///     singleton!(: bool = false).unwrap()
+/// }
+/// ```
+#[macro_export]
+macro_rules! singleton {
+    (: $ty:ty = $expr:expr) => {
+        $crate::interrupt::free(|_| {
+            static mut VAR: Option<$ty> = None;
+
+            #[allow(unsafe_code)]
+            let used = unsafe { VAR.is_some() };
+            if used {
+                None
+            } else {
+                let expr = $expr;
+
+                #[allow(unsafe_code)]
+                unsafe {
+                    VAR = Some(expr)
+                }
+
+                #[allow(unsafe_code)]
+                unsafe {
+                    VAR.as_mut()
+                }
+            }
+        })
+    };
+}
+
+/// ``` compile_fail
+/// #[macro_use(singleton)]
+/// extern crate cortex_m;
+///
+/// fn main() {}
+///
+/// fn foo() {
+///     // check that the call to `uninitialized` requires unsafe
+///     singleton!(: u8 = std::mem::uninitialized());
+/// }
+/// ```
+#[allow(dead_code)]
+const CFAIL: () = ();
+
+/// ```
+/// #![deny(unsafe_code)]
+/// #[macro_use(singleton)]
+/// extern crate cortex_m;
+///
+/// fn main() {}
+///
+/// fn foo() {
+///     // check that calls to `singleton!` don't trip the `unsafe_code` lint
+///     singleton!(: u8 = 0);
+/// }
+/// ```
+#[allow(dead_code)]
+const CPASS: () = ();
+
      +
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+
      +//! Cache and branch predictor maintenance operations
+//!
+//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
+
+use volatile_register::WO;
+
+use peripheral::CBP;
+
+/// Register block
+#[repr(C)]
+pub struct RegisterBlock {
+    /// I-cache invalidate all to PoU
+    pub iciallu: WO<u32>,
+    reserved0: u32,
+    /// I-cache invalidate by MVA to PoU
+    pub icimvau: WO<u32>,
+    /// D-cache invalidate by MVA to PoC
+    pub dcimvac: WO<u32>,
+    /// D-cache invalidate by set-way
+    pub dcisw: WO<u32>,
+    /// D-cache clean by MVA to PoU
+    pub dccmvau: WO<u32>,
+    /// D-cache clean by MVA to PoC
+    pub dccmvac: WO<u32>,
+    /// D-cache clean by set-way
+    pub dccsw: WO<u32>,
+    /// D-cache clean and invalidate by MVA to PoC
+    pub dccimvac: WO<u32>,
+    /// D-cache clean and invalidate by set-way
+    pub dccisw: WO<u32>,
+    /// Branch predictor invalidate all
+    pub bpiall: WO<u32>,
+}
+
+const CBP_SW_WAY_POS: u32 = 30;
+const CBP_SW_WAY_MASK: u32 = 0x3 << CBP_SW_WAY_POS;
+const CBP_SW_SET_POS: u32 = 5;
+const CBP_SW_SET_MASK: u32 = 0x1FF << CBP_SW_SET_POS;
+
+impl CBP {
+    /// I-cache invalidate all to PoU
+    #[inline]
+    pub fn iciallu(&mut self) {
+        unsafe {
+            self.iciallu.write(0);
+        }
+    }
+
+    /// I-cache invalidate by MVA to PoU
+    #[inline]
+    pub fn icimvau(&mut self, mva: u32) {
+        unsafe {
+            self.icimvau.write(mva);
+        }
+    }
+
+    /// D-cache invalidate by MVA to PoC
+    #[inline]
+    pub fn dcimvac(&mut self, mva: u32) {
+        unsafe {
+            self.dcimvac.write(mva);
+        }
+    }
+
+    /// D-cache invalidate by set-way
+    ///
+    /// `set` is masked to be between 0 and 3, and `way` between 0 and 511.
+    #[inline]
+    pub fn dcisw(&mut self, set: u16, way: u16) {
+        // The ARMv7-M Architecture Reference Manual, as of Revision E.b, says these set/way
+        // operations have a register data format which depends on the implementation's
+        // associativity and number of sets. Specifically the 'way' and 'set' fields have
+        // offsets 32-log2(ASSOCIATIVITY) and log2(LINELEN) respectively.
+        //
+        // However, in Cortex-M7 devices, these offsets are fixed at 30 and 5, as per the Cortex-M7
+        // Generic User Guide section 4.8.3. Since no other ARMv7-M implementations except the
+        // Cortex-M7 have a DCACHE or ICACHE at all, it seems safe to do the same thing as the
+        // CMSIS-Core implementation and use fixed values.
+        unsafe {
+            self.dcisw.write(
+                (((way as u32) & (CBP_SW_WAY_MASK >> CBP_SW_WAY_POS)) << CBP_SW_WAY_POS)
+                    | (((set as u32) & (CBP_SW_SET_MASK >> CBP_SW_SET_POS)) << CBP_SW_SET_POS),
+            );
+        }
+    }
+
+    /// D-cache clean by MVA to PoU
+    #[inline]
+    pub fn dccmvau(&mut self, mva: u32) {
+        unsafe {
+            self.dccmvau.write(mva);
+        }
+    }
+
+    /// D-cache clean by MVA to PoC
+    #[inline]
+    pub fn dccmvac(&mut self, mva: u32) {
+        unsafe {
+            self.dccmvac.write(mva);
+        }
+    }
+
+    /// D-cache clean by set-way
+    ///
+    /// `set` is masked to be between 0 and 3, and `way` between 0 and 511.
+    #[inline]
+    pub fn dccsw(&mut self, set: u16, way: u16) {
+        // See comment for dcisw() about the format here
+        unsafe {
+            self.dccsw.write(
+                (((way as u32) & (CBP_SW_WAY_MASK >> CBP_SW_WAY_POS)) << CBP_SW_WAY_POS)
+                    | (((set as u32) & (CBP_SW_SET_MASK >> CBP_SW_SET_POS)) << CBP_SW_SET_POS),
+            );
+        }
+    }
+
+    /// D-cache clean and invalidate by MVA to PoC
+    #[inline]
+    pub fn dccimvac(&mut self, mva: u32) {
+        unsafe {
+            self.dccimvac.write(mva);
+        }
+    }
+
+    /// D-cache clean and invalidate by set-way
+    ///
+    /// `set` is masked to be between 0 and 3, and `way` between 0 and 511.
+    #[inline]
+    pub fn dccisw(&mut self, set: u16, way: u16) {
+        // See comment for dcisw() about the format here
+        unsafe {
+            self.dccisw.write(
+                (((way as u32) & (CBP_SW_WAY_MASK >> CBP_SW_WAY_POS)) << CBP_SW_WAY_POS)
+                    | (((set as u32) & (CBP_SW_SET_MASK >> CBP_SW_SET_POS)) << CBP_SW_SET_POS),
+            );
+        }
+    }
+
+    /// Branch predictor invalidate all
+    #[inline]
+    pub fn bpiall(&mut self) {
+        unsafe {
+            self.bpiall.write(0);
+        }
+    }
+}
+
      +
      \ No newline at end of file diff --git a/src/cortex_m/peripheral/cpuid.rs.html b/src/cortex_m/peripheral/cpuid.rs.html new file mode 100644 index 0000000..78314a6 --- /dev/null +++ b/src/cortex_m/peripheral/cpuid.rs.html @@ -0,0 +1,229 @@ +cpuid.rs.html -- source
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+
      +//! CPUID
+
+use volatile_register::RO;
+#[cfg(not(armv6m))]
+use volatile_register::RW;
+
+#[cfg(not(armv6m))]
+use peripheral::CPUID;
+
+/// Register block
+#[repr(C)]
+pub struct RegisterBlock {
+    /// CPUID base
+    pub base: RO<u32>,
+
+    _reserved0: [u32; 15],
+
+    /// Processor Feature (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
+    pub pfr: [RO<u32>; 2],
+    #[cfg(armv6m)]
+    _reserved1: [u32; 2],
+
+    /// Debug Feature (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
+    pub dfr: RO<u32>,
+    #[cfg(armv6m)]
+    _reserved2: u32,
+
+    /// Auxiliary Feature (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
+    pub afr: RO<u32>,
+    #[cfg(armv6m)]
+    _reserved3: u32,
+
+    /// Memory Model Feature (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
+    pub mmfr: [RO<u32>; 4],
+    #[cfg(armv6m)]
+    _reserved4: [u32; 4],
+
+    /// Instruction Set Attribute (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
+    pub isar: [RO<u32>; 5],
+    #[cfg(armv6m)]
+    _reserved5: [u32; 5],
+
+    _reserved6: u32,
+
+    /// Cache Level ID (only present on Cortex-M7)
+    #[cfg(not(armv6m))]
+    pub clidr: RO<u32>,
+
+    /// Cache Type (only present on Cortex-M7)
+    #[cfg(not(armv6m))]
+    pub ctr: RO<u32>,
+
+    /// Cache Size ID (only present on Cortex-M7)
+    #[cfg(not(armv6m))]
+    pub ccsidr: RO<u32>,
+
+    /// Cache Size Selection (only present on Cortex-M7)
+    #[cfg(not(armv6m))]
+    pub csselr: RW<u32>,
+}
+
+/// Type of cache to select on CSSELR writes.
+#[cfg(not(armv6m))]
+pub enum CsselrCacheType {
+    /// Select DCache or unified cache
+    DataOrUnified = 0,
+    /// Select ICache
+    Instruction = 1,
+}
+
+#[cfg(not(armv6m))]
+impl CPUID {
+    /// Selects the current CCSIDR
+    ///
+    /// * `level`: the required cache level minus 1, e.g. 0 for L1, 1 for L2
+    /// * `ind`: select instruction cache or data/unified cache
+    ///
+    /// `level` is masked to be between 0 and 7.
+    pub fn select_cache(&mut self, level: u8, ind: CsselrCacheType) {
+        const CSSELR_IND_POS: u32 = 0;
+        const CSSELR_IND_MASK: u32 = 1 << CSSELR_IND_POS;
+        const CSSELR_LEVEL_POS: u32 = 1;
+        const CSSELR_LEVEL_MASK: u32 = 0x7 << CSSELR_LEVEL_POS;
+
+        unsafe {
+            self.csselr.write(
+                (((level as u32) << CSSELR_LEVEL_POS) & CSSELR_LEVEL_MASK)
+                    | (((ind as u32) << CSSELR_IND_POS) & CSSELR_IND_MASK),
+            )
+        }
+    }
+
+    /// Returns the number of sets and ways in the selected cache
+    pub fn cache_num_sets_ways(&mut self, level: u8, ind: CsselrCacheType) -> (u16, u16) {
+        const CCSIDR_NUMSETS_POS: u32 = 13;
+        const CCSIDR_NUMSETS_MASK: u32 = 0x7FFF << CCSIDR_NUMSETS_POS;
+        const CCSIDR_ASSOCIATIVITY_POS: u32 = 3;
+        const CCSIDR_ASSOCIATIVITY_MASK: u32 = 0x3FF << CCSIDR_ASSOCIATIVITY_POS;
+
+        self.select_cache(level, ind);
+        ::asm::dsb();
+        let ccsidr = self.ccsidr.read();
+        (
+            (1 + ((ccsidr & CCSIDR_NUMSETS_MASK) >> CCSIDR_NUMSETS_POS)) as u16,
+            (1 + ((ccsidr & CCSIDR_ASSOCIATIVITY_MASK) >> CCSIDR_ASSOCIATIVITY_POS)) as u16,
+        )
+    }
+}
+
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      \ No newline at end of file diff --git a/src/cortex_m/peripheral/dcb.rs.html b/src/cortex_m/peripheral/dcb.rs.html new file mode 100644 index 0000000..a33ba6a --- /dev/null +++ b/src/cortex_m/peripheral/dcb.rs.html @@ -0,0 +1,35 @@ +dcb.rs.html -- source
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      +//! Debug Control Block
+
+use volatile_register::{RW, WO};
+
+/// Register block
+#[repr(C)]
+pub struct RegisterBlock {
+    /// Debug Halting Control and Status
+    pub dhcsr: RW<u32>,
+    /// Debug Core Register Selector
+    pub dcrsr: WO<u32>,
+    /// Debug Core Register Data
+    pub dcrdr: RW<u32>,
+    /// Debug Exception and Monitor Control
+    pub demcr: RW<u32>,
+}
+
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+
      +//! Data Watchpoint and Trace unit
+
+use volatile_register::{RO, RW, WO};
+
+use peripheral::DWT;
+
+/// Register block
+#[repr(C)]
+pub struct RegisterBlock {
+    /// Control
+    pub ctrl: RW<u32>,
+    /// Cycle Count
+    pub cyccnt: RW<u32>,
+    /// CPI Count
+    pub cpicnt: RW<u32>,
+    /// Exception Overhead Count
+    pub exccnt: RW<u32>,
+    /// Sleep Count
+    pub sleepcnt: RW<u32>,
+    /// LSU Count
+    pub lsucnt: RW<u32>,
+    /// Folded-instruction Count
+    pub foldcnt: RW<u32>,
+    /// Program Counter Sample
+    pub pcsr: RO<u32>,
+    /// Comparators
+    pub c: [Comparator; 16],
+    reserved: [u32; 932],
+    /// Lock Access
+    pub lar: WO<u32>,
+    /// Lock Status
+    pub lsr: RO<u32>,
+}
+
+/// Comparator
+#[repr(C)]
+pub struct Comparator {
+    /// Comparator
+    pub comp: RW<u32>,
+    /// Comparator Mask
+    pub mask: RW<u32>,
+    /// Comparator Function
+    pub function: RW<u32>,
+    reserved: u32,
+}
+
+impl DWT {
+    /// Enables the cycle counter
+    pub fn enable_cycle_counter(&mut self) {
+        unsafe { self.ctrl.modify(|r| r | 1) }
+    }
+
+    /// Returns the current clock cycle count
+    pub fn get_cycle_count() -> u32 {
+        // NOTE(unsafe) atomic read with no side effects
+        unsafe { (*Self::ptr()).cyccnt.read() }
+    }
+}
+
      +
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      +//! Flash Patch and Breakpoint unit
+//!
+//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
+
+use volatile_register::{RO, RW, WO};
+
+/// Register block
+#[repr(C)]
+pub struct RegisterBlock {
+    /// Control
+    pub ctrl: RW<u32>,
+    /// Remap
+    pub remap: RW<u32>,
+    /// Comparator
+    pub comp: [RW<u32>; 127],
+    reserved: [u32; 875],
+    /// Lock Access
+    pub lar: WO<u32>,
+    /// Lock Status
+    pub lsr: RO<u32>,
+}
+
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      \ No newline at end of file diff --git a/src/cortex_m/peripheral/fpu.rs.html b/src/cortex_m/peripheral/fpu.rs.html new file mode 100644 index 0000000..0234252 --- /dev/null +++ b/src/cortex_m/peripheral/fpu.rs.html @@ -0,0 +1,41 @@ +fpu.rs.html -- source
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      +//! Floating Point Unit
+//!
+//! *NOTE* Available only on ARMv7E-M (`thumbv7em-none-eabihf`)
+
+use volatile_register::{RO, RW};
+
+/// Register block
+#[repr(C)]
+pub struct RegisterBlock {
+    reserved: u32,
+    /// Floating Point Context Control
+    pub fpccr: RW<u32>,
+    /// Floating Point Context Address
+    pub fpcar: RW<u32>,
+    /// Floating Point Default Status Control
+    pub fpdscr: RW<u32>,
+    /// Media and FP Feature
+    pub mvfr: [RO<u32>; 3],
+}
+
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      +//! Instrumentation Trace Macrocell
+//!
+//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
+
+use core::cell::UnsafeCell;
+use core::ptr;
+
+use volatile_register::{RO, RW, WO};
+
+/// Register block
+#[repr(C)]
+pub struct RegisterBlock {
+    /// Stimulus Port
+    pub stim: [Stim; 256],
+    reserved0: [u32; 640],
+    /// Trace Enable
+    pub ter: [RW<u32>; 8],
+    reserved1: [u32; 8],
+    /// Trace Privilege
+    pub tpr: RW<u32>,
+    reserved2: [u32; 15],
+    /// Trace Control
+    pub tcr: RW<u32>,
+    reserved3: [u32; 75],
+    /// Lock Access
+    pub lar: WO<u32>,
+    /// Lock Status
+    pub lsr: RO<u32>,
+}
+
+/// Stimulus Port
+pub struct Stim {
+    register: UnsafeCell<u32>,
+}
+
+impl Stim {
+    /// Writes an `u8` payload into the stimulus port
+    pub fn write_u8(&mut self, value: u8) {
+        unsafe { ptr::write_volatile(self.register.get() as *mut u8, value) }
+    }
+
+    /// Writes an `u16` payload into the stimulus port
+    pub fn write_u16(&mut self, value: u16) {
+        unsafe { ptr::write_volatile(self.register.get() as *mut u16, value) }
+    }
+
+    /// Writes an `u32` payload into the stimulus port
+    pub fn write_u32(&mut self, value: u32) {
+        unsafe { ptr::write_volatile(self.register.get(), value) }
+    }
+
+    /// Returns `true` if the stimulus port is ready to accept more data
+    pub fn is_fifo_ready(&self) -> bool {
+        unsafe { ptr::read_volatile(self.register.get()) == 1 }
+    }
+}
+
      +
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+
      +//! Core peripherals
+//!
+//! # API
+//!
+//! To use (most of) the peripheral API first you must get an *instance* of the peripheral. All the
+//! core peripherals are modeled as singletons (there can only ever be, at most, one instance of any
+//! one of them at any given point in time) and the only way to get an instance of them is through
+//! the [`Peripherals::take`](struct.Peripherals.html#method.take) method.
+//!
+//! ``` no_run
+//! extern crate cortex_m;
+//!
+//! use cortex_m::peripheral::Peripherals;
+//!
+//! fn main() {
+//!     let mut peripherals = Peripherals::take().unwrap();
+//!     peripherals.DWT.enable_cycle_counter();
+//! }
+//! ```
+//!
+//! This method can only be successfully called *once* -- this is why the method returns an
+//! `Option`. Subsequent calls to the method will result in a `None` value being returned.
+//!
+//! ``` no_run
+//! extern crate cortex_m;
+//!
+//! use cortex_m::peripheral::Peripherals;
+//!
+//! fn main() {
+//!     let ok = Peripherals::take().unwrap();
+//!     let panics = Peripherals::take().unwrap();
+//! }
+//! ```
+//! A part of the peripheral API doesn't require access to a peripheral instance. This part of the
+//! API is provided as static methods on the peripheral types. One example is the
+//! [`DWT::get_cycle_count`](struct.DWT.html#method.get_cycle_count) method.
+//!
+//! ``` no_run
+//! extern crate cortex_m;
+//!
+//! use cortex_m::peripheral::{DWT, Peripherals};
+//!
+//! fn main() {
+//!     {
+//!         let mut peripherals = Peripherals::take().unwrap();
+//!         peripherals.DWT.enable_cycle_counter();
+//!     } // all the peripheral singletons are destroyed here
+//!
+//!     // but this method can be called without a DWT instance
+//!     let cyccnt = DWT::get_cycle_count();
+//! }
+//! ```
+//!
+//! The singleton property can be *unsafely* bypassed using the `ptr` static method which is
+//! available on all the peripheral types. This method is a useful building block for implementing
+//! safe higher level abstractions.
+//!
+//! ``` no_run
+//! extern crate cortex_m;
+//!
+//! use cortex_m::peripheral::{DWT, Peripherals};
+//!
+//! fn main() {
+//!     {
+//!         let mut peripherals = Peripherals::take().unwrap();
+//!         peripherals.DWT.enable_cycle_counter();
+//!     } // all the peripheral singletons are destroyed here
+//!
+//!     // actually safe because this is an atomic read with no side effects
+//!     let cyccnt = unsafe { (*DWT::ptr()).cyccnt.read() };
+//! }
+//! ```
+//!
+//! # References
+//!
+//! - ARMv7-M Architecture Reference Manual (Issue E.b) - Chapter B3
+
+// TODO stand-alone registers: ICTR, ACTLR and STIR
+
+#![allow(private_no_mangle_statics)]
+
+use core::marker::PhantomData;
+use core::ops;
+
+use interrupt;
+
+#[cfg(not(armv6m))]
+pub mod cbp;
+pub mod cpuid;
+pub mod dcb;
+pub mod dwt;
+#[cfg(not(armv6m))]
+pub mod fpb;
+// NOTE(target_arch) is for documentation purposes
+#[cfg(any(has_fpu, target_arch = "x86_64"))]
+pub mod fpu;
+#[cfg(not(armv6m))]
+pub mod itm;
+pub mod mpu;
+pub mod nvic;
+pub mod scb;
+pub mod syst;
+#[cfg(not(armv6m))]
+pub mod tpiu;
+
+#[cfg(test)]
+mod test;
+
+// NOTE the `PhantomData` used in the peripherals proxy is to make them `Send` but *not* `Sync`
+
+/// Core peripherals
+#[allow(non_snake_case)]
+pub struct Peripherals {
+    /// Cache and branch predictor maintenance operations (not present on Cortex-M0 variants)
+    pub CBP: CBP,
+
+    /// CPUID
+    pub CPUID: CPUID,
+
+    /// Debug Control Block
+    pub DCB: DCB,
+
+    /// Data Watchpoint and Trace unit
+    pub DWT: DWT,
+
+    /// Flash Patch and Breakpoint unit (not present on Cortex-M0 variants)
+    pub FPB: FPB,
+
+    /// Floating Point Unit (only present on `thumbv7em-none-eabihf`)
+    pub FPU: FPU,
+
+    /// Instrumentation Trace Macrocell (not present on Cortex-M0 variants)
+    pub ITM: ITM,
+
+    /// Memory Protection Unit
+    pub MPU: MPU,
+
+    /// Nested Vector Interrupt Controller
+    pub NVIC: NVIC,
+
+    /// System Control Block
+    pub SCB: SCB,
+
+    /// SysTick: System Timer
+    pub SYST: SYST,
+
+    /// Trace Port Interface Unit (not present on Cortex-M0 variants)
+    pub TPIU: TPIU,
+}
+
+// NOTE `no_mangle` is used here to prevent linking different minor versions of this crate as that
+// would let you `take` the core peripherals more than once (one per minor version)
+#[no_mangle]
+static mut CORE_PERIPHERALS: bool = false;
+
+impl Peripherals {
+    /// Returns all the core peripherals *once*
+    #[inline]
+    pub fn take() -> Option<Self> {
+        interrupt::free(|_| {
+            if unsafe { CORE_PERIPHERALS } {
+                None
+            } else {
+                Some(unsafe { Peripherals::steal() })
+            }
+        })
+    }
+
+    /// Unchecked version of `Peripherals::take`
+    pub unsafe fn steal() -> Self {
+        debug_assert!(!CORE_PERIPHERALS);
+
+        CORE_PERIPHERALS = true;
+
+        Peripherals {
+            CBP: CBP {
+                _marker: PhantomData,
+            },
+            CPUID: CPUID {
+                _marker: PhantomData,
+            },
+            DCB: DCB {
+                _marker: PhantomData,
+            },
+            DWT: DWT {
+                _marker: PhantomData,
+            },
+            FPB: FPB {
+                _marker: PhantomData,
+            },
+            FPU: FPU {
+                _marker: PhantomData,
+            },
+            ITM: ITM {
+                _marker: PhantomData,
+            },
+            MPU: MPU {
+                _marker: PhantomData,
+            },
+            NVIC: NVIC {
+                _marker: PhantomData,
+            },
+            SCB: SCB {
+                _marker: PhantomData,
+            },
+            SYST: SYST {
+                _marker: PhantomData,
+            },
+            TPIU: TPIU {
+                _marker: PhantomData,
+            },
+        }
+    }
+}
+
+/// Cache and branch predictor maintenance operations
+pub struct CBP {
+    _marker: PhantomData<*const ()>,
+}
+
+unsafe impl Send for CBP {}
+
+#[cfg(not(armv6m))]
+impl CBP {
+    pub(crate) unsafe fn new() -> Self {
+        CBP {
+            _marker: PhantomData,
+        }
+    }
+
+    /// Returns a pointer to the register block
+    pub fn ptr() -> *const self::cbp::RegisterBlock {
+        0xE000_EF50 as *const _
+    }
+}
+
+#[cfg(not(armv6m))]
+impl ops::Deref for CBP {
+    type Target = self::cbp::RegisterBlock;
+
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::ptr() }
+    }
+}
+
+/// CPUID
+pub struct CPUID {
+    _marker: PhantomData<*const ()>,
+}
+
+unsafe impl Send for CPUID {}
+
+impl CPUID {
+    /// Returns a pointer to the register block
+    pub fn ptr() -> *const self::cpuid::RegisterBlock {
+        0xE000_ED00 as *const _
+    }
+}
+
+impl ops::Deref for CPUID {
+    type Target = self::cpuid::RegisterBlock;
+
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::ptr() }
+    }
+}
+
+/// Debug Control Block
+pub struct DCB {
+    _marker: PhantomData<*const ()>,
+}
+
+unsafe impl Send for DCB {}
+
+impl DCB {
+    /// Returns a pointer to the register block
+    pub fn ptr() -> *const dcb::RegisterBlock {
+        0xE000_EDF0 as *const _
+    }
+}
+
+impl ops::Deref for DCB {
+    type Target = self::dcb::RegisterBlock;
+
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*DCB::ptr() }
+    }
+}
+
+/// Data Watchpoint and Trace unit
+pub struct DWT {
+    _marker: PhantomData<*const ()>,
+}
+
+unsafe impl Send for DWT {}
+
+impl DWT {
+    /// Returns a pointer to the register block
+    pub fn ptr() -> *const dwt::RegisterBlock {
+        0xE000_1000 as *const _
+    }
+}
+
+impl ops::Deref for DWT {
+    type Target = self::dwt::RegisterBlock;
+
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::ptr() }
+    }
+}
+
+/// Flash Patch and Breakpoint unit
+pub struct FPB {
+    _marker: PhantomData<*const ()>,
+}
+
+unsafe impl Send for FPB {}
+
+#[cfg(not(armv6m))]
+impl FPB {
+    /// Returns a pointer to the register block
+    pub fn ptr() -> *const fpb::RegisterBlock {
+        0xE000_2000 as *const _
+    }
+}
+
+#[cfg(not(armv6m))]
+impl ops::Deref for FPB {
+    type Target = self::fpb::RegisterBlock;
+
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::ptr() }
+    }
+}
+
+/// Floating Point Unit
+pub struct FPU {
+    _marker: PhantomData<*const ()>,
+}
+
+unsafe impl Send for FPU {}
+
+#[cfg(any(has_fpu, target_arch = "x86_64"))]
+impl FPU {
+    /// Returns a pointer to the register block
+    pub fn ptr() -> *const fpu::RegisterBlock {
+        0xE000_EF30 as *const _
+    }
+}
+
+#[cfg(any(has_fpu, target_arch = "x86_64"))]
+impl ops::Deref for FPU {
+    type Target = self::fpu::RegisterBlock;
+
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::ptr() }
+    }
+}
+
+/// Instrumentation Trace Macrocell
+pub struct ITM {
+    _marker: PhantomData<*const ()>,
+}
+
+unsafe impl Send for ITM {}
+
+#[cfg(not(armv6m))]
+impl ITM {
+    /// Returns a pointer to the register block
+    pub fn ptr() -> *mut itm::RegisterBlock {
+        0xE000_0000 as *mut _
+    }
+}
+
+#[cfg(not(armv6m))]
+impl ops::Deref for ITM {
+    type Target = self::itm::RegisterBlock;
+
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::ptr() }
+    }
+}
+
+#[cfg(not(armv6m))]
+impl ops::DerefMut for ITM {
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        unsafe { &mut *Self::ptr() }
+    }
+}
+
+/// Memory Protection Unit
+pub struct MPU {
+    _marker: PhantomData<*const ()>,
+}
+
+unsafe impl Send for MPU {}
+
+impl MPU {
+    /// Returns a pointer to the register block
+    pub fn ptr() -> *const mpu::RegisterBlock {
+        0xE000_ED90 as *const _
+    }
+}
+
+impl ops::Deref for MPU {
+    type Target = self::mpu::RegisterBlock;
+
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::ptr() }
+    }
+}
+
+/// Nested Vector Interrupt Controller
+pub struct NVIC {
+    _marker: PhantomData<*const ()>,
+}
+
+unsafe impl Send for NVIC {}
+
+impl NVIC {
+    /// Returns a pointer to the register block
+    pub fn ptr() -> *const nvic::RegisterBlock {
+        0xE000_E100 as *const _
+    }
+}
+
+impl ops::Deref for NVIC {
+    type Target = self::nvic::RegisterBlock;
+
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::ptr() }
+    }
+}
+
+/// System Control Block
+pub struct SCB {
+    _marker: PhantomData<*const ()>,
+}
+
+unsafe impl Send for SCB {}
+
+impl SCB {
+    /// Returns a pointer to the register block
+    pub fn ptr() -> *const scb::RegisterBlock {
+        0xE000_ED04 as *const _
+    }
+}
+
+impl ops::Deref for SCB {
+    type Target = self::scb::RegisterBlock;
+
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::ptr() }
+    }
+}
+
+/// SysTick: System Timer
+pub struct SYST {
+    _marker: PhantomData<*const ()>,
+}
+
+unsafe impl Send for SYST {}
+
+impl SYST {
+    /// Returns a pointer to the register block
+    pub fn ptr() -> *const syst::RegisterBlock {
+        0xE000_E010 as *const _
+    }
+}
+
+impl ops::Deref for SYST {
+    type Target = self::syst::RegisterBlock;
+
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::ptr() }
+    }
+}
+
+/// Trace Port Interface Unit
+pub struct TPIU {
+    _marker: PhantomData<*const ()>,
+}
+
+unsafe impl Send for TPIU {}
+
+#[cfg(not(armv6m))]
+impl TPIU {
+    /// Returns a pointer to the register block
+    pub fn ptr() -> *const tpiu::RegisterBlock {
+        0xE004_0000 as *const _
+    }
+}
+
+#[cfg(not(armv6m))]
+impl ops::Deref for TPIU {
+    type Target = self::tpiu::RegisterBlock;
+
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::ptr() }
+    }
+}
+
      +
      \ No newline at end of file diff --git a/src/cortex_m/peripheral/mpu.rs.html b/src/cortex_m/peripheral/mpu.rs.html new file mode 100644 index 0000000..19cbbcc --- /dev/null +++ b/src/cortex_m/peripheral/mpu.rs.html @@ -0,0 +1,63 @@ +mpu.rs.html -- source
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+
      +//! Memory Protection Unit
+
+use volatile_register::{RO, RW};
+
+/// Register block
+#[repr(C)]
+pub struct RegisterBlock {
+    /// Type
+    pub _type: RO<u32>,
+    /// Control
+    pub ctrl: RW<u32>,
+    /// Region Number
+    pub rnr: RW<u32>,
+    /// Region Base Address
+    pub rbar: RW<u32>,
+    /// Region Attribute and Size
+    pub rasr: RW<u32>,
+    /// Alias 1 of RBAR
+    pub rbar_a1: RW<u32>,
+    /// Alias 1 of RSAR
+    pub rsar_a1: RW<u32>,
+    /// Alias 2 of RBAR
+    pub rbar_a2: RW<u32>,
+    /// Alias 2 of RSAR
+    pub rsar_a2: RW<u32>,
+    /// Alias 3 of RBAR
+    pub rbar_a3: RW<u32>,
+    /// Alias 3 of RSAR
+    pub rsar_a3: RW<u32>,
+}
+
      +
      \ No newline at end of file diff --git a/src/cortex_m/peripheral/nvic.rs.html b/src/cortex_m/peripheral/nvic.rs.html new file mode 100644 index 0000000..94453e3 --- /dev/null +++ b/src/cortex_m/peripheral/nvic.rs.html @@ -0,0 +1,435 @@ +nvic.rs.html -- source
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+
      +//! Nested Vector Interrupt Controller
+
+#[cfg(not(armv6m))]
+use volatile_register::RO;
+use volatile_register::RW;
+
+use interrupt::Nr;
+use peripheral::NVIC;
+
+/// Register block
+#[repr(C)]
+pub struct RegisterBlock {
+    /// Interrupt Set-Enable
+    pub iser: [RW<u32>; 16],
+
+    _reserved0: [u32; 16],
+
+    /// Interrupt Clear-Enable
+    pub icer: [RW<u32>; 16],
+
+    _reserved1: [u32; 16],
+
+    /// Interrupt Set-Pending
+    pub ispr: [RW<u32>; 16],
+
+    _reserved2: [u32; 16],
+
+    /// Interrupt Clear-Pending
+    pub icpr: [RW<u32>; 16],
+
+    _reserved3: [u32; 16],
+
+    /// Interrupt Active Bit (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
+    pub iabr: [RO<u32>; 16],
+    #[cfg(armv6m)]
+    _reserved4: [u32; 16],
+
+    _reserved5: [u32; 48],
+
+    #[cfg(not(armv6m))]
+    /// Interrupt Priority
+    ///
+    /// On ARMv7-M, 124 word-sized registers are available. Each of those
+    /// contains of 4 interrupt priorities of 8 byte each.The architecture
+    /// specifically allows accessing those along byte boundaries, so they are
+    /// represented as 496 byte-sized registers, for convenience, and to allow
+    /// atomic priority updates.
+    ///
+    /// On ARMv6-M, the registers must only be accessed along word boundaries,
+    /// so convenient byte-sized representation wouldn't work on that
+    /// architecture.
+    pub ipr: [RW<u8>; 496],
+
+    #[cfg(armv6m)]
+    /// Interrupt Priority
+    ///
+    /// On ARMv7-M, 124 word-sized registers are available. Each of those
+    /// contains of 4 interrupt priorities of 8 byte each.The architecture
+    /// specifically allows accessing those along byte boundaries, so they are
+    /// represented as 496 byte-sized registers, for convenience, and to allow
+    /// atomic priority updates.
+    ///
+    /// On ARMv6-M, the registers must only be accessed along word boundaries,
+    /// so convenient byte-sized representation wouldn't work on that
+    /// architecture.
+    pub ipr: [RW<u32>; 8],
+}
+
+impl NVIC {
+    /// Clears `interrupt`'s pending state
+    pub fn clear_pending<I>(&mut self, interrupt: I)
+    where
+        I: Nr,
+    {
+        let nr = interrupt.nr();
+
+        unsafe { self.icpr[usize::from(nr / 32)].write(1 << (nr % 32)) }
+    }
+
+    /// Disables `interrupt`
+    pub fn disable<I>(&mut self, interrupt: I)
+    where
+        I: Nr,
+    {
+        let nr = interrupt.nr();
+
+        unsafe { self.icer[usize::from(nr / 32)].write(1 << (nr % 32)) }
+    }
+
+    /// Enables `interrupt`
+    pub fn enable<I>(&mut self, interrupt: I)
+    where
+        I: Nr,
+    {
+        let nr = interrupt.nr();
+
+        unsafe { self.iser[usize::from(nr / 32)].write(1 << (nr % 32)) }
+    }
+
+    /// Returns the NVIC priority of `interrupt`
+    ///
+    /// *NOTE* NVIC encodes priority in the highest bits of a byte so values like `1` and `2` map
+    /// to the same priority. Also for NVIC priorities, a lower value (e.g. `16`) has higher
+    /// priority (urgency) than a larger value (e.g. `32`).
+    pub fn get_priority<I>(interrupt: I) -> u8
+    where
+        I: Nr,
+    {
+        #[cfg(not(armv6m))]
+        {
+            let nr = interrupt.nr();
+            // NOTE(unsafe) atomic read with no side effects
+            unsafe { (*Self::ptr()).ipr[usize::from(nr)].read() }
+        }
+
+        #[cfg(armv6m)]
+        {
+            // NOTE(unsafe) atomic read with no side effects
+            let ipr_n = unsafe { (*Self::ptr()).ipr[Self::ipr_index(&interrupt)].read() };
+            let prio = (ipr_n >> Self::ipr_shift(&interrupt)) & 0x000000ff;
+            prio as u8
+        }
+    }
+
+    /// Is `interrupt` active or pre-empted and stacked
+    #[cfg(not(armv6m))]
+    pub fn is_active<I>(interrupt: I) -> bool
+    where
+        I: Nr,
+    {
+        let nr = interrupt.nr();
+        let mask = 1 << (nr % 32);
+
+        // NOTE(unsafe) atomic read with no side effects
+        unsafe { ((*Self::ptr()).iabr[usize::from(nr / 32)].read() & mask) == mask }
+    }
+
+    /// Checks if `interrupt` is enabled
+    pub fn is_enabled<I>(interrupt: I) -> bool
+    where
+        I: Nr,
+    {
+        let nr = interrupt.nr();
+        let mask = 1 << (nr % 32);
+
+        // NOTE(unsafe) atomic read with no side effects
+        unsafe { ((*Self::ptr()).iser[usize::from(nr / 32)].read() & mask) == mask }
+    }
+
+    /// Checks if `interrupt` is pending
+    pub fn is_pending<I>(interrupt: I) -> bool
+    where
+        I: Nr,
+    {
+        let nr = interrupt.nr();
+        let mask = 1 << (nr % 32);
+
+        // NOTE(unsafe) atomic read with no side effects
+        unsafe { ((*Self::ptr()).ispr[usize::from(nr / 32)].read() & mask) == mask }
+    }
+
+    /// Forces `interrupt` into pending state
+    pub fn set_pending<I>(&mut self, interrupt: I)
+    where
+        I: Nr,
+    {
+        let nr = interrupt.nr();
+
+        unsafe { self.ispr[usize::from(nr / 32)].write(1 << (nr % 32)) }
+    }
+
+    /// Sets the "priority" of `interrupt` to `prio`
+    ///
+    /// *NOTE* See [`get_priority`](struct.NVIC.html#method.get_priority) method for an explanation
+    /// of how NVIC priorities work.
+    ///
+    /// On ARMv6-M, updating an interrupt priority requires a read-modify-write operation. On
+    /// ARMv7-M, the operation is performed in a single atomic write operation.
+    pub unsafe fn set_priority<I>(&mut self, interrupt: I, prio: u8)
+    where
+        I: Nr,
+    {
+        #[cfg(not(armv6m))]
+        {
+            let nr = interrupt.nr();
+            self.ipr[usize::from(nr)].write(prio)
+        }
+
+        #[cfg(armv6m)]
+        {
+            self.ipr[Self::ipr_index(&interrupt)].modify(|value| {
+                let mask = 0x000000ff << Self::ipr_shift(&interrupt);
+                let prio = u32::from(prio) << Self::ipr_shift(&interrupt);
+
+                (value & !mask) | prio
+            })
+        }
+    }
+
+    #[cfg(armv6m)]
+    fn ipr_index<I>(interrupt: &I) -> usize
+    where
+        I: Nr,
+    {
+        usize::from(interrupt.nr()) / 4
+    }
+
+    #[cfg(armv6m)]
+    fn ipr_shift<I>(interrupt: &I) -> usize
+    where
+        I: Nr,
+    {
+        (usize::from(interrupt.nr()) % 4) * 8
+    }
+}
+
      +
      \ No newline at end of file diff --git a/src/cortex_m/peripheral/scb.rs.html b/src/cortex_m/peripheral/scb.rs.html new file mode 100644 index 0000000..882b9d4 --- /dev/null +++ b/src/cortex_m/peripheral/scb.rs.html @@ -0,0 +1,1237 @@ +scb.rs.html -- source
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+
      +//! System Control Block
+
+use core::ptr;
+
+use volatile_register::RW;
+
+#[cfg(not(armv6m))]
+use super::cpuid::CsselrCacheType;
+#[cfg(not(armv6m))]
+use super::CPUID;
+#[cfg(not(armv6m))]
+use super::CBP;
+use super::SCB;
+
+/// Register block
+#[repr(C)]
+pub struct RegisterBlock {
+    /// Interrupt Control and State
+    pub icsr: RW<u32>,
+
+    /// Vector Table Offset (not present on Cortex-M0 variants)
+    pub vtor: RW<u32>,
+
+    /// Application Interrupt and Reset Control
+    pub aircr: RW<u32>,
+
+    /// System Control
+    pub scr: RW<u32>,
+
+    /// Configuration and Control
+    pub ccr: RW<u32>,
+
+    /// System Handler Priority (word accessible only on Cortex-M0 variants)
+    ///
+    /// On ARMv7-M, `shpr[0]` points to SHPR1
+    ///
+    /// On ARMv6-M, `shpr[0]` points to SHPR2
+    #[cfg(not(armv6m))]
+    pub shpr: [RW<u8>; 12],
+    #[cfg(armv6m)]
+    _reserved1: u32,
+    /// System Handler Priority (word accessible only on Cortex-M0 variants)
+    ///
+    /// On ARMv7-M, `shpr[0]` points to SHPR1
+    ///
+    /// On ARMv6-M, `shpr[0]` points to SHPR2
+    #[cfg(armv6m)]
+    pub shpr: [RW<u32>; 2],
+
+    /// System Handler Control and State
+    pub shcrs: RW<u32>,
+
+    /// Configurable Fault Status (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
+    pub cfsr: RW<u32>,
+    #[cfg(armv6m)]
+    _reserved2: u32,
+
+    /// HardFault Status (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
+    pub hfsr: RW<u32>,
+    #[cfg(armv6m)]
+    _reserved3: u32,
+
+    /// Debug Fault Status (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
+    pub dfsr: RW<u32>,
+    #[cfg(armv6m)]
+    _reserved4: u32,
+
+    /// MemManage Fault Address (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
+    pub mmfar: RW<u32>,
+    #[cfg(armv6m)]
+    _reserved5: u32,
+
+    /// BusFault Address (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
+    pub bfar: RW<u32>,
+    #[cfg(armv6m)]
+    _reserved6: u32,
+
+    /// Auxiliary Fault Status (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
+    pub afsr: RW<u32>,
+    #[cfg(armv6m)]
+    _reserved7: u32,
+
+    _reserved8: [u32; 18],
+
+    /// Coprocessor Access Control (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
+    pub cpacr: RW<u32>,
+    #[cfg(armv6m)]
+    _reserved9: u32,
+}
+
+/// FPU access mode
+#[cfg(has_fpu)]
+#[derive(Clone, Copy, Debug)]
+pub enum FpuAccessMode {
+    /// FPU is not accessible
+    Disabled,
+    /// FPU is accessible in Privileged and User mode
+    Enabled,
+    /// FPU is accessible in Privileged mode only
+    Privileged,
+}
+
+#[cfg(has_fpu)]
+mod fpu_consts {
+    pub const SCB_CPACR_FPU_MASK: u32 = 0b11_11 << 20;
+    pub const SCB_CPACR_FPU_ENABLE: u32 = 0b01_01 << 20;
+    pub const SCB_CPACR_FPU_USER: u32 = 0b10_10 << 20;
+}
+
+#[cfg(has_fpu)]
+use self::fpu_consts::*;
+
+#[cfg(has_fpu)]
+impl SCB {
+    /// Shorthand for `set_fpu_access_mode(FpuAccessMode::Disabled)`
+    pub fn disable_fpu(&mut self) {
+        self.set_fpu_access_mode(FpuAccessMode::Disabled)
+    }
+
+    /// Shorthand for `set_fpu_access_mode(FpuAccessMode::Enabled)`
+    pub fn enable_fpu(&mut self) {
+        self.set_fpu_access_mode(FpuAccessMode::Enabled)
+    }
+
+    /// Gets FPU access mode
+    pub fn fpu_access_mode() -> FpuAccessMode {
+        // NOTE(unsafe) atomic read operation with no side effects
+        let cpacr = unsafe { (*Self::ptr()).cpacr.read() };
+
+        if cpacr & SCB_CPACR_FPU_MASK == SCB_CPACR_FPU_ENABLE | SCB_CPACR_FPU_USER {
+            FpuAccessMode::Enabled
+        } else if cpacr & SCB_CPACR_FPU_MASK == SCB_CPACR_FPU_ENABLE {
+            FpuAccessMode::Privileged
+        } else {
+            FpuAccessMode::Disabled
+        }
+    }
+
+    /// Sets FPU access mode
+    ///
+    /// *IMPORTANT* Any function that runs fully or partly with the FPU disabled must *not* take any
+    /// floating-point arguments or have any floating-point local variables. Because the compiler
+    /// might inline such a function into a caller that does have floating-point arguments or
+    /// variables, any such function must be also marked #[inline(never)].
+    pub fn set_fpu_access_mode(&mut self, mode: FpuAccessMode) {
+        let mut cpacr = self.cpacr.read() & !SCB_CPACR_FPU_MASK;
+        match mode {
+            FpuAccessMode::Disabled => (),
+            FpuAccessMode::Privileged => cpacr |= SCB_CPACR_FPU_ENABLE,
+            FpuAccessMode::Enabled => cpacr |= SCB_CPACR_FPU_ENABLE | SCB_CPACR_FPU_USER,
+        }
+        unsafe { self.cpacr.write(cpacr) }
+    }
+}
+
+impl SCB {
+    /// Returns the active exception number
+    pub fn vect_active() -> VectActive {
+        let icsr = unsafe { ptr::read(&(*SCB::ptr()).icsr as *const _ as *const u32) };
+
+        match icsr as u8 {
+            0 => VectActive::ThreadMode,
+            2 => VectActive::Exception(Exception::NonMaskableInt),
+            3 => VectActive::Exception(Exception::HardFault),
+            #[cfg(not(armv6m))]
+            4 => VectActive::Exception(Exception::MemoryManagement),
+            #[cfg(not(armv6m))]
+            5 => VectActive::Exception(Exception::BusFault),
+            #[cfg(not(armv6m))]
+            6 => VectActive::Exception(Exception::UsageFault),
+            #[cfg(any(armv8m, target_arch = "x86_64"))]
+            7 => VectActive::Exception(Exception::SecureFault),
+            11 => VectActive::Exception(Exception::SVCall),
+            #[cfg(not(armv6m))]
+            12 => VectActive::Exception(Exception::DebugMonitor),
+            14 => VectActive::Exception(Exception::PendSV),
+            15 => VectActive::Exception(Exception::SysTick),
+            irqn => VectActive::Interrupt { irqn: irqn - 16 },
+        }
+    }
+}
+
+/// Processor core exceptions (internal interrupts)
+#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+pub enum Exception {
+    /// Non maskable interrupt
+    NonMaskableInt,
+
+    /// Hard fault interrupt
+    HardFault,
+
+    /// Memory management interrupt (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
+    MemoryManagement,
+
+    /// Bus fault interrupt (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
+    BusFault,
+
+    /// Usage fault interrupt (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
+    UsageFault,
+
+    /// Secure fault interrupt (only on ARMv8-M)
+    #[cfg(any(armv8m, target_arch = "x86_64"))]
+    SecureFault,
+
+    /// SV call interrupt
+    SVCall,
+
+    /// Debug monitor interrupt (not present on Cortex-M0 variants)
+    #[cfg(not(armv6m))]
+    DebugMonitor,
+
+    /// Pend SV interrupt
+    PendSV,
+
+    /// System Tick interrupt
+    SysTick,
+}
+
+impl Exception {
+    /// Returns the IRQ number of this `Exception`
+    ///
+    /// The return value is always within the closed range `[-1, -14]`
+    pub fn irqn(&self) -> i8 {
+        match *self {
+            Exception::NonMaskableInt => -14,
+            Exception::HardFault => -13,
+            #[cfg(not(armv6m))]
+            Exception::MemoryManagement => -12,
+            #[cfg(not(armv6m))]
+            Exception::BusFault => -11,
+            #[cfg(not(armv6m))]
+            Exception::UsageFault => -10,
+            #[cfg(any(armv8m, target_arch = "x86_64"))]
+            Exception::SecureFault => -9,
+            Exception::SVCall => -5,
+            #[cfg(not(armv6m))]
+            Exception::DebugMonitor => -4,
+            Exception::PendSV => -2,
+            Exception::SysTick => -1,
+        }
+    }
+}
+
+/// Active exception number
+#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+pub enum VectActive {
+    /// Thread mode
+    ThreadMode,
+
+    /// Processor core exception (internal interrupts)
+    Exception(Exception),
+
+    /// Device specific exception (external interrupts)
+    Interrupt {
+        /// Interrupt number. This number is always within half open range `[0, 240)`
+        irqn: u8,
+    },
+}
+
+impl VectActive {
+    /// Converts a `byte` into `VectActive`
+    pub fn from(vect_active: u8) -> Option<Self> {
+        Some(match vect_active {
+            0 => VectActive::ThreadMode,
+            2 => VectActive::Exception(Exception::NonMaskableInt),
+            3 => VectActive::Exception(Exception::HardFault),
+            #[cfg(not(armv6m))]
+            4 => VectActive::Exception(Exception::MemoryManagement),
+            #[cfg(not(armv6m))]
+            5 => VectActive::Exception(Exception::BusFault),
+            #[cfg(not(armv6m))]
+            6 => VectActive::Exception(Exception::UsageFault),
+            #[cfg(any(armv8m, target_arch = "x86_64"))]
+            7 => VectActive::Exception(Exception::SecureFault),
+            11 => VectActive::Exception(Exception::SVCall),
+            #[cfg(not(armv6m))]
+            12 => VectActive::Exception(Exception::DebugMonitor),
+            14 => VectActive::Exception(Exception::PendSV),
+            15 => VectActive::Exception(Exception::SysTick),
+            irqn if irqn >= 16 => VectActive::Interrupt { irqn },
+            _ => return None,
+        })
+    }
+}
+
+#[cfg(not(armv6m))]
+mod scb_consts {
+    pub const SCB_CCR_IC_MASK: u32 = (1 << 17);
+    pub const SCB_CCR_DC_MASK: u32 = (1 << 16);
+}
+
+#[cfg(not(armv6m))]
+use self::scb_consts::*;
+
+#[cfg(not(armv6m))]
+impl SCB {
+    /// Enables I-Cache if currently disabled
+    #[inline]
+    pub fn enable_icache(&mut self) {
+        // Don't do anything if ICache is already enabled
+        if Self::icache_enabled() {
+            return;
+        }
+
+        // NOTE(unsafe) All CBP registers are write-only and stateless
+        let mut cbp = unsafe { CBP::new() };
+
+        // Invalidate I-Cache
+        cbp.iciallu();
+
+        // Enable I-Cache
+        unsafe { self.ccr.modify(|r| r | SCB_CCR_IC_MASK) };
+
+        ::asm::dsb();
+        ::asm::isb();
+    }
+
+    /// Disables I-Cache if currently enabled
+    #[inline]
+    pub fn disable_icache(&mut self) {
+        // Don't do anything if ICache is already disabled
+        if !Self::icache_enabled() {
+            return;
+        }
+
+        // NOTE(unsafe) All CBP registers are write-only and stateless
+        let mut cbp = unsafe { CBP::new() };
+
+        // Disable I-Cache
+        unsafe { self.ccr.modify(|r| r & !SCB_CCR_IC_MASK) };
+
+        // Invalidate I-Cache
+        cbp.iciallu();
+
+        ::asm::dsb();
+        ::asm::isb();
+    }
+
+    /// Returns whether the I-Cache is currently enabled
+    #[inline]
+    pub fn icache_enabled() -> bool {
+        ::asm::dsb();
+        ::asm::isb();
+
+        // NOTE(unsafe) atomic read with no side effects
+        unsafe { (*Self::ptr()).ccr.read() & SCB_CCR_IC_MASK == SCB_CCR_IC_MASK }
+    }
+
+    /// Invalidates I-Cache
+    #[inline]
+    pub fn invalidate_icache(&mut self) {
+        // NOTE(unsafe) All CBP registers are write-only and stateless
+        let mut cbp = unsafe { CBP::new() };
+
+        // Invalidate I-Cache
+        cbp.iciallu();
+
+        ::asm::dsb();
+        ::asm::isb();
+    }
+
+    /// Enables D-cache if currently disabled
+    #[inline]
+    pub fn enable_dcache(&mut self, cpuid: &mut CPUID) {
+        // Don't do anything if DCache is already enabled
+        if Self::dcache_enabled() {
+            return;
+        }
+
+        // Invalidate anything currently in the DCache
+        self.invalidate_dcache(cpuid);
+
+        // Now turn on the DCache
+        unsafe { self.ccr.modify(|r| r | SCB_CCR_DC_MASK) };
+
+        ::asm::dsb();
+        ::asm::isb();
+    }
+
+    /// Disables D-cache if currently enabled
+    #[inline]
+    pub fn disable_dcache(&mut self, cpuid: &mut CPUID) {
+        // Don't do anything if DCache is already disabled
+        if !Self::dcache_enabled() {
+            return;
+        }
+
+        // Turn off the DCache
+        unsafe { self.ccr.modify(|r| r & !SCB_CCR_DC_MASK) };
+
+        // Clean and invalidate whatever was left in it
+        self.clean_invalidate_dcache(cpuid);
+    }
+
+    /// Returns whether the D-Cache is currently enabled
+    #[inline]
+    pub fn dcache_enabled() -> bool {
+        ::asm::dsb();
+        ::asm::isb();
+
+        // NOTE(unsafe) atomic read with no side effects
+        unsafe { (*Self::ptr()).ccr.read() & SCB_CCR_DC_MASK == SCB_CCR_DC_MASK }
+    }
+
+    /// Invalidates D-cache
+    ///
+    /// Note that calling this while the dcache is enabled will probably wipe out your
+    /// stack, depending on optimisations, breaking returning to the call point.
+    /// It's used immediately before enabling the dcache, but not exported publicly.
+    #[inline]
+    fn invalidate_dcache(&mut self, cpuid: &mut CPUID) {
+        // NOTE(unsafe) All CBP registers are write-only and stateless
+        let mut cbp = unsafe { CBP::new() };
+
+        // Read number of sets and ways
+        let (sets, ways) = cpuid.cache_num_sets_ways(0, CsselrCacheType::DataOrUnified);
+
+        // Invalidate entire D-Cache
+        for set in 0..sets {
+            for way in 0..ways {
+                cbp.dcisw(set, way);
+            }
+        }
+
+        ::asm::dsb();
+        ::asm::isb();
+    }
+
+    /// Cleans D-cache
+    #[inline]
+    pub fn clean_dcache(&mut self, cpuid: &mut CPUID) {
+        // NOTE(unsafe) All CBP registers are write-only and stateless
+        let mut cbp = unsafe { CBP::new() };
+
+        // Read number of sets and ways
+        let (sets, ways) = cpuid.cache_num_sets_ways(0, CsselrCacheType::DataOrUnified);
+
+        for set in 0..sets {
+            for way in 0..ways {
+                cbp.dccsw(set, way);
+            }
+        }
+
+        ::asm::dsb();
+        ::asm::isb();
+    }
+
+    /// Cleans and invalidates D-cache
+    #[inline]
+    pub fn clean_invalidate_dcache(&mut self, cpuid: &mut CPUID) {
+        // NOTE(unsafe) All CBP registers are write-only and stateless
+        let mut cbp = unsafe { CBP::new() };
+
+        // Read number of sets and ways
+        let (sets, ways) = cpuid.cache_num_sets_ways(0, CsselrCacheType::DataOrUnified);
+
+        for set in 0..sets {
+            for way in 0..ways {
+                cbp.dccisw(set, way);
+            }
+        }
+
+        ::asm::dsb();
+        ::asm::isb();
+    }
+
+    /// Invalidates D-cache by address
+    ///
+    /// `addr`: the address to invalidate
+    /// `size`: size of the memory block, in number of bytes
+    ///
+    /// Invalidates cache starting from the lowest 32-byte aligned address represented by `addr`,
+    /// in blocks of 32 bytes until at least `size` bytes have been invalidated.
+    #[inline]
+    pub fn invalidate_dcache_by_address(&mut self, addr: usize, size: usize) {
+        // No-op zero sized operations
+        if size == 0 {
+            return;
+        }
+
+        // NOTE(unsafe) All CBP registers are write-only and stateless
+        let mut cbp = unsafe { CBP::new() };
+
+        ::asm::dsb();
+
+        // Cache lines are fixed to 32 bit on Cortex-M7 and not present in earlier Cortex-M
+        const LINESIZE: usize = 32;
+        let num_lines = ((size - 1) / LINESIZE) + 1;
+
+        let mut addr = addr & 0xFFFF_FFE0;
+
+        for _ in 0..num_lines {
+            cbp.dcimvac(addr as u32);
+            addr += LINESIZE;
+        }
+
+        ::asm::dsb();
+        ::asm::isb();
+    }
+
+    /// Cleans D-cache by address
+    ///
+    /// `addr`: the address to clean
+    /// `size`: size of the memory block, in number of bytes
+    ///
+    /// Cleans cache starting from the lowest 32-byte aligned address represented by `addr`,
+    /// in blocks of 32 bytes until at least `size` bytes have been cleaned.
+    #[inline]
+    pub fn clean_dcache_by_address(&mut self, addr: usize, size: usize) {
+        // No-op zero sized operations
+        if size == 0 {
+            return;
+        }
+
+        // NOTE(unsafe) All CBP registers are write-only and stateless
+        let mut cbp = unsafe { CBP::new() };
+
+        ::asm::dsb();
+
+        // Cache lines are fixed to 32 bit on Cortex-M7 and not present in earlier Cortex-M
+        const LINESIZE: usize = 32;
+        let num_lines = ((size - 1) / LINESIZE) + 1;
+
+        let mut addr = addr & 0xFFFF_FFE0;
+
+        for _ in 0..num_lines {
+            cbp.dccmvac(addr as u32);
+            addr += LINESIZE;
+        }
+
+        ::asm::dsb();
+        ::asm::isb();
+    }
+
+    /// Cleans and invalidates D-cache by address
+    ///
+    /// `addr`: the address to clean and invalidate
+    /// `size`: size of the memory block, in number of bytes
+    ///
+    /// Cleans and invalidates cache starting from the lowest 32-byte aligned address represented
+    /// by `addr`, in blocks of 32 bytes until at least `size` bytes have been cleaned and
+    /// invalidated.
+    #[inline]
+    pub fn clean_invalidate_dcache_by_address(&mut self, addr: usize, size: usize) {
+        // No-op zero sized operations
+        if size == 0 {
+            return;
+        }
+
+        // NOTE(unsafe) All CBP registers are write-only and stateless
+        let mut cbp = unsafe { CBP::new() };
+
+        ::asm::dsb();
+
+        // Cache lines are fixed to 32 bit on Cortex-M7 and not present in earlier Cortex-M
+        const LINESIZE: usize = 32;
+        let num_lines = ((size - 1) / LINESIZE) + 1;
+
+        let mut addr = addr & 0xFFFF_FFE0;
+
+        for _ in 0..num_lines {
+            cbp.dccimvac(addr as u32);
+            addr += LINESIZE;
+        }
+
+        ::asm::dsb();
+        ::asm::isb();
+    }
+}
+
+const SCB_SCR_SLEEPDEEP: u32 = 0x1 << 2;
+
+impl SCB {
+    /// Set the SLEEPDEEP bit in the SCR register
+    pub fn set_sleepdeep(&mut self) {
+        unsafe {
+            self.scr.modify(|scr| scr | SCB_SCR_SLEEPDEEP);
+        }
+    }
+
+    /// Clear the SLEEPDEEP bit in the SCR register
+    pub fn clear_sleepdeep(&mut self) {
+        unsafe {
+            self.scr.modify(|scr| scr & !SCB_SCR_SLEEPDEEP);
+        }
+    }
+}
+
+const SCB_AIRCR_VECTKEY: u32 = 0x05FA << 16;
+const SCB_AIRCR_PRIGROUP_MASK: u32 = 0x5 << 8;
+const SCB_AIRCR_SYSRESETREQ: u32 = 1 << 2;
+
+impl SCB {
+    /// Initiate a system reset request to reset the MCU
+    pub fn system_reset(&mut self) -> ! {
+        ::asm::dsb();
+        unsafe { self.aircr.modify(|r|
+            SCB_AIRCR_VECTKEY | // otherwise the write is ignored
+            r & SCB_AIRCR_PRIGROUP_MASK | // keep priority group unchanged
+            SCB_AIRCR_SYSRESETREQ // set the bit
+        ) };
+        ::asm::dsb();
+        loop { // wait for the reset
+            ::asm::nop(); // avoid rust-lang/rust#28728
+        }
+    }
+}
+
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+
      +//! SysTick: System Timer
+
+use volatile_register::{RO, RW};
+
+use peripheral::SYST;
+
+/// Register block
+#[repr(C)]
+pub struct RegisterBlock {
+    /// Control and Status
+    pub csr: RW<u32>,
+    /// Reload Value
+    pub rvr: RW<u32>,
+    /// Current Value
+    pub cvr: RW<u32>,
+    /// Calibration Value
+    pub calib: RO<u32>,
+}
+
+/// SysTick clock source
+#[derive(Clone, Copy, Debug)]
+pub enum SystClkSource {
+    /// Core-provided clock
+    Core,
+    /// External reference clock
+    External,
+}
+
+const SYST_COUNTER_MASK: u32 = 0x00ffffff;
+
+const SYST_CSR_ENABLE: u32 = 1 << 0;
+const SYST_CSR_TICKINT: u32 = 1 << 1;
+const SYST_CSR_CLKSOURCE: u32 = 1 << 2;
+const SYST_CSR_COUNTFLAG: u32 = 1 << 16;
+
+const SYST_CALIB_SKEW: u32 = 1 << 30;
+const SYST_CALIB_NOREF: u32 = 1 << 31;
+
+impl SYST {
+    /// Clears current value to 0
+    ///
+    /// After calling `clear_current()`, the next call to `has_wrapped()` will return `false`.
+    pub fn clear_current(&mut self) {
+        unsafe { self.cvr.write(0) }
+    }
+
+    /// Disables counter
+    pub fn disable_counter(&mut self) {
+        unsafe { self.csr.modify(|v| v & !SYST_CSR_ENABLE) }
+    }
+
+    /// Disables SysTick interrupt
+    pub fn disable_interrupt(&mut self) {
+        unsafe { self.csr.modify(|v| v & !SYST_CSR_TICKINT) }
+    }
+
+    /// Enables counter
+    ///
+    /// *NOTE* The reference manual indicates that:
+    ///
+    /// "The SysTick counter reload and current value are undefined at reset, the correct
+    /// initialization sequence for the SysTick counter is:
+    ///
+    /// - Program reload value
+    /// - Clear current value
+    /// - Program Control and Status register"
+    ///
+    /// The sequence translates to `self.set_reload(x); self.clear_current(); self.enable_counter()`
+    pub fn enable_counter(&mut self) {
+        unsafe { self.csr.modify(|v| v | SYST_CSR_ENABLE) }
+    }
+
+    /// Enables SysTick interrupt
+    pub fn enable_interrupt(&mut self) {
+        unsafe { self.csr.modify(|v| v | SYST_CSR_TICKINT) }
+    }
+
+    /// Gets clock source
+    ///
+    /// *NOTE* This takes `&mut self` because the read operation is side effectful and can clear the
+    /// bit that indicates that the timer has wrapped (cf. `SYST.has_wrapped`)
+    pub fn get_clock_source(&mut self) -> SystClkSource {
+        // NOTE(unsafe) atomic read with no side effects
+        let clk_source_bit = self.csr.read() & SYST_CSR_CLKSOURCE != 0;
+        match clk_source_bit {
+            false => SystClkSource::External,
+            true => SystClkSource::Core,
+        }
+    }
+
+    /// Gets current value
+    pub fn get_current() -> u32 {
+        // NOTE(unsafe) atomic read with no side effects
+        unsafe { (*Self::ptr()).cvr.read() }
+    }
+
+    /// Gets reload value
+    pub fn get_reload() -> u32 {
+        // NOTE(unsafe) atomic read with no side effects
+        unsafe { (*Self::ptr()).rvr.read() }
+    }
+
+    /// Returns the reload value with which the counter would wrap once per 10
+    /// ms
+    ///
+    /// Returns `0` if the value is not known (e.g. because the clock can
+    /// change dynamically).
+    pub fn get_ticks_per_10ms() -> u32 {
+        // NOTE(unsafe) atomic read with no side effects
+        unsafe { (*Self::ptr()).calib.read() & SYST_COUNTER_MASK }
+    }
+
+    /// Checks if an external reference clock is available
+    pub fn has_reference_clock() -> bool {
+        // NOTE(unsafe) atomic read with no side effects
+        unsafe { (*Self::ptr()).calib.read() & SYST_CALIB_NOREF == 0 }
+    }
+
+    /// Checks if the counter wrapped (underflowed) since the last check
+    ///
+    /// *NOTE* This takes `&mut self` because the read operation is side effectful and will clear
+    /// the bit of the read register.
+    pub fn has_wrapped(&mut self) -> bool {
+        self.csr.read() & SYST_CSR_COUNTFLAG != 0
+    }
+
+    /// Checks if counter is enabled
+    ///
+    /// *NOTE* This takes `&mut self` because the read operation is side effectful and can clear the
+    /// bit that indicates that the timer has wrapped (cf. `SYST.has_wrapped`)
+    pub fn is_counter_enabled(&mut self) -> bool {
+        self.csr.read() & SYST_CSR_ENABLE != 0
+    }
+
+    /// Checks if SysTick interrupt is enabled
+    ///
+    /// *NOTE* This takes `&mut self` because the read operation is side effectful and can clear the
+    /// bit that indicates that the timer has wrapped (cf. `SYST.has_wrapped`)
+    pub fn is_interrupt_enabled(&mut self) -> bool {
+        self.csr.read() & SYST_CSR_TICKINT != 0
+    }
+
+    /// Checks if the calibration value is precise
+    ///
+    /// Returns `false` if using the reload value returned by
+    /// `get_ticks_per_10ms()` may result in a period significantly deviating
+    /// from 10 ms.
+    pub fn is_precise() -> bool {
+        // NOTE(unsafe) atomic read with no side effects
+        unsafe { (*Self::ptr()).calib.read() & SYST_CALIB_SKEW == 0 }
+    }
+
+    /// Sets clock source
+    pub fn set_clock_source(&mut self, clk_source: SystClkSource) {
+        match clk_source {
+            SystClkSource::External => unsafe { self.csr.modify(|v| v & !SYST_CSR_CLKSOURCE) },
+            SystClkSource::Core => unsafe { self.csr.modify(|v| v | SYST_CSR_CLKSOURCE) },
+        }
+    }
+
+    /// Sets reload value
+    ///
+    /// Valid values are between `1` and `0x00ffffff`.
+    ///
+    /// *NOTE* To make the timer wrap every `N` ticks set the reload value to `N - 1`
+    pub fn set_reload(&mut self, value: u32) {
+        unsafe { self.rvr.write(value) }
+    }
+}
+
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      \ No newline at end of file diff --git a/src/cortex_m/peripheral/tpiu.rs.html b/src/cortex_m/peripheral/tpiu.rs.html new file mode 100644 index 0000000..130ab20 --- /dev/null +++ b/src/cortex_m/peripheral/tpiu.rs.html @@ -0,0 +1,65 @@ +tpiu.rs.html -- source
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      +//! Trace Port Interface Unit;
+//!
+//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
+
+use volatile_register::{RO, RW, WO};
+
+/// Register block
+#[repr(C)]
+pub struct RegisterBlock {
+    /// Supported Parallel Port Sizes
+    pub sspsr: RO<u32>,
+    /// Current Parallel Port Size
+    pub cspsr: RW<u32>,
+    reserved0: [u32; 2],
+    /// Asynchronous Clock Prescaler
+    pub acpr: RW<u32>,
+    reserved1: [u32; 55],
+    /// Selected Pin Control
+    pub sppr: RW<u32>,
+    reserved2: [u32; 132],
+    /// Formatter and Flush Control
+    pub ffcr: RW<u32>,
+    reserved3: [u32; 810],
+    /// Lock Access
+    pub lar: WO<u32>,
+    /// Lock Status
+    pub lsr: RO<u32>,
+    reserved4: [u32; 4],
+    /// TPIU Type
+    pub _type: RO<u32>,
+}
+
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      +//! Application Program Status Register
+
+/// Application Program Status Register
+#[derive(Clone, Copy, Debug)]
+pub struct Apsr {
+    bits: u32,
+}
+
+impl Apsr {
+    /// Returns the contents of the register as raw bits
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+
+    /// DSP overflow and saturation flag
+    pub fn q(&self) -> bool {
+        self.bits & (1 << 27) == (1 << 27)
+    }
+
+    /// Overflow flag
+    pub fn v(&self) -> bool {
+        self.bits & (1 << 28) == (1 << 28)
+    }
+
+    /// Carry or borrow flag
+    pub fn c(&self) -> bool {
+        self.bits & (1 << 29) == (1 << 29)
+    }
+
+    /// Zero flag
+    pub fn z(&self) -> bool {
+        self.bits & (1 << 30) == (1 << 30)
+    }
+
+    /// Negative flag
+    pub fn n(&self) -> bool {
+        self.bits & (1 << 31) == (1 << 31)
+    }
+}
+
+/// Reads the CPU register
+///
+/// **NOTE** This function is available if `cortex-m` is built with the `"inline-asm"` feature.
+#[inline]
+pub fn read() -> Apsr {
+    match () {
+        #[cfg(cortex_m)]
+        () => {
+            let r: u32;
+            unsafe {
+                asm!("mrs $0, APSR" : "=r"(r) ::: "volatile");
+            }
+            Apsr { bits: r }
+        }
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
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      +//! Base Priority Mask Register
+
+/// Reads the CPU register
+#[inline]
+pub fn read() -> u8 {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => {
+            let r: u32;
+            unsafe {
+                asm!("mrs $0, BASEPRI" : "=r"(r) ::: "volatile");
+            }
+            r as u8
+        }
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __basepri_r() -> u8;
+            }
+
+            __basepri_r()
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// Writes to the CPU register
+///
+/// **IMPORTANT** If you are using a Cortex-M7 device with revision r0p1 you MUST enable the
+/// `cm7-r0p1` Cargo feature or this function WILL misbehave.
+#[inline]
+pub unsafe fn write(_basepri: u8) {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => match () {
+            #[cfg(not(feature = "cm7-r0p1"))]
+            () => asm!("msr BASEPRI, $0" :: "r"(_basepri) : "memory" : "volatile"),
+            #[cfg(feature = "cm7-r0p1")]
+            () => ::interrupt::free(
+                |_| asm!("msr BASEPRI, $0" :: "r"(_basepri) : "memory" : "volatile"),
+            ),
+        },
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => match () {
+            #[cfg(not(feature = "cm7-r0p1"))]
+            () => {
+                extern "C" {
+                    fn __basepri_w(_: u8);
+                }
+
+                __basepri_w(_basepri);
+            }
+            #[cfg(feature = "cm7-r0p1")]
+            () => {
+                extern "C" {
+                    fn __basepri_w_cm7_r0p1(_: u8);
+                }
+
+                __basepri_w_cm7_r0p1(_basepri);
+            }
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
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      \ No newline at end of file diff --git a/src/cortex_m/register/basepri_max.rs.html b/src/cortex_m/register/basepri_max.rs.html new file mode 100644 index 0000000..d20dd89 --- /dev/null +++ b/src/cortex_m/register/basepri_max.rs.html @@ -0,0 +1,103 @@ +basepri_max.rs.html -- source
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+
      +//! Base Priority Mask Register (conditional write)
+
+/// Writes to BASEPRI *if*
+///
+/// - `basepri != 0` AND `basepri::read() == 0`, OR
+/// - `basepri != 0` AND `basepri < basepri::read()`
+///
+/// **IMPORTANT** If you are using a Cortex-M7 device with revision r0p1 you MUST enable the
+/// `cm7-r0p1` Cargo feature or this function WILL misbehave.
+#[inline]
+pub fn write(_basepri: u8) {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => unsafe {
+            match () {
+                #[cfg(not(feature = "cm7-r0p1"))]
+                () => asm!("msr BASEPRI_MAX, $0" :: "r"(_basepri) : "memory" : "volatile"),
+                #[cfg(feature = "cm7-r0p1")]
+                () => ::interrupt::free(
+                    |_| asm!("msr BASEPRI_MAX, $0" :: "r"(_basepri) : "memory" : "volatile"),
+                ),
+            }
+        },
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            match () {
+                #[cfg(not(feature = "cm7-r0p1"))]
+                () => {
+                    extern "C" {
+                        fn __basepri_max(_: u8);
+                    }
+
+                    __basepri_max(_basepri)
+                }
+                #[cfg(feature = "cm7-r0p1")]
+                () => {
+                    extern "C" {
+                        fn __basepri_max_cm7_r0p1(_: u8);
+                    }
+
+                    __basepri_max_cm7_r0p1(_basepri)
+                }
+            }
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
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      \ No newline at end of file diff --git a/src/cortex_m/register/control.rs.html b/src/cortex_m/register/control.rs.html new file mode 100644 index 0000000..b15db70 --- /dev/null +++ b/src/cortex_m/register/control.rs.html @@ -0,0 +1,275 @@ +control.rs.html -- source
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+
      +//! Control register
+
+/// Control register
+#[derive(Clone, Copy, Debug)]
+pub struct Control {
+    bits: u32,
+}
+
+impl Control {
+    /// Returns the contents of the register as raw bits
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+
+    /// Thread mode privilege level
+    pub fn npriv(&self) -> Npriv {
+        if self.bits & (1 << 0) == (1 << 0) {
+            Npriv::Unprivileged
+        } else {
+            Npriv::Privileged
+        }
+    }
+
+    /// Currently active stack pointer
+    pub fn spsel(&self) -> Spsel {
+        if self.bits & (1 << 1) == (1 << 1) {
+            Spsel::Psp
+        } else {
+            Spsel::Msp
+        }
+    }
+
+    /// Whether context floating-point is currently active
+    pub fn fpca(&self) -> Fpca {
+        if self.bits & (1 << 2) == (1 << 2) {
+            Fpca::Active
+        } else {
+            Fpca::NotActive
+        }
+    }
+}
+
+/// Thread mode privilege level
+#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+pub enum Npriv {
+    /// Privileged
+    Privileged,
+    /// Unprivileged
+    Unprivileged,
+}
+
+impl Npriv {
+    /// Is in privileged thread mode?
+    pub fn is_privileged(&self) -> bool {
+        *self == Npriv::Privileged
+    }
+
+    /// Is in unprivileged thread mode?
+    pub fn is_unprivileged(&self) -> bool {
+        *self == Npriv::Unprivileged
+    }
+}
+
+/// Currently active stack pointer
+#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+pub enum Spsel {
+    /// MSP is the current stack pointer
+    Msp,
+    /// PSP is the current stack pointer
+    Psp,
+}
+
+impl Spsel {
+    /// Is MSP the current stack pointer?
+    pub fn is_msp(&self) -> bool {
+        *self == Spsel::Msp
+    }
+
+    /// Is PSP the current stack pointer?
+    pub fn is_psp(&self) -> bool {
+        *self == Spsel::Psp
+    }
+}
+
+/// Whether context floating-point is currently active
+#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+pub enum Fpca {
+    /// Floating-point context active.
+    Active,
+    /// No floating-point context active
+    NotActive,
+}
+
+impl Fpca {
+    /// Is a floating-point context active?
+    pub fn is_active(&self) -> bool {
+        *self == Fpca::Active
+    }
+
+    /// Is a floating-point context not active?
+    pub fn is_not_active(&self) -> bool {
+        *self == Fpca::NotActive
+    }
+}
+
+/// Reads the CPU register
+#[inline]
+pub fn read() -> Control {
+    match () {
+        #[cfg(cortex_m)]
+        () => {
+            let r = match () {
+                #[cfg(feature = "inline-asm")]
+                () => {
+                    let r: u32;
+                    unsafe { asm!("mrs $0, CONTROL" : "=r"(r) ::: "volatile") }
+                    r
+                }
+
+                #[cfg(not(feature = "inline-asm"))]
+                () => unsafe {
+                    extern "C" {
+                        fn __control() -> u32;
+                    }
+
+                    __control()
+                },
+            };
+
+            Control { bits: r }
+        }
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
      +
      \ No newline at end of file diff --git a/src/cortex_m/register/faultmask.rs.html b/src/cortex_m/register/faultmask.rs.html new file mode 100644 index 0000000..f60b411 --- /dev/null +++ b/src/cortex_m/register/faultmask.rs.html @@ -0,0 +1,121 @@ +faultmask.rs.html -- source
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+
      +//! Fault Mask Register
+
+/// All exceptions are ...
+#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+pub enum Faultmask {
+    /// Active
+    Active,
+    /// Inactive, expect for NMI
+    Inactive,
+}
+
+impl Faultmask {
+    /// All exceptions are active
+    pub fn is_active(&self) -> bool {
+        *self == Faultmask::Active
+    }
+
+    /// All exceptions, except for NMI, are inactive
+    pub fn is_inactive(&self) -> bool {
+        *self == Faultmask::Inactive
+    }
+}
+
+/// Reads the CPU register
+#[inline]
+pub fn read() -> Faultmask {
+    match () {
+        #[cfg(cortex_m)]
+        () => {
+            let r = match () {
+                #[cfg(feature = "inline-asm")]
+                () => {
+                    let r: u32;
+                    unsafe { asm!("mrs $0, FAULTMASK" : "=r"(r) ::: "volatile") }
+                    r
+                }
+
+                #[cfg(not(feature = "inline-asm"))]
+                () => unsafe {
+                    extern "C" {
+                        fn __faultmask() -> u32;
+
+                    }
+
+                    __faultmask()
+                },
+            };
+
+            if r & (1 << 0) == (1 << 0) {
+                Faultmask::Inactive
+            } else {
+                Faultmask::Active
+            }
+        }
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
      +
      \ No newline at end of file diff --git a/src/cortex_m/register/lr.rs.html b/src/cortex_m/register/lr.rs.html new file mode 100644 index 0000000..04dec27 --- /dev/null +++ b/src/cortex_m/register/lr.rs.html @@ -0,0 +1,69 @@ +lr.rs.html -- source
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+
      +//! Link register
+
+/// Reads the CPU register
+///
+/// **NOTE** This function is available if `cortex-m` is built with the `"inline-asm"` feature.
+#[inline]
+pub fn read() -> u32 {
+    match () {
+        #[cfg(cortex_m)]
+        () => {
+            let r: u32;
+            unsafe { asm!("mov $0,R14" : "=r"(r) ::: "volatile") }
+            r
+        }
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// Writes `bits` to the CPU register
+///
+/// **NOTE** This function is available if `cortex-m` is built with the `"inline-asm"` feature.
+#[inline]
+pub unsafe fn write(_bits: u32) {
+    match () {
+        #[cfg(cortex_m)]
+        () => asm!("mov R14,$0" :: "r"(_bits) :: "volatile"),
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
      +
      \ No newline at end of file diff --git a/src/cortex_m/register/mod.rs.html b/src/cortex_m/register/mod.rs.html new file mode 100644 index 0000000..d9cd044 --- /dev/null +++ b/src/cortex_m/register/mod.rs.html @@ -0,0 +1,113 @@ +mod.rs.html -- source
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+
      +//! Processor core registers
+//!
+//! The following registers can only be accessed in PRIVILEGED mode:
+//!
+//! - BASEPRI
+//! - CONTROL
+//! - FAULTMASK
+//! - MSP
+//! - PRIMASK
+//!
+//! The rest of registers (see list below) can be accessed in either, PRIVILEGED
+//! or UNPRIVILEGED, mode.
+//!
+//! - APSR
+//! - LR
+//! - PC
+//! - PSP
+//!
+//! The following registers are NOT available on ARMv6-M devices
+//! (`thumbv6m-none-eabi`):
+//!
+//! - BASEPRI
+//! - FAULTMASK
+//!
+//! # References
+//!
+//! - Cortex-M* Devices Generic User Guide - Section 2.1.3 Core registers
+
+#[cfg(not(armv6m))]
+pub mod basepri;
+
+#[cfg(not(armv6m))]
+pub mod basepri_max;
+
+pub mod control;
+
+#[cfg(not(armv6m))]
+pub mod faultmask;
+
+pub mod msp;
+
+pub mod primask;
+
+pub mod psp;
+
+// Accessing these registers requires inline assembly because their contents are tied to the current
+// stack frame
+#[cfg(any(feature = "inline-asm", target_arch = "x86_64"))]
+pub mod apsr;
+
+#[cfg(any(feature = "inline-asm", target_arch = "x86_64"))]
+pub mod lr;
+
+#[cfg(any(feature = "inline-asm", target_arch = "x86_64"))]
+pub mod pc;
+
      +
      \ No newline at end of file diff --git a/src/cortex_m/register/msp.rs.html b/src/cortex_m/register/msp.rs.html new file mode 100644 index 0000000..97df70c --- /dev/null +++ b/src/cortex_m/register/msp.rs.html @@ -0,0 +1,97 @@ +msp.rs.html -- source
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+
      +//! Main Stack Pointer
+
+/// Reads the CPU register
+#[inline]
+pub fn read() -> u32 {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => {
+            let r;
+            unsafe { asm!("mrs $0,MSP" : "=r"(r) ::: "volatile") }
+            r
+        }
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __msp_r() -> u32;
+            }
+
+            __msp_r()
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// Writes `bits` to the CPU register
+#[inline]
+pub unsafe fn write(_bits: u32) {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => asm!("msr MSP,$0" :: "r"(_bits) :: "volatile"),
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => {
+            extern "C" {
+                fn __msp_w(_: u32);
+            }
+
+            __msp_w(_bits);
+        }
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
      +
      \ No newline at end of file diff --git a/src/cortex_m/register/pc.rs.html b/src/cortex_m/register/pc.rs.html new file mode 100644 index 0000000..690d06c --- /dev/null +++ b/src/cortex_m/register/pc.rs.html @@ -0,0 +1,69 @@ +pc.rs.html -- source
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+
      +//! Program counter
+
+/// Reads the CPU register
+///
+/// **NOTE** This function is available if `cortex-m` is built with the `"inline-asm"` feature.
+#[inline]
+pub fn read() -> u32 {
+    match () {
+        #[cfg(cortex_m)]
+        () => {
+            let r;
+            unsafe { asm!("mov $0,R15" : "=r"(r) ::: "volatile") }
+            r
+        }
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// Writes `bits` to the CPU register
+///
+/// **NOTE** This function is available if `cortex-m` is built with the `"inline-asm"` feature.
+#[inline]
+pub unsafe fn write(_bits: u32) {
+    match () {
+        #[cfg(cortex_m)]
+        () => asm!("mov R15,$0" :: "r"(_bits) :: "volatile"),
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
      +
      \ No newline at end of file diff --git a/src/cortex_m/register/primask.rs.html b/src/cortex_m/register/primask.rs.html new file mode 100644 index 0000000..5d6d879 --- /dev/null +++ b/src/cortex_m/register/primask.rs.html @@ -0,0 +1,119 @@ +primask.rs.html -- source
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+
      +//! Priority mask register
+
+/// All exceptions with configurable priority are ...
+#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+pub enum Primask {
+    /// Active
+    Active,
+    /// Inactive
+    Inactive,
+}
+
+impl Primask {
+    /// All exceptions with configurable priority are active
+    pub fn is_active(&self) -> bool {
+        *self == Primask::Active
+    }
+
+    /// All exceptions with configurable priority are inactive
+    pub fn is_inactive(&self) -> bool {
+        *self == Primask::Inactive
+    }
+}
+
+/// Reads the CPU register
+#[inline]
+pub fn read() -> Primask {
+    match () {
+        #[cfg(cortex_m)]
+        () => {
+            let r = match () {
+                #[cfg(feature = "inline-asm")]
+                () => {
+                    let r: u32;
+                    unsafe { asm!("mrs $0, PRIMASK" : "=r"(r) ::: "volatile") }
+                    r
+                }
+
+                #[cfg(not(feature = "inline-asm"))]
+                () => {
+                    extern "C" {
+                        fn __primask() -> u32;
+                    }
+
+                    unsafe { __primask() }
+                }
+            };
+
+            if r & (1 << 0) == (1 << 0) {
+                Primask::Inactive
+            } else {
+                Primask::Active
+            }
+        }
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
      +
      \ No newline at end of file diff --git a/src/cortex_m/register/psp.rs.html b/src/cortex_m/register/psp.rs.html new file mode 100644 index 0000000..b1568c3 --- /dev/null +++ b/src/cortex_m/register/psp.rs.html @@ -0,0 +1,97 @@ +psp.rs.html -- source
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      +//! Process Stack Pointer
+
+/// Reads the CPU register
+#[inline]
+pub fn read() -> u32 {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => {
+            let r;
+            unsafe { asm!("mrs $0,PSP" : "=r"(r) ::: "volatile") }
+            r
+        }
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => unsafe {
+            extern "C" {
+                fn __psp_r() -> u32;
+            }
+
+            __psp_r()
+        },
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
+/// Writes `bits` to the CPU register
+#[inline]
+pub unsafe fn write(_bits: u32) {
+    match () {
+        #[cfg(all(cortex_m, feature = "inline-asm"))]
+        () => asm!("msr PSP,$0" :: "r"(_bits) :: "volatile"),
+
+        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
+        () => {
+            extern "C" {
+                fn __psp_w(_: u32);
+            }
+
+            __psp_w(_bits);
+        }
+
+        #[cfg(not(cortex_m))]
+        () => unimplemented!(),
+    }
+}
+
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+
      +//! Minimal Cortex-M program
+//!
+//! When executed this program will hit the breakpoint set in `main`.
+//!
+//! All Cortex-M programs need to:
+//!
+//! - Contain the `#![no_main]` and `#![no_std]` attributes. Embedded programs don't use the
+//! standard Rust `main` interface or the Rust standard (`std`) library.
+//!
+//! - Define their entry point using [`entry!`] macro.
+//!
+//! [`entry!`]: https://docs.rs/cortex-m-rt/~0.5/cortex_m_rt/macro.entry.html
+//!
+//! - Define their panicking behavior, i.e. what happens when `panic!` is called. The easiest way to
+//! define a panicking behavior is to link to a [panic handler crate][0]
+//!
+//! [0]: https://crates.io/keywords/panic-impl
+//!
+//! - Define the `HardFault` handler using the [`exception!`] macro. This handler (function) is
+//! called when a hard fault exception is raised by the hardware.
+//!
+//! [`exception!`]: https://docs.rs/cortex-m-rt/~0.5/cortex_m_rt/macro..html
+//!
+//! - Define a default handler using the [`exception!`] macro. This function will be used to handle
+//! all interrupts and exceptions which have not been assigned a specific handler.
+//!
+//! ```
+//!
+//! #![no_main] // <- IMPORTANT!
+//! #![no_std]
+//!
+//! extern crate cortex_m;
+//!
+//! #[macro_use(entry, exception)]
+//! extern crate cortex_m_rt as rt;
+//!
+//! // makes `panic!` print messages to the host stderr using semihosting
+//! extern crate panic_semihosting;
+//!
+//! use cortex_m::asm;
+//! use rt::ExceptionFrame;
+//!
+//! // the program entry point is ...
+//! entry!(main);
+//!
+//! // ... this never ending function
+//! fn main() -> ! {
+//!     loop {
+//!         asm::bkpt();
+//!     }
+//! }
+//!
+//! // define the hard fault handler
+//! exception!(HardFault, hard_fault);
+//!
+//! fn hard_fault(ef: &ExceptionFrame) -> ! {
+//!     panic!("HardFault at {:#?}", ef);
+//! }
+//!
+//! // define the default exception handler
+//! exception!(*, default_handler);
+//!
+//! fn default_handler(irqn: i16) {
+//!     panic!("Unhandled exception (IRQn = {})", irqn);
+//! }
+//! ```
+// Auto-generated. Do not modify.
+
      +
      \ No newline at end of file diff --git a/src/cortex_m_quickstart/examples/_1_hello.rs.html b/src/cortex_m_quickstart/examples/_1_hello.rs.html new file mode 100644 index 0000000..f6b643b --- /dev/null +++ b/src/cortex_m_quickstart/examples/_1_hello.rs.html @@ -0,0 +1,85 @@ +_1_hello.rs.html -- source
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+
      +//! Prints "Hello, world!" on the OpenOCD console using semihosting
+//!
+//! ---
+//!
+//! ```
+//!
+//! #![no_main]
+//! #![no_std]
+//!
+//! #[macro_use]
+//! extern crate cortex_m_rt as rt;
+//! extern crate cortex_m_semihosting as sh;
+//! extern crate panic_semihosting;
+//!
+//! use core::fmt::Write;
+//!
+//! use rt::ExceptionFrame;
+//! use sh::hio;
+//!
+//! entry!(main);
+//!
+//! fn main() -> ! {
+//!     let mut stdout = hio::hstdout().unwrap();
+//!     writeln!(stdout, "Hello, world!").unwrap();
+//!
+//!     loop {}
+//! }
+//!
+//! exception!(HardFault, hard_fault);
+//!
+//! fn hard_fault(ef: &ExceptionFrame) -> ! {
+//!     panic!("HardFault at {:#?}", ef);
+//! }
+//!
+//! exception!(*, default_handler);
+//!
+//! fn default_handler(irqn: i16) {
+//!     panic!("Unhandled exception (IRQn = {})", irqn);
+//! }
+//! ```
+// Auto-generated. Do not modify.
+
      +
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+
      +//! Sends "Hello, world!" through the ITM port 0
+//!
+//! ITM is much faster than semihosting. Like 4 orders of magnitude or so.
+//!
+//! **NOTE** Cortex-M0 chips don't support ITM.
+//!
+//! You'll have to connect the microcontroller's SWO pin to the SWD interface. Note that some
+//! development boards don't provide this option.
+//!
+//! You'll need [`itmdump`] to receive the message on the host plus you'll need to uncomment two
+//! `monitor` commands in the `.gdbinit` file.
+//!
+//! [`itmdump`]: https://docs.rs/itm/0.2.1/itm/
+//!
+//! ---
+//!
+//! ```
+//!
+//! #![no_main]
+//! #![no_std]
+//!
+//! #[macro_use]
+//! extern crate cortex_m;
+//! #[macro_use]
+//! extern crate cortex_m_rt as rt;
+//! extern crate panic_semihosting;
+//!
+//! use cortex_m::{asm, Peripherals};
+//! use rt::ExceptionFrame;
+//!
+//! entry!(main);
+//!
+//! fn main() -> ! {
+//!     let mut p = Peripherals::take().unwrap();
+//!     let stim = &mut p.ITM.stim[0];
+//!
+//!     iprintln!(stim, "Hello, world!");
+//!
+//!     loop {
+//!         asm::bkpt();
+//!     }
+//! }
+//!
+//! // define the hard fault handler
+//! exception!(HardFault, hard_fault);
+//!
+//! fn hard_fault(ef: &ExceptionFrame) -> ! {
+//!     panic!("HardFault at {:#?}", ef);
+//! }
+//!
+//! // define the default exception handler
+//! exception!(*, default_handler);
+//!
+//! fn default_handler(irqn: i16) {
+//!     panic!("Unhandled exception (IRQn = {})", irqn);
+//! }
+//! ```
+// Auto-generated. Do not modify.
+
      +
      \ No newline at end of file diff --git a/src/cortex_m_quickstart/examples/_3_panic.rs.html b/src/cortex_m_quickstart/examples/_3_panic.rs.html new file mode 100644 index 0000000..c87cba0 --- /dev/null +++ b/src/cortex_m_quickstart/examples/_3_panic.rs.html @@ -0,0 +1,97 @@ +_3_panic.rs.html -- source
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+
      +//! Changing the panic handler
+//!
+//! The easiest way to change the panic handler is to use a different [panic handler crate][0].
+//!
+//! [0]: https://crates.io/keywords/panic-impl
+//!
+//! ---
+//!
+//! ```
+//!
+//! #![no_main]
+//! #![no_std]
+//!
+//! #[macro_use]
+//! extern crate cortex_m_rt as rt;
+//!
+//! // Pick one of these two panic handlers:
+//!
+//! // Reports panic messages to the host stderr using semihosting
+//! extern crate panic_semihosting;
+//!
+//! // Logs panic messages using the ITM (Instrumentation Trace Macrocell)
+//! // extern crate panic_itm;
+//!
+//! use rt::ExceptionFrame;
+//!
+//! entry!(main);
+//!
+//! fn main() -> ! {
+//!     panic!("Oops")
+//! }
+//!
+//! // define the hard fault handler
+//! exception!(HardFault, hard_fault);
+//!
+//! fn hard_fault(ef: &ExceptionFrame) -> ! {
+//!     panic!("HardFault at {:#?}", ef);
+//! }
+//!
+//! // define the default exception handler
+//! exception!(*, default_handler);
+//!
+//! fn default_handler(irqn: i16) {
+//!     panic!("Unhandled exception (IRQn = {})", irqn);
+//! }
+//! ```
+// Auto-generated. Do not modify.
+
      +
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+
      +//! Debugging a crash (exception)
+//!
+//! Most crash conditions trigger a hard fault exception, whose handler is defined via
+//! `exception!(HardFault, ..)`. The `HardFault` handler has access to the exception frame, a
+//! snapshot of the CPU registers at the moment of the exception.
+//!
+//! This program crashes and the `HardFault` handler prints to the console the contents of the
+//! `ExceptionFrame` and then triggers a breakpoint. From that breakpoint one can see the backtrace
+//! that led to the exception.
+//!
+//! ``` text
+//! (gdb) continue
+//! Program received signal SIGTRAP, Trace/breakpoint trap.
+//! __bkpt () at asm/bkpt.s:3
+//! 3         bkpt
+//!
+//! (gdb) backtrace
+//! #0  __bkpt () at asm/bkpt.s:3
+//! #1  0x080030b4 in cortex_m::asm::bkpt () at $$/cortex-m-0.5.0/src/asm.rs:19
+//! #2  rust_begin_unwind (args=..., file=..., line=99, col=5) at $$/panic-semihosting-0.2.0/src/lib.rs:87
+//! #3  0x08001d06 in core::panicking::panic_fmt () at libcore/panicking.rs:71
+//! #4  0x080004a6 in crash::hard_fault (ef=0x20004fa0) at examples/crash.rs:99
+//! #5  0x08000548 in UserHardFault (ef=0x20004fa0) at <exception macros>:10
+//! #6  0x0800093a in HardFault () at asm.s:5
+//! Backtrace stopped: previous frame identical to this frame (corrupt stack?)
+//! ```
+//!
+//! In the console output one will find the state of the Program Counter (PC) register at the time
+//! of the exception.
+//!
+//! ``` text
+//! panicked at 'HardFault at ExceptionFrame {
+//!     r0: 0x2fffffff,
+//!     r1: 0x2fffffff,
+//!     r2: 0x080051d4,
+//!     r3: 0x080051d4,
+//!     r12: 0x20000000,
+//!     lr: 0x08000435,
+//!     pc: 0x08000ab6,
+//!     xpsr: 0x61000000
+//! }', examples/crash.rs:106:5
+//! ```
+//!
+//! This register contains the address of the instruction that caused the exception. In GDB one can
+//! disassemble the program around this address to observe the instruction that caused the
+//! exception.
+//!
+//! ``` text
+//! (gdb) disassemble/m 0x08000ab6
+//! Dump of assembler code for function core::ptr::read_volatile:
+//! 451     pub unsafe fn read_volatile<T>(src: *const T) -> T {
+//!    0x08000aae <+0>:     sub     sp, #16
+//!    0x08000ab0 <+2>:     mov     r1, r0
+//!    0x08000ab2 <+4>:     str     r0, [sp, #8]
+//!
+//! 452         intrinsics::volatile_load(src)
+//!    0x08000ab4 <+6>:     ldr     r0, [sp, #8]
+//! -> 0x08000ab6 <+8>:     ldr     r0, [r0, #0]
+//!    0x08000ab8 <+10>:    str     r0, [sp, #12]
+//!    0x08000aba <+12>:    ldr     r0, [sp, #12]
+//!    0x08000abc <+14>:    str     r1, [sp, #4]
+//!    0x08000abe <+16>:    str     r0, [sp, #0]
+//!    0x08000ac0 <+18>:    b.n     0x8000ac2 <core::ptr::read_volatile+20>
+//!
+//! 453     }
+//!    0x08000ac2 <+20>:    ldr     r0, [sp, #0]
+//!    0x08000ac4 <+22>:    add     sp, #16
+//!    0x08000ac6 <+24>:    bx      lr
+//!
+//! End of assembler dump.
+//! ```
+//!
+//! `ldr r0, [r0, #0]` caused the exception. This instruction tried to load (read) a 32-bit word
+//! from the address stored in the register `r0`. Looking again at the contents of `ExceptionFrame`
+//! we see that the `r0` contained the address `0x2FFF_FFFF` when this instruction was executed.
+//!
+//! ---
+//!
+//! ```
+//!
+//! #![no_main]
+//! #![no_std]
+//!
+//! extern crate cortex_m;
+//! #[macro_use]
+//! extern crate cortex_m_rt as rt;
+//! extern crate panic_semihosting;
+//!
+//! use core::ptr;
+//!
+//! use rt::ExceptionFrame;
+//!
+//! entry!(main);
+//!
+//! fn main() -> ! {
+//!     unsafe {
+//!         // read an address outside of the RAM region; causes a HardFault exception
+//!         ptr::read_volatile(0x2FFF_FFFF as *const u32);
+//!     }
+//!
+//!     loop {}
+//! }
+//!
+//! // define the hard fault handler
+//! exception!(HardFault, hard_fault);
+//!
+//! fn hard_fault(ef: &ExceptionFrame) -> ! {
+//!     panic!("HardFault at {:#?}", ef);
+//! }
+//!
+//! // define the default exception handler
+//! exception!(*, default_handler);
+//!
+//! fn default_handler(irqn: i16) {
+//!     panic!("Unhandled exception (IRQn = {})", irqn);
+//! }
+//! ```
+// Auto-generated. Do not modify.
+
      +
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+
      +//! Overriding an exception handler
+//!
+//! You can override an exception handler using the [`exception!`][1] macro.
+//!
+//! [1]: https://docs.rs/cortex-m-rt/0.5.0/cortex_m_rt/macro.exception.html
+//!
+//! ---
+//!
+//! ```
+//!
+//! #![deny(unsafe_code)]
+//! #![no_main]
+//! #![no_std]
+//!
+//! extern crate cortex_m;
+//! #[macro_use]
+//! extern crate cortex_m_rt as rt;
+//! extern crate cortex_m_semihosting as sh;
+//! extern crate panic_semihosting;
+//!
+//! use core::fmt::Write;
+//!
+//! use cortex_m::peripheral::syst::SystClkSource;
+//! use cortex_m::Peripherals;
+//! use rt::ExceptionFrame;
+//! use sh::hio::{self, HStdout};
+//!
+//! entry!(main);
+//!
+//! fn main() -> ! {
+//!     let p = Peripherals::take().unwrap();
+//!     let mut syst = p.SYST;
+//!
+//!     // configures the system timer to trigger a SysTick exception every second
+//!     syst.set_clock_source(SystClkSource::Core);
+//!     syst.set_reload(8_000_000); // period = 1s
+//!     syst.enable_counter();
+//!     syst.enable_interrupt();
+//!
+//!     loop {}
+//! }
+//!
+//! // try commenting out this line: you'll end in `default_handler` instead of in `sys_tick`
+//! exception!(SysTick, sys_tick, state: Option<HStdout> = None);
+//!
+//! fn sys_tick(state: &mut Option<HStdout>) {
+//!     if state.is_none() {
+//!         *state = Some(hio::hstdout().unwrap());
+//!     }
+//!
+//!     if let Some(hstdout) = state.as_mut() {
+//!         hstdout.write_str(".").unwrap();
+//!     }
+//! }
+//!
+//! exception!(HardFault, hard_fault);
+//!
+//! fn hard_fault(ef: &ExceptionFrame) -> ! {
+//!     panic!("HardFault at {:#?}", ef);
+//! }
+//!
+//! exception!(*, default_handler);
+//!
+//! fn default_handler(irqn: i16) {
+//!     panic!("Unhandled exception (IRQn = {})", irqn);
+//! }
+//! ```
+// Auto-generated. Do not modify.
+
      +
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+
      +//! How to use the heap and a dynamic memory allocator
+//!
+//! This example depends on the alloc-cortex-m crate so you'll have to add it to your Cargo.toml:
+//!
+//! ``` text
+//! # or edit the Cargo.toml file manually
+//! $ cargo add alloc-cortex-m
+//! ```
+//!
+//! ---
+//!
+//! ```
+//!
+//! #![feature(alloc)]
+//! #![feature(global_allocator)]
+//! #![feature(lang_items)]
+//! #![no_main]
+//! #![no_std]
+//!
+//! // This is the allocator crate; you can use a different one
+//! extern crate alloc_cortex_m;
+//! #[macro_use]
+//! extern crate alloc;
+//! extern crate cortex_m;
+//! #[macro_use]
+//! extern crate cortex_m_rt as rt;
+//! extern crate cortex_m_semihosting as sh;
+//! extern crate panic_semihosting;
+//!
+//! use core::fmt::Write;
+//!
+//! use alloc_cortex_m::CortexMHeap;
+//! use cortex_m::asm;
+//! use rt::ExceptionFrame;
+//! use sh::hio;
+//!
+//! // this is the allocator the application will use
+//! #[global_allocator]
+//! static ALLOCATOR: CortexMHeap = CortexMHeap::empty();
+//!
+//! const HEAP_SIZE: usize = 1024; // in bytes
+//!
+//! entry!(main);
+//!
+//! fn main() -> ! {
+//!     // Initialize the allocator BEFORE you use it
+//!     unsafe { ALLOCATOR.init(rt::heap_start() as usize, HEAP_SIZE) }
+//!
+//!     // Growable array allocated on the heap
+//!     let xs = vec![0, 1, 2];
+//!
+//!     let mut stdout = hio::hstdout().unwrap();
+//!     writeln!(stdout, "{:?}", xs).unwrap();
+//!
+//!     loop {}
+//! }
+//!
+//! // define what happens in an Out Of Memory (OOM) condition
+//! #[lang = "oom"]
+//! #[no_mangle]
+//! pub fn rust_oom() -> ! {
+//!     asm::bkpt();
+//!
+//!     loop {}
+//! }
+//!
+//! exception!(HardFault, hard_fault);
+//!
+//! fn hard_fault(ef: &ExceptionFrame) -> ! {
+//!     panic!("HardFault at {:#?}", ef);
+//! }
+//!
+//! exception!(*, default_handler);
+//!
+//! fn default_handler(irqn: i16) {
+//!     panic!("Unhandled exception (IRQn = {})", irqn);
+//! }
+//! ```
+// Auto-generated. Do not modify.
+
      +
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+
      +//! Using a device crate
+//!
+//! Crates generated using [`svd2rust`] are referred to as device crates. These crates provide an
+//! API to access the peripherals of a device.
+//!
+//! [`svd2rust`]: https://crates.io/crates/svd2rust
+//!
+//! Device crates also provide an `interrupt!` macro (behind the "rt" feature) to register interrupt
+//! handlers.
+//!
+//! This example depends on the [`stm32f103xx`] crate so you'll have to add it to your Cargo.toml.
+//!
+//! [`stm32f103xx`]: https://crates.io/crates/stm32f103xx
+//!
+//! ```
+//! $ edit Cargo.toml && tail $_
+//! [dependencies.stm32f103xx]
+//! features = ["rt"]
+//! version = "0.10.0"
+//! ```
+//!
+//! ---
+//!
+//! ```
+//!
+//! #![no_main]
+//! #![no_std]
+//!
+//! extern crate cortex_m;
+//! #[macro_use]
+//! extern crate cortex_m_rt as rt;
+//! extern crate cortex_m_semihosting as sh;
+//! #[macro_use]
+//! extern crate stm32f103xx;
+//! extern crate panic_semihosting;
+//!
+//! use core::fmt::Write;
+//!
+//! use cortex_m::peripheral::syst::SystClkSource;
+//! use rt::ExceptionFrame;
+//! use sh::hio::{self, HStdout};
+//! use stm32f103xx::Interrupt;
+//!
+//! entry!(main);
+//!
+//! fn main() -> ! {
+//!     let p = cortex_m::Peripherals::take().unwrap();
+//!
+//!     let mut syst = p.SYST;
+//!     let mut nvic = p.NVIC;
+//!
+//!     nvic.enable(Interrupt::EXTI0);
+//!
+//!     // configure the system timer to wrap around every second
+//!     syst.set_clock_source(SystClkSource::Core);
+//!     syst.set_reload(8_000_000); // 1s
+//!     syst.enable_counter();
+//!
+//!     loop {
+//!         // busy wait until the timer wraps around
+//!         while !syst.has_wrapped() {}
+//!
+//!         // trigger the `EXTI0` interrupt
+//!         nvic.set_pending(Interrupt::EXTI0);
+//!     }
+//! }
+//!
+//! // try commenting out this line: you'll end in `default_handler` instead of in `exti0`
+//! interrupt!(EXTI0, exti0, state: Option<HStdout> = None);
+//!
+//! fn exti0(state: &mut Option<HStdout>) {
+//!     if state.is_none() {
+//!         *state = Some(hio::hstdout().unwrap());
+//!     }
+//!
+//!     if let Some(hstdout) = state.as_mut() {
+//!         hstdout.write_str(".").unwrap();
+//!     }
+//! }
+//!
+//! exception!(HardFault, hard_fault);
+//!
+//! fn hard_fault(ef: &ExceptionFrame) -> ! {
+//!     panic!("HardFault at {:#?}", ef);
+//! }
+//!
+//! exception!(*, default_handler);
+//!
+//! fn default_handler(irqn: i16) {
+//!     panic!("Unhandled exception (IRQn = {})", irqn);
+//! }
+//! ```
+// Auto-generated. Do not modify.
+
      +
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      +//! Examples sorted in increasing degree of complexity
+// Auto-generated. Do not modify.
+pub mod _0_minimal;
+pub mod _1_hello;
+pub mod _2_itm;
+pub mod _3_panic;
+pub mod _4_crash;
+pub mod _5_exception;
+pub mod _6_allocator;
+pub mod _7_device;
+
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+
      +//! A template for building applications for ARM Cortex-M microcontrollers
+//!
+//! # Dependencies
+//!
+//! - Nightly Rust toolchain from 2018-08-28 or newer: `rustup default nightly`
+//! - Cargo `clone` subcommand: `cargo install cargo-clone`
+//! - GDB: `sudo apt-get install gdb-arm-none-eabi` (on Ubuntu)
+//! - OpenOCD: `sudo apt-get install OpenOCD` (on Ubuntu)
+//! - [Optional] Cargo `add` subcommand: `cargo install cargo-edit`
+//!
+//! # Usage
+//!
+//! 0) Figure out the cross compilation *target* to use.
+//!
+//! - Use `thumbv6m-none-eabi` for ARM Cortex-M0 and Cortex-M0+
+//! - Use `thumbv7m-none-eabi` for ARM Cortex-M3
+//! - Use `thumbv7em-none-eabi` for ARM Cortex-M4 and Cortex-M7 (*no* FPU support)
+//! - Use `thumbv7em-none-eabihf` for ARM Cortex-M4**F** and Cortex-M7**F** (*with* FPU support)
+//!
+//! 1) Install the `rust-std` component for your target, if you haven't done so already
+//!
+//! ``` console
+//! $ rustup target add thumbv7em-none-eabihf
+//! ```
+//!
+//! 2) Clone this crate
+//!
+//! ``` text
+//! $ cargo clone cortex-m-quickstart --vers 0.3.4
+//! ```
+//!
+//! 3) Change the crate name, author and version
+//!
+//! ``` text
+//! $ edit Cargo.toml && head $_
+//! [package]
+//! authors = ["Jorge Aparicio <jorge@japaric.io>"]
+//! name = "demo"
+//! version = "0.1.0"
+//! ```
+//!
+//! 4) Specify the memory layout of the target device
+//!
+//! **NOTE** board support crates sometimes provide this file for you (check the crate
+//! documentation). If you are using one that does then remove *both* `memory.x` and `build.rs` from
+//! the root of this crate.
+//!
+//! ``` text
+//! $ cat >memory.x <<'EOF'
+//! MEMORY
+//! {
+//!   /* NOTE K = KiBi = 1024 bytes */
+//!   FLASH : ORIGIN = 0x08000000, LENGTH = 256K
+//!   RAM : ORIGIN = 0x20000000, LENGTH = 40K
+//! }
+//! EOF
+//! ```
+//!
+//! 5) Optionally, set a default build target. This way you don't have to pass `--target` to each
+//! Cargo invocation.
+//!
+//! ``` text
+//! $ cat >>.cargo/config <<'EOF'
+//! [build]
+//! target = "thumbv7em-none-eabihf"
+//! EOF
+//! ```
+//!
+//! 6) Optionally, depend on a device, HAL implementation or a board support crate.
+//!
+//! ``` text
+//! $ # add a device crate, OR
+//! $ cargo add stm32f30x
+//!
+//! $ # add a HAL implementation crate, OR
+//! $ cargo add stm32f30x-hal
+//!
+//! $ # add a board support crate
+//! $ cargo add f3
+//! ```
+//!
+//! 7) Write the application or start from one of the examples
+//!
+//! ``` text
+//! $ rm -r src/* && cp examples/hello.rs src/main.rs
+//! ```
+//!
+//! 8) Build the application
+//!
+//! ``` text
+//! $ cargo build --release
+//!
+//! $ # sanity check
+//! $ arm-none-eabi-readelf -A target/thumbv7em-none-eabihf/release/demo
+//! Attribute Section: aeabi
+//! File Attributes
+//!   Tag_conformance: "2.09"
+//!   Tag_CPU_arch: v7E-M
+//!   Tag_CPU_arch_profile: Microcontroller
+//!   Tag_THUMB_ISA_use: Thumb-2
+//!   Tag_FP_arch: VFPv4-D16
+//!   Tag_ABI_PCS_GOT_use: direct
+//!   Tag_ABI_FP_denormal: Needed
+//!   Tag_ABI_FP_exceptions: Needed
+//!   Tag_ABI_FP_number_model: IEEE 754
+//!   Tag_ABI_align_needed: 8-byte
+//!   Tag_ABI_align_preserved: 8-byte, except leaf SP
+//!   Tag_ABI_HardFP_use: SP only
+//!   Tag_ABI_VFP_args: VFP registers
+//!   Tag_ABI_optimization_goals: Aggressive Speed
+//!   Tag_CPU_unaligned_access: v6
+//!   Tag_FP_HP_extension: Allowed
+//!   Tag_ABI_FP_16bit_format: IEEE 754
+//! ```
+//!
+//! 9) Flash and debug the program
+//!
+//! ``` text
+//! $ # Launch OpenOCD on a terminal
+//! $ openocd -f (..)
+//! ```
+//!
+//! ``` text
+//! $ # Start a debug session in another terminal
+//! $ arm-none-eabi-gdb target/thumbv7em-none-eabihf/release/demo
+//! ```
+//!
+//! Alternatively, you can use `cargo run` to build, flash and debug the program in a single step.
+//!
+//! ``` text
+//! $ cargo run --example hello
+//! > # drops you into a GDB session
+//! ```
+//!
+//! # Examples
+//!
+//! Check the [examples module][examples]
+//!
+//! [examples]: ./examples/index.html
+//!
+//! # Troubleshooting
+//!
+//! This section contains fixes for common errors encountered when the
+//! `cortex-m-quickstart` template is misused.
+//!
+//! ## Used the standard `main` interface
+//!
+//! Error message:
+//!
+//! ``` text
+//! $ cargo build
+//!    Compiling demo v0.1.0 (file:///home/japaric/tmp/demo)
+//!
+//! error: requires `start` lang_item
+//! ```
+//!
+//! Solution: Use `#![no_main]` and `entry!` as shown in the [examples].
+//!
+//! ## Forgot to launch an OpenOCD instance
+//!
+//! Error message:
+//!
+//! ``` text
+//! $ arm-none-eabi-gdb target/..
+//! Reading symbols from hello...done.
+//! .gdbinit:1: Error in sourced command file:
+//! :3333: Connection timed out.
+//! ```
+//!
+//! Solution: Launch OpenOCD on other terminal. See [Usage] section.
+//!
+//! [Usage]: ./index.html#usage
+//!
+//! ## Didn't modify the `memory.x` linker script
+//!
+//! Error message:
+//!
+//! ``` text
+//! $ cargo build
+//! Compiling demo v0.1.0 (file:///home/japaric/tmp/demo)
+//! error: linking with `rust-lld` failed: exit code: 1
+//! |
+//! = note: "rust-lld" "-flavor" "gnu" "-L" (..)
+//! (..)
+//!  = note: rust-lld: error: section '.vector_table' will not fit in region 'FLASH': overflowed by X bytes
+//!          rust-lld: error: section '.vector_table' will not fit in region 'FLASH': overflowed by Y bytes
+//! (..)
+//! ```
+//!
+//! Solution: Specify your device memory layout in the `memory.x` linker script. See [Usage]
+//! section.
+//!
+//! ## Didn't set a default build target and forgot to pass `--target` to Cargo
+//!
+//! Error message:
+//!
+//! ``` text
+//! $ cargo build
+//! (..)
+//! error: language item required, but not found: `eh_personality`
+//!
+//! error: aborting due to previous error
+//! ```
+//!
+//! Solution: Set a default build target in the `.cargo/config` file (see [Usage] section), or call
+//! Cargo with `--target` flag: `cargo build --target thumbv7em-none-eabi`.
+//!
+//! ## Overwrote the original `.cargo/config` file
+//!
+//! You won't get an error message but the output binary will be empty
+//!
+//! ``` text
+//! $ cargo build && echo OK
+//! OK
+//!
+//! $ size target/thumbv7m-none-eabi/debug/app
+//!    text    data     bss     dec     hex filename
+//!       0       0       0       0       0 target/thumbv7m-none-eabi/debug/app
+//! ```
+//!
+//! Solution: You probably overwrote the original `.cargo/config` instead of appending the default
+//! build target (e.g. `cat >` instead of `cat >>`). The less error prone way to fix this is to
+//! remove the `.cargo` directory, clone a new copy of the template and then copy the `.cargo`
+//! directory from that fresh template into your current project. Don't forget to *append* the
+//! default build target to `.cargo/config`.
+//!
+//! ## Called OpenOCD with wrong arguments
+//!
+//! Error message:
+//!
+//! ``` text
+//! $ openocd -f ..
+//! (..)
+//! Error: open failed
+//! in procedure 'init'
+//! in procedure 'ocd_bouncer'
+//! ```
+//!
+//! Solution: Correct the OpenOCD arguments. Check the `/usr/share/openocd/scripts` directory (exact
+//! location varies per distribution / OS) for a list of scripts that can be used.
+//!
+//! ## Forgot to install the `rust-std` component
+//!
+//! Error message:
+//!
+//! ``` text
+//! $ cargo build
+//! error[E0463]: can't find crate for `core`
+//!   |
+//!   = note: the `thumbv7m-none-eabi` target may not be installed
+//! ```
+//!
+//! Solution: call `rustup target add thumbv7m-none-eabi` but with the name of your target
+//!
+//! ## Used an old nightly
+//!
+//! Error message:
+//!
+//! ``` text
+//! $ cargo build
+//! Compiling cortex-m-rt v0.2.0
+//! error[E0463]: can't find crate for `core`
+//! |
+//! = note: the `thumbv7em-none-eabihf` target may not be installed
+//!
+//! error: aborting due to previous error
+//! ```
+//!
+//! Solution: Use a more recent nightly
+//!
+//! ## Used the stable toolchain
+//!
+//! Error message:
+//!
+//! ``` text
+//! $ cargo build
+//! error[E0463]: can't find crate for `core`
+//!   |
+//!   = note: the `thumbv7em-none-eabihf` target may not be installed
+//! ```
+//!
+//! Solution: We are not there yet! Switch to the nightly toolchain with `rustup default nightly`.
+//!
+//! ## Used `gdb` instead of `arm-none-eabi-gdb`
+//!
+//! Error message:
+//!
+//! ``` text
+//! $ gdb target/..
+//! Reading symbols from hello...done.
+//! warning: Architecture rejected target-supplied description
+//! warning: Cannot convert floating-point register value to ..
+//! value has been optimized out
+//! Cannot write the dashboard
+//! Traceback (most recent call last):
+//! File "<string>", line 353, in render
+//! File "<string>", line 846, in lines
+//! gdb.error: Frame is invalid.
+//! 0x00000000 in ?? ()
+//! semihosting is enabled
+//! Loading section .text, size 0xd88 lma 0x8000000
+//! Start address 0x8000000, load size 3464
+//! .gdbinit:6: Error in sourced command file:
+//! Remote connection closed
+//! ```
+//!
+//! Solution: Use `arm-none-eabi-gdb target/..`
+//!
+//! # Used a named piped for `itm.fifo`
+//!
+//! Error message:
+//!
+//! ``` text
+//! $ cargo run [--example ..]
+//!
+//! Reading symbols from target/thumbv7em-none-eabihf/debug/cortex-m-quickstart...done.
+//! cortex_m_rt::reset_handler ()
+//!     at $REGISTRY/cortex-m-rt-0.3.12/src/lib.rs:330
+//! 330     unsafe extern "C" fn reset_handler() -> ! {
+//! semihosting is enabled
+//! Ignoring packet error, continuing...
+//! Ignoring packet error, continuing...
+//! ```
+//!
+//! Note that when you reach this point OpenOCD will become unresponsive and you'll have to kill it
+//! and start a new OpenOCD process before you can invoke `cargo run` / start GDB.
+//!
+//! Cause: You uncommented the `monitor tpiu ..` line in `.gdbinit` and are using a named pipe to
+//! receive the ITM data (i.e. you ran `mkfifo itm.fifo`). This error occurs when `itmdump -f
+//! itm.fifo` (or equivalent, e.g. `cat itm.fifo`) is not running.
+//!
+//! Solution: Run `itmdump -f itm.fifo` (or equivalently `cat itm.fifo`) *before* invoking `cargo
+//! run` / starting GDB. Note that sometimes `itmdump` will exit when the GDB session ends. In that
+//! case you'll have to run `itmdump` before you start the next GDB session.
+//!
+//! Alternative solution: Use a plain text file instead of a named pipe. In this scenario you omit
+//! the `mkfifo itm.dump` command. You can use `itmdump`'s *follow* mode (-F) to get named pipe like
+//! output.
+
+#![no_std]
+
+pub mod examples;
+
      +
      \ No newline at end of file diff --git a/src/cortex_m_rt/lib.rs.html b/src/cortex_m_rt/lib.rs.html new file mode 100644 index 0000000..b125d34 --- /dev/null +++ b/src/cortex_m_rt/lib.rs.html @@ -0,0 +1,1855 @@ +lib.rs.html -- source
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+
      +//! Minimal startup / runtime for Cortex-M microcontrollers
+//!
+//! This crate contains all the required parts to build a `no_std` application (binary crate) that
+//! targets a Cortex-M microcontroller.
+//!
+//! # Features
+//!
+//! This crates takes care of:
+//!
+//! - The memory layout of the program. In particular, it populates the vector table so the device
+//! can boot correctly, and properly dispatch exceptions and interrupts.
+//!
+//! - Initializing `static` variables before the program entry point.
+//!
+//! - Enabling the FPU before the program entry point if the target is `thumbv7em-none-eabihf`.
+//!
+//! This crate also provides a mechanism to set exception handlers: see the [`exception!`] macro.
+//!
+//! [`exception!`]: macro.exception.html
+//!
+//! # Requirements
+//!
+//! ## `memory.x`
+//!
+//! This crate expects the user, or some other crate, to provide the memory layout of the target
+//! device via a linker script named `memory.x`. This section covers the contents of `memory.x`
+//!
+//! ### `MEMORY`
+//!
+//! The linker script must specify the memory available in the device as, at least, two `MEMORY`
+//! regions: one named `FLASH` and one named `RAM`. The `.text` and `.rodata` sections of the
+//! program will be placed in the `FLASH` region, whereas the `.bss` and `.data` sections, as well
+//! as the heap,will be placed in the `RAM` region.
+//!
+//! ``` text
+//! /* Linker script for the STM32F103C8T6 */
+//! MEMORY
+//! {
+//!   FLASH : ORIGIN = 0x08000000, LENGTH = 64K
+//!   RAM : ORIGIN = 0x20000000, LENGTH = 20K
+//! }
+//! ```
+//!
+//! ### `_stack_start`
+//!
+//! This optional symbol can be used to indicate where the call stack of the program should be
+//! placed. If this symbol is not used then the stack will be placed at the *end* of the `RAM`
+//! region -- the stack grows downwards towards smaller address. This symbol can be used to place
+//! the stack in a different memory region, for example:
+//!
+//! ``` text
+//! /* Linker script for the STM32F303VCT6 */
+//! MEMORY
+//! {
+//!     FLASH : ORIGIN = 0x08000000, LENGTH = 256K
+//!
+//!     /* .bss, .data and the heap go in this region */
+//!     RAM : ORIGIN = 0x20000000, LENGTH = 40K
+//!
+//!     /* Core coupled (faster) RAM dedicated to hold the stack */
+//!     CCRAM : ORIGIN = 0x10000000, LENGTH = 8K
+//! }
+//!
+//! _stack_start = ORIGIN(CCRAM) + LENGTH(CCRAM);
+//! ```
+//!
+//! ### `_stext`
+//!
+//! This optional symbol can be used to control where the `.text` section is placed. If omitted the
+//! `.text` section will be placed right after the vector table, which is placed at the beginning of
+//! `FLASH`. Some devices store settings like Flash configuration right after the vector table;
+//! for these devices one must place the `.text` section after this configuration section --
+//! `_stext` can be used for this purpose.
+//!
+//! ``` text
+//! MEMORY
+//! {
+//!   /* .. */
+//! }
+//!
+//! /* The device stores Flash configuration in 0x400-0x40C so we place .text after that */
+//! _stext = ORIGIN(FLASH) + 0x40C
+//! ```
+//!
+//! # An example
+//!
+//! This section presents a minimal application built on top of `cortex-m-rt`. Apart from the
+//! mandatory `memory.x` linker script describing the memory layout of the device, the hard fault
+//! handler and the default exception handler must also be defined somewhere in the dependency
+//! graph (cf. [`exception!`]). In this example we define them in the binary crate:
+//!
+//! ``` ignore
+//! // IMPORTANT the standard `main` interface is not used because it requires nightly
+//! #![no_main]
+//! #![no_std]
+//!
+//! #[macro_use(entry, exception)]
+//! extern crate cortex_m_rt as rt;
+//!
+//! // makes `panic!` print messages to the host stderr using semihosting
+//! extern crate panic_semihosting;
+//!
+//! use rt::ExceptionFrame;
+//!
+//! // use `main` as the entry point of this application
+//! entry!(main);
+//!
+//! // `main` is not allowed to return
+//! fn main() -> ! {
+//!     // initialization
+//!
+//!     loop {
+//!         // application logic
+//!     }
+//! }
+//!
+//! // define the hard fault handler
+//! exception!(HardFault, hard_fault);
+//!
+//! fn hard_fault(ef: &ExceptionFrame) -> ! {
+//!     panic!("{:#?}", ef);
+//! }
+//!
+//! // define the default exception handler
+//! exception!(*, default_handler);
+//!
+//! fn default_handler(irqn: i16) {
+//!     panic!("unhandled exception (IRQn={})", irqn);
+//! }
+//! ```
+//!
+//! To actually build this program you need to place a `memory.x` linker script somewhere the linker
+//! can find it, e.g. in the current directory; and then link the program using `cortex-m-rt`'s
+//! linker script: `link.x`. The required steps are shown below:
+//!
+//! ``` text
+//! $ cat > memory.x <<EOF
+//! /* Linker script for the STM32F103C8T6 */
+//! MEMORY
+//! {
+//!   FLASH : ORIGIN = 0x08000000, LENGTH = 64K
+//!   RAM : ORIGIN = 0x20000000, LENGTH = 20K
+//! }
+//! EOF
+//!
+//! $ cargo rustc --target thumbv7m-none-eabi -- \
+//!       -C link-arg=-nostartfiles -C link-arg=-Tlink.x
+//!
+//! $ file target/thumbv7m-none-eabi/debug/app
+//! app: ELF 32-bit LSB executable, ARM, EABI5 version 1 (SYSV), statically linked, (..)
+//! ```
+//!
+//! # Optional features
+//!
+//! ## `device`
+//!
+//! If this feature is disabled then this crate populates the whole vector table. All the interrupts
+//! in the vector table, even the ones unused by the target device, will be bound to the default
+//! exception handler. This makes the final application device agnostic: you will be able to run it
+//! on any Cortex-M device -- provided that you correctly specified its memory layout in `memory.x`
+//! -- without hitting undefined behavior.
+//!
+//! If this feature is enabled then the interrupts section of the vector table is left unpopulated
+//! and some other crate, or the user, will have to populate it. This mode is meant to be used in
+//! conjunction with crates generated using `svd2rust`. Those *device crates* will populate the
+//! missing part of the vector table when their `"rt"` feature is enabled.
+//!
+//! # Inspection
+//!
+//! This section covers how to inspect a binary that builds on top of `cortex-m-rt`.
+//!
+//! ## Sections (`size`)
+//!
+//! `cortex-m-rt` uses standard sections like `.text`, `.rodata`, `.bss` and `.data` as one would
+//! expect. `cortex-m-rt` separates the vector table in its own section, named `.vector_table`. This
+//! lets you distinguish how much space is taking the vector table in Flash vs how much is being
+//! used by actual instructions (`.text`) and constants (`.rodata`).
+//!
+//! ```
+//! $ size -Ax target/thumbv7m-none-eabi/examples/app
+//! target/thumbv7m-none-eabi/release/examples/app  :
+//! section             size         addr
+//! .vector_table      0x400    0x8000000
+//! .text               0x88    0x8000400
+//! .rodata              0x0    0x8000488
+//! .data                0x0   0x20000000
+//! .bss                 0x0   0x20000000
+//! ```
+//!
+//! Without the `-A` argument `size` reports the sum of the sizes of `.text`, `.rodata` and
+//! `.vector_table` under "text".
+//!
+//! ```
+//! $ size target/thumbv7m-none-eabi/examples/app
+//!   text    data     bss     dec     hex filename
+//!   1160       0       0    1660     67c target/thumbv7m-none-eabi/release/app
+//! ```
+//!
+//! ## Symbols (`objdump`, `nm`)
+//!
+//! One will always find the following (unmangled) symbols in `cortex-m-rt` applications:
+//!
+//! - `Reset`. This is the reset handler. The microcontroller will executed this function upon
+//! booting. This function will call the user program entry point (cf. [`entry!`]) using the `main`
+//! symbol so you may also find that symbol in your program; if you do, `main` will contain your
+//! application code. Some other times `main` gets inlined into `Reset` so you won't find it.
+//!
+//! [`entry!`]:  macro.entry.html
+//!
+//! - `DefaultHandler`. This is the default handler. This function will contain, or call, the
+//! function you declared in the second argument of `exception!(*, ..)`.
+//!
+//! - `HardFault`. This is the hard fault handler. This function is simply a trampoline that jumps
+//! into the user defined hard fault handler: `UserHardFault`. The trampoline is required to set up
+//! the pointer to the stacked exception frame.
+//!
+//! - `UserHardFault`. This is the user defined hard fault handler. This function will contain, or
+//! call, the function you declared in the second argument of `exception!(HardFault, ..)`
+//!
+//! - `__STACK_START`. This is the first entry in the `.vector_table` section. This symbol contains
+//! the initial value of the stack pointer; this is where the stack will be located -- the stack
+//! grows downwards towards smaller addresses.
+//!
+//! - `__RESET_VECTOR`. This is the reset vector, a pointer into the `Reset` handler. This vector is
+//! located in the `.vector_table` section after `__STACK_START`.
+//!
+//! - `__EXCEPTIONS`. This is the core exceptions portion of the vector table; it's an array of 14
+//! exception vectors, which includes exceptions like `HardFault` and `SysTick`. This array is
+//! located after `__RESET_VECTOR` in the `.vector_table` section.
+//!
+//! - `__EXCEPTIONS`. This is the device specific interrupt portion of the vector table; its exact
+//! size depends on the target device but if the `"device"` feature has not been enabled it will
+//! have a size of 32 vectors (on ARMv6-M) or 240 vectors (on ARMv7-M). This array is located after
+//! `__EXCEPTIONS` in the `.vector_table` section.
+//!
+//! - `__pre_init`. This is a function to be run before RAM is initialized. It defaults to an empty
+//! function. The function called can be changed by calling the `pre_init!` macro. The empty
+//! function is not optimized out by default, but if an empty function is passed to `pre_init!` the
+//! function call will be optimized out.
+//!
+//! If you override any exception handler you'll find it as an unmangled symbol, e.g. `SysTick` or
+//! `SVCall`, in the output of `objdump`,
+//!
+//! If you are targeting the `thumbv7em-none-eabihf` target you'll also see a `ResetTrampoline`
+//! symbol in the output. To avoid the compiler placing FPU instructions before the FPU has been
+//! enabled (cf. `vpush`) `Reset` calls the function `ResetTrampoline` which is marked as
+//! `#[inline(never)]` and `ResetTrampoline` calls `main`. The compiler is free to inline `main`
+//! into `ResetTrampoline` but it can't inline `ResetTrampoline` into `Reset` -- the FPU is enabled
+//! in `Reset`.
+//!
+//! # Advanced usage
+//!
+//! ## Setting the program entry point
+//!
+//! This section describes how `entry!` is implemented. This information is useful to developers who
+//! want to provide an alternative to `entry!` that provides extra guarantees.
+//!
+//! The `Reset` handler will call a symbol named `main` (unmangled) *after* initializing `.bss` and
+//! `.data`, and enabling the FPU (if the target is `thumbv7em-none-eabihf`). `entry!` provides this
+//! symbol in its expansion:
+//!
+//! ``` ignore
+//! entry!(path::to::main);
+//!
+//! // expands into
+//!
+//! #[export_name = "main"]
+//! pub extern "C" fn __impl_main() -> ! {
+//!     // validate the signature of the program entry point
+//!     let f: fn() -> ! = path::to::main;
+//!
+//!     f()
+//! }
+//! ```
+//!
+//! The unmangled `main` symbol must have signature `extern "C" fn() -> !` or its invocation from
+//! `Reset`  will result in undefined behavior.
+//!
+//! ## Incorporating device specific interrupts
+//!
+//! This section covers how an external crate can insert device specific interrupt handlers into the
+//! vector table. Most users don't need to concern themselves with these details, but if you are
+//! interested in how device crates generated using `svd2rust` integrate with `cortex-m-rt` read on.
+//!
+//! The information in this section applies when the `"device"` feature has been enabled.
+//!
+//! ### `__INTERRUPTS`
+//!
+//! The external crate must provide the interrupts portion of the vector table via a `static`
+//! variable named`__INTERRUPTS` (unmangled) that must be placed in the `.vector_table.interrupts`
+//! section of its object file.
+//!
+//! This `static` variable will be placed at `ORIGIN(FLASH) + 0x40`. This address corresponds to the
+//! spot where IRQ0 (IRQ number 0) is located.
+//!
+//! To conform to the Cortex-M ABI `__INTERRUPTS` must be an array of function pointers; some spots
+//! in this array may need to be set to 0 if they are marked as *reserved* in the data sheet /
+//! reference manual. We recommend using a `union` to set the reserved spots to `0`; `None`
+//! (`Option<fn()>`) may also work but it's not guaranteed that the `None` variant will *always* be
+//! represented by the value `0`.
+//!
+//! Let's illustrate with an artificial example where a device only has two interrupt: `Foo`, with
+//! IRQ number = 2, and `Bar`, with IRQ number = 4.
+//!
+//! ``` ignore
+//! union Vector {
+//!     handler: extern "C" fn(),
+//!     reserved: usize,
+//! }
+//!
+//! extern "C" {
+//!     fn Foo();
+//!     fn Bar();
+//! }
+//!
+//! #[link_section = ".vector_table.interrupts"]
+//! #[no_mangle]
+//! pub static __INTERRUPTS: [Vector; 5] = [
+//!     // 0-1: Reserved
+//!     Vector { reserved: 0 },
+//!     Vector { reserved: 0 },
+//!
+//!     // 2: Foo
+//!     Vector { handler: Foo },
+//!
+//!     // 3: Reserved
+//!     Vector { reserved: 0 },
+//!
+//!     // 4: Bar
+//!     Vector { handler: Bar },
+//! ];
+//! ```
+//!
+//! ### `device.x`
+//!
+//! Linking in `__INTERRUPTS` creates a bunch of undefined references. If the user doesn't set a
+//! handler for *all* the device specific interrupts then linking will fail with `"undefined
+//! reference"` errors.
+//!
+//! We want to provide a default handler for all the interrupts while still letting the user
+//! individually override each interrupt handler. In C projects, this is usually accomplished using
+//! weak aliases declared in external assembly files. In Rust, we could achieve something similar
+//! using `global_asm!`, but that's an unstable feature.
+//!
+//! A solution that doesn't require `global_asm!` or external assembly files is to use the `PROVIDE`
+//! command in a linker script to create the weak aliases. This is the approach that `cortex-m-rt`
+//! uses; when the `"device"` feature is enabled `cortex-m-rt`'s linker script (`link.x`) depends on
+//! a linker script named `device.x`. The crate that provides `__INTERRUPTS` must also provide this
+//! file.
+//!
+//! For our running example the `device.x` linker script looks like this:
+//!
+//! ``` text
+//! /* device.x */
+//! PROVIDE(Foo = DefaultHandler);
+//! PROVIDE(Bar = DefaultHandler);
+//! ```
+//!
+//! This weakly aliases both `Foo` and `Bar`. `DefaultHandler` is the default exception handler that
+//! the user provides via `exception!(*, ..)` and that the core exceptions use unless overridden.
+//!
+//! Because this linker script is provided by a dependency of the final application the dependency
+//! must contain build script that puts `device.x` somewhere the linker can find. An example of such
+//! build script is shown below:
+//!
+//! ``` ignore
+//! use std::env;
+//! use std::fs::File;
+//! use std::io::Write;
+//! use std::path::PathBuf;
+//!
+//! fn main() {
+//!     // Put the linker script somewhere the linker can find it
+//!     let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+//!     File::create(out.join("device.x"))
+//!         .unwrap()
+//!         .write_all(include_bytes!("device.x"))
+//!         .unwrap();
+//!     println!("cargo:rustc-link-search={}", out.display());
+//! }
+//! ```
+//!
+//! ## `pre_init!`
+//!
+//! A user-defined function can be run at the start of the reset handler, before RAM is
+//! initialized. The macro `pre_init!` can be called to set the function to be run. The function is
+//! intended to perform actions that cannot wait the time it takes for RAM to be initialized, such
+//! as disabling a watchdog. As the function is called before RAM is initialized, any access of
+//! static variables will result in undefined behavior.
+
+// # Developer notes
+//
+// - `link_section` is used to place symbols in specific places of the final binary. The names used
+// here will appear in the linker script (`link.x`) in conjunction with the `KEEP` command.
+
+#![deny(missing_docs)]
+#![deny(warnings)]
+#![no_std]
+
+extern crate r0;
+
+use core::fmt;
+use core::sync::atomic::{self, Ordering};
+
+/// Registers stacked (pushed into the stack) during an exception
+#[derive(Clone, Copy)]
+#[repr(C)]
+pub struct ExceptionFrame {
+    /// (General purpose) Register 0
+    pub r0: u32,
+
+    /// (General purpose) Register 1
+    pub r1: u32,
+
+    /// (General purpose) Register 2
+    pub r2: u32,
+
+    /// (General purpose) Register 3
+    pub r3: u32,
+
+    /// (General purpose) Register 12
+    pub r12: u32,
+
+    /// Linker Register
+    pub lr: u32,
+
+    /// Program Counter
+    pub pc: u32,
+
+    /// Program Status Register
+    pub xpsr: u32,
+}
+
+impl fmt::Debug for ExceptionFrame {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        struct Hex(u32);
+        impl fmt::Debug for Hex {
+            fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+                write!(f, "0x{:08x}", self.0)
+            }
+        }
+        f.debug_struct("ExceptionFrame")
+            .field("r0", &Hex(self.r0))
+            .field("r1", &Hex(self.r1))
+            .field("r2", &Hex(self.r2))
+            .field("r3", &Hex(self.r3))
+            .field("r12", &Hex(self.r12))
+            .field("lr", &Hex(self.lr))
+            .field("pc", &Hex(self.pc))
+            .field("xpsr", &Hex(self.xpsr))
+            .finish()
+    }
+}
+
+/// Returns a pointer to the start of the heap
+///
+/// The returned pointer is guaranteed to be 4-byte aligned.
+#[inline]
+pub fn heap_start() -> *mut u32 {
+    extern "C" {
+        static mut __sheap: u32;
+    }
+
+    unsafe { &mut __sheap }
+}
+
+/* Entry point */
+#[doc(hidden)]
+#[link_section = ".vector_table.reset_vector"]
+#[no_mangle]
+pub static __RESET_VECTOR: unsafe extern "C" fn() -> ! = Reset;
+
+#[doc(hidden)]
+#[no_mangle]
+pub unsafe extern "C" fn Reset() -> ! {
+    extern "C" {
+        // This symbol will be provided by the user via the `entry!` macro
+        fn main() -> !;
+
+        // These symbols come from `link.x`
+        static mut __sbss: u32;
+        static mut __ebss: u32;
+
+        static mut __sdata: u32;
+        static mut __edata: u32;
+        static __sidata: u32;
+
+        fn __pre_init();
+    }
+
+    let pre_init: unsafe extern "C" fn() = __pre_init;
+    pre_init();
+
+    // Initialize RAM
+    r0::zero_bss(&mut __sbss, &mut __ebss);
+    r0::init_data(&mut __sdata, &mut __edata, &__sidata);
+
+    match () {
+        #[cfg(not(has_fpu))]
+        () => main(),
+        #[cfg(has_fpu)]
+        () => {
+            // We redefine these here to avoid pulling the `cortex-m` crate as a dependency
+            const SCB_CPACR: *mut u32 = 0xE000_ED88 as *mut u32;
+            const SCB_CPACR_FPU_ENABLE: u32 = 0b01_01 << 20;
+            const SCB_CPACR_FPU_USER: u32 = 0b10_10 << 20;
+
+            // enable the FPU
+            core::ptr::write_volatile(
+                SCB_CPACR,
+                *SCB_CPACR | SCB_CPACR_FPU_ENABLE | SCB_CPACR_FPU_USER,
+            );
+
+            // this is used to prevent the compiler from inlining the user `main` into the reset
+            // handler. Inlining can cause the FPU instructions in the user `main` to be executed
+            // before enabling the FPU, and that would produce a hard to diagnose hard fault at
+            // runtime.
+            #[inline(never)]
+            #[export_name = "ResetTrampoline"]
+            fn trampoline() -> ! {
+                unsafe { main() }
+            }
+
+            trampoline()
+        }
+    }
+}
+
+#[allow(unused_variables)]
+#[doc(hidden)]
+#[no_mangle]
+pub unsafe extern "C" fn UserHardFault_(ef: &ExceptionFrame) -> ! {
+    loop {
+        // add some side effect to prevent this from turning into a UDF instruction
+        // see rust-lang/rust#28728 for details
+        atomic::compiler_fence(Ordering::SeqCst);
+    }
+}
+
+#[doc(hidden)]
+#[no_mangle]
+pub unsafe extern "C" fn DefaultHandler_() -> ! {
+    loop {
+        // add some side effect to prevent this from turning into a UDF instruction
+        // see rust-lang/rust#28728 for details
+        atomic::compiler_fence(Ordering::SeqCst);
+    }
+}
+
+#[doc(hidden)]
+#[no_mangle]
+pub unsafe extern "C" fn DefaultPreInit() {}
+
+/// Macro to define the entry point of the program
+///
+/// **NOTE** This macro must be invoked once and must be invoked from an accessible module, ideally
+/// from the root of the crate.
+///
+/// Usage: `entry!(path::to::entry::point)`
+///
+/// The specified function will be called by the reset handler *after* RAM has been initialized. In
+/// the case of the `thumbv7em-none-eabihf` target the FPU will also be enabled before the function
+/// is called.
+///
+/// The signature of the specified function must be `fn() -> !` (never ending function)
+#[macro_export]
+macro_rules! entry {
+    ($path:expr) => {
+        #[export_name = "main"]
+        pub extern "C" fn __impl_main() -> ! {
+            // validate the signature of the program entry point
+            let f: fn() -> ! = $path;
+
+            f()
+        }
+    };
+}
+
+/* Exceptions */
+#[doc(hidden)]
+pub enum Exception {
+    NonMaskableInt,
+
+    // Not overridable
+    // HardFault,
+    #[cfg(not(armv6m))]
+    MemoryManagement,
+
+    #[cfg(not(armv6m))]
+    BusFault,
+
+    #[cfg(not(armv6m))]
+    UsageFault,
+
+    #[cfg(armv8m)]
+    SecureFault,
+
+    SVCall,
+
+    #[cfg(not(armv6m))]
+    DebugMonitor,
+
+    PendSV,
+
+    SysTick,
+}
+
+extern "C" {
+    fn NonMaskableInt();
+
+    fn HardFault();
+
+    #[cfg(not(armv6m))]
+    fn MemoryManagement();
+
+    #[cfg(not(armv6m))]
+    fn BusFault();
+
+    #[cfg(not(armv6m))]
+    fn UsageFault();
+
+    #[cfg(armv8m)]
+    fn SecureFault();
+
+    fn SVCall();
+
+    #[cfg(not(armv6m))]
+    fn DebugMonitor();
+
+    fn PendSV();
+
+    fn SysTick();
+}
+
+#[doc(hidden)]
+pub union Vector {
+    handler: unsafe extern "C" fn(),
+    reserved: usize,
+}
+
+#[doc(hidden)]
+#[link_section = ".vector_table.exceptions"]
+#[no_mangle]
+pub static __EXCEPTIONS: [Vector; 14] = [
+    // Exception 2: Non Maskable Interrupt.
+    Vector {
+        handler: NonMaskableInt,
+    },
+    // Exception 3: Hard Fault Interrupt.
+    Vector { handler: HardFault },
+    // Exception 4: Memory Management Interrupt [not on Cortex-M0 variants].
+    #[cfg(not(armv6m))]
+    Vector {
+        handler: MemoryManagement,
+    },
+    #[cfg(armv6m)]
+    Vector { reserved: 0 },
+    // Exception 5: Bus Fault Interrupt [not on Cortex-M0 variants].
+    #[cfg(not(armv6m))]
+    Vector { handler: BusFault },
+    #[cfg(armv6m)]
+    Vector { reserved: 0 },
+    // Exception 6: Usage Fault Interrupt [not on Cortex-M0 variants].
+    #[cfg(not(armv6m))]
+    Vector {
+        handler: UsageFault,
+    },
+    #[cfg(armv6m)]
+    Vector { reserved: 0 },
+    // Exception 7: Secure Fault Interrupt [only on Armv8-M].
+    #[cfg(armv8m)]
+    Vector {
+        handler: SecureFault,
+    },
+    #[cfg(not(armv8m))]
+    Vector { reserved: 0 },
+    // 8-10: Reserved
+    Vector { reserved: 0 },
+    Vector { reserved: 0 },
+    Vector { reserved: 0 },
+    // Exception 11: SV Call Interrupt.
+    Vector { handler: SVCall },
+    // Exception 12: Debug Monitor Interrupt [not on Cortex-M0 variants].
+    #[cfg(not(armv6m))]
+    Vector {
+        handler: DebugMonitor,
+    },
+    #[cfg(armv6m)]
+    Vector { reserved: 0 },
+    // 13: Reserved
+    Vector { reserved: 0 },
+    // Exception 14: Pend SV Interrupt [not on Cortex-M0 variants].
+    Vector { handler: PendSV },
+    // Exception 15: System Tick Interrupt.
+    Vector { handler: SysTick },
+];
+
+// If we are not targeting a specific device we bind all the potential device specific interrupts
+// to the default handler
+#[cfg(all(not(feature = "device"), not(armv6m)))]
+#[doc(hidden)]
+#[link_section = ".vector_table.interrupts"]
+#[no_mangle]
+pub static __INTERRUPTS: [unsafe extern "C" fn(); 240] = [{
+    extern "C" {
+        fn DefaultHandler();
+    }
+
+    DefaultHandler
+}; 240];
+
+// ARMv6-M can only have a maximum of 32 device specific interrupts
+#[cfg(all(not(feature = "device"), armv6m))]
+#[doc(hidden)]
+#[link_section = ".vector_table.interrupts"]
+#[no_mangle]
+pub static __INTERRUPTS: [unsafe extern "C" fn(); 32] = [{
+    extern "C" {
+        fn DefaultHandler();
+    }
+
+    DefaultHandler
+}; 32];
+
+/// Macro to set or override a processor core exception handler
+///
+/// **NOTE** This macro must be invoked from an accessible module, ideally from the root of the
+/// crate.
+///
+/// # Syntax
+///
+/// ``` ignore
+/// exception!(
+///     // Name of the exception
+///     $Name:ident,
+///
+///     // Path to the exception handler (a function)
+///     $handler:expr,
+///
+///     // Optional, state preserved across invocations of the handler
+///     state: $State:ty = $initial_state:expr,
+/// );
+/// ```
+///
+/// where `$Name` can be one of:
+///
+/// - `*`
+/// - `NonMaskableInt`
+/// - `HardFault`
+/// - `MemoryManagement` (a)
+/// - `BusFault` (a)
+/// - `UsageFault` (a)
+/// - `SecureFault` (b)
+/// - `SVCall`
+/// - `DebugMonitor` (a)
+/// - `PendSV`
+/// - `SysTick`
+///
+/// (a) Not available on Cortex-M0 variants (`thumbv6m-none-eabi`)
+///
+/// (b) Only available on ARMv8-M
+///
+/// # Usage
+///
+/// `exception!(HardFault, ..)` sets the hard fault handler. The handler must have signature
+/// `fn(&ExceptionFrame) -> !`. This handler is not allowed to return as that can cause undefined
+/// behavior. It's mandatory to set the `HardFault` handler somewhere in the dependency graph of an
+/// application.
+///
+/// `exception!(*, ..)` sets the *default* handler. All exceptions which have not been assigned a
+/// handler will be serviced by this handler. This handler must have signature `fn(irqn: i16)`.
+/// `irqn` is the IRQ number (cf. CMSIS); `irqn` will be a negative number when the handler is
+/// servicing a core exception; `irqn` will be a positive number when the handler is servicing a
+/// device specific exception (interrupt). It's mandatory to set the default handler somewhere
+/// in the dependency graph of an application.
+///
+/// `exception!($Exception, ..)` overrides the default handler for `$Exception`. All exceptions,
+/// except for `HardFault`, can be assigned some `$State`.
+///
+/// # Examples
+///
+/// - Setting the `HardFault` handler
+///
+/// ```
+/// #[macro_use(exception)]
+/// extern crate cortex_m_rt as rt;
+///
+/// use rt::ExceptionFrame;
+///
+/// exception!(HardFault, hard_fault);
+///
+/// fn hard_fault(ef: &ExceptionFrame) -> ! {
+///     // prints the exception frame as a panic message
+///     panic!("{:#?}", ef);
+/// }
+///
+/// # fn main() {}
+/// ```
+///
+/// - Setting the default handler
+///
+/// ```
+/// #[macro_use(exception)]
+/// extern crate cortex_m_rt as rt;
+///
+/// exception!(*, default_handler);
+///
+/// fn default_handler(irqn: i16) {
+///     println!("IRQn = {}", irqn);
+/// }
+///
+/// # fn main() {}
+/// ```
+///
+/// - Overriding the `SysTick` handler
+///
+/// ```
+/// #[macro_use(exception)]
+/// extern crate cortex_m_rt as rt;
+///
+/// exception!(SysTick, sys_tick, state: u32 = 0);
+///
+/// fn sys_tick(count: &mut u32) {
+///     println!("count = {}", *count);
+///
+///     *count += 1;
+/// }
+///
+/// # fn main() {}
+/// ```
+#[macro_export]
+macro_rules! exception {
+    (* , $handler:expr) => {
+        #[allow(unsafe_code)]
+        #[deny(private_no_mangle_fns)] // raise an error if this item is not accessible
+        #[no_mangle]
+        pub unsafe extern "C" fn DefaultHandler() {
+            extern crate core;
+
+            // validate the signature of the user provided handler
+            let f: fn(i16) = $handler;
+
+            const SCB_ICSR: *const u32 = 0xE000_ED04 as *const u32;
+
+            // NOTE not volatile so the compiler can opt the load operation away if the value is
+            // unused
+            f(core::ptr::read(SCB_ICSR) as u8 as i16 - 16)
+        }
+    };
+
+    (HardFault, $handler:expr) => {
+        #[allow(unsafe_code)]
+        #[deny(private_no_mangle_fns)] // raise an error if this item is not accessible
+        #[no_mangle]
+        pub unsafe extern "C" fn UserHardFault(ef: &$crate::ExceptionFrame) {
+            // validate the signature of the user provided handler
+            let f: fn(&$crate::ExceptionFrame) -> ! = $handler;
+
+            f(ef)
+        }
+    };
+
+    ($Name:ident, $handler:expr,state: $State:ty = $initial_state:expr) => {
+        #[allow(unsafe_code)]
+        #[deny(private_no_mangle_fns)] // raise an error if this item is not accessible
+        #[no_mangle]
+        pub unsafe extern "C" fn $Name() {
+            static mut STATE: $State = $initial_state;
+
+            // check that this exception exists
+            let _ = $crate::Exception::$Name;
+
+            // validate the signature of the user provided handler
+            let f: fn(&mut $State) = $handler;
+
+            f(&mut STATE)
+        }
+    };
+
+    ($Name:ident, $handler:expr) => {
+        #[allow(unsafe_code)]
+        #[deny(private_no_mangle_fns)] // raise an error if this item is not accessible
+        #[no_mangle]
+        pub unsafe extern "C" fn $Name() {
+            // check that this exception exists
+            let _ = $crate::Exception::$Name;
+
+            // validate the signature of the user provided handler
+            let f: fn() = $handler;
+
+            f()
+        }
+    };
+}
+
+/// Macro to set the function to be called at the beginning of the reset handler.
+///
+/// The function must have the signature of `unsafe fn()`.
+///
+/// The function passed will be called before static variables are initialized. Any access of static
+/// variables will result in undefined behavior.
+///
+/// # Examples
+///
+/// ``` ignore
+/// pre_init!(foo::bar);
+///
+/// mod foo {
+///     pub unsafe fn bar() {
+///         // do something here
+///     }
+/// }
+/// ```
+#[macro_export]
+macro_rules! pre_init {
+    ($handler:path) => {
+        #[allow(unsafe_code)]
+        #[deny(private_no_mangle_fns)] // raise an error if this item is not accessible
+        #[no_mangle]
+        pub unsafe extern "C" fn __pre_init() {
+            // validate user handler
+            let f: unsafe fn() = $handler;
+            f();
+        }
+    };
+}
+
      +
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+
      +//! Interacting with debugging agent
+//!
+//! # Example
+//!
+//! This example will show how to terminate the QEMU session. The program
+//! should be running under QEMU with semihosting enabled
+//! (use `-semihosting` flag).
+//!
+//! Target program:
+//!
+//! ```
+//! #[macro_use]
+//! extern crate cortex_m_semihosting;
+//! use cortex_m_semihosting::debug::{self, EXIT_SUCCESS, EXIT_FAILURE};
+//!
+//! fn main() {
+//!     if 2 == 2 {
+//!         // report success
+//!         debug::exit(EXIT_SUCCESS);
+//!     } else {
+//!         // report failure
+//!         debug::exit(EXIT_FAILURE);
+//!     }
+//! }
+//!
+
+/// This values are taken from section 5.5.2 of
+/// ADS Debug Target Guide (DUI0058).
+// TODO document
+#[allow(missing_docs)]
+pub enum Exception {
+    // Hardware reason codes
+    BranchThroughZero = 0x20000,
+    UndefinedInstr = 0x20001,
+    SoftwareInterrupt = 0x20002,
+    PrefetchAbort = 0x20003,
+    DataAbort = 0x20004,
+    AddressException = 0x20005,
+    IRQ = 0x20006,
+    FIQ = 0x20007,
+    // Software reason codes
+    BreakPoint = 0x20020,
+    WatchPoint = 0x20021,
+    StepComplete = 0x20022,
+    RunTimeErrorUnknown = 0x20023,
+    InternalError = 0x20024,
+    UserInterruption = 0x20025,
+    ApplicationExit = 0x20026,
+    StackOverflow = 0x20027,
+    DivisionByZero = 0x20028,
+    OSSpecific = 0x20029,
+}
+
+/// Status enum for `exit` syscall.
+pub type ExitStatus = Result<(), ()>;
+
+/// Successful execution of a program.
+pub const EXIT_SUCCESS: ExitStatus = Ok(());
+
+/// Unsuccessful execution of a program.
+pub const EXIT_FAILURE: ExitStatus = Err(());
+
+/// Reports to the debugger that the execution has completed.
+///
+/// This call can be used to terminate QEMU session and report back success
+/// or failure. If you need to pass more than one type of error, consider
+/// using `report_exception` syscall instead.
+///
+/// This call should not return. However, it is possible for the debugger
+/// to request that the application continue. In that case this call
+/// returns normally.
+///
+pub fn exit(status: ExitStatus) {
+    match status {
+        EXIT_SUCCESS => report_exception(Exception::ApplicationExit),
+        EXIT_FAILURE => report_exception(Exception::RunTimeErrorUnknown),
+    }
+}
+
+/// Report an exception to the debugger directly.
+///
+/// Exception handlers can use this SWI at the end of handler chains
+/// as the default action, to indicate that the exception has not been handled.
+///
+/// This call should not return. However, it is possible for the debugger
+/// to request that the application continue. In that case this call
+/// returns normally.
+///
+/// # Arguments
+///
+/// * `reason` - A reason code reported back to the debugger.
+///
+pub fn report_exception(reason: Exception) {
+    let code = reason as usize;
+    unsafe {
+        syscall1!(REPORT_EXCEPTION, code);
+    }
+}
+
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+
      +//! Host I/O
+
+use core::{fmt, slice};
+use nr;
+
+/// Host's standard error
+pub struct HStderr {
+    fd: usize,
+}
+
+impl HStderr {
+    /// Attempts to write an entire `buffer` into this sink
+    pub fn write_all(&mut self, buffer: &[u8]) -> Result<(), ()> {
+        write_all(self.fd, buffer)
+    }
+}
+
+impl fmt::Write for HStderr {
+    fn write_str(&mut self, s: &str) -> fmt::Result {
+        self.write_all(s.as_bytes()).map_err(|_| fmt::Error)
+    }
+}
+
+/// Host's standard output
+pub struct HStdout {
+    fd: usize,
+}
+
+impl HStdout {
+    /// Attempts to write an entire `buffer` into this sink
+    pub fn write_all(&mut self, buffer: &[u8]) -> Result<(), ()> {
+        write_all(self.fd, buffer)
+    }
+}
+
+impl fmt::Write for HStdout {
+    fn write_str(&mut self, s: &str) -> fmt::Result {
+        self.write_all(s.as_bytes()).map_err(|_| fmt::Error)
+    }
+}
+
+/// Construct a new handle to the host's standard error.
+pub fn hstderr() -> Result<HStderr, ()> {
+    // There is actually no stderr access in ARM Semihosting documentation. Use
+    // convention used in libgloss.
+    // See: libgloss/arm/syscalls.c, line 139.
+    // https://sourceware.org/git/gitweb.cgi?p=newlib-cygwin.git;a=blob;f=libgloss/arm/syscalls.c#l139
+    open(":tt\0", nr::open::W_APPEND).map(|fd| HStderr { fd })
+}
+
+/// Construct a new handle to the host's standard output.
+pub fn hstdout() -> Result<HStdout, ()> {
+    open(":tt\0", nr::open::W_TRUNC).map(|fd| HStdout { fd })
+}
+
+fn open(name: &str, mode: usize) -> Result<usize, ()> {
+    let name = name.as_bytes();
+    match unsafe { syscall!(OPEN, name.as_ptr(), mode, name.len() - 1) } as
+        isize {
+        -1 => Err(()),
+        fd => Ok(fd as usize),
+    }
+}
+
+fn write_all(fd: usize, mut buffer: &[u8]) -> Result<(), ()> {
+    while !buffer.is_empty() {
+        match unsafe { syscall!(WRITE, fd, buffer.as_ptr(), buffer.len()) } {
+            // Done
+            0 => return Ok(()),
+            // `n` bytes were not written
+            n if n <= buffer.len() => {
+                let offset = (buffer.len() - n) as isize;
+                buffer = unsafe {
+                    slice::from_raw_parts(buffer.as_ptr().offset(offset), n)
+                }
+            }
+            // Error
+            _ => return Err(()),
+        }
+    }
+    Ok(())
+}
+
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+
      +//! Semihosting for ARM Cortex-M processors
+//!
+//! # What is semihosting?
+//!
+//! "Semihosting is a mechanism that enables code running on an ARM target to communicate and use
+//! the Input/Output facilities on a host computer that is running a debugger." - ARM
+//!
+//! # Interface
+//!
+//! This crate provides implementations of
+//! [`core::fmt::Write`](https://doc.rust-lang.org/core/fmt/trait.Write.html), so you can use it,
+//! in conjunction with
+//! [`core::format_args!`](https://doc.rust-lang.org/core/macro.format_args.html) or the [`write!` macro](https://doc.rust-lang.org/core/macro.write.html), for user-friendly construction and printing of formatted strings.
+//!
+//! Since semihosting operations are modeled as [system calls][sc], this crate exposes an untyped
+//! `syscall!` interface just like the [`sc`] crate does.
+//!
+//! [sc]: https://en.wikipedia.org/wiki/System_call
+//! [`sc`]: https://crates.io/crates/sc
+//!
+//! # Forewarning
+//!
+//! Semihosting operations are *very* slow. Like, each WRITE operation can take hundreds of
+//! milliseconds.
+//!
+//! # Example
+//!
+//! ## Using `hio::HStdout`
+//!
+//! This example will demonstrate how to print formatted strings.
+//!
+//! ```rust
+//! extern crate cortex_m_semihosting;
+//!
+//! use cortex_m_semihosting::hio;
+//! use core::fmt::Write;
+//!
+//! // This function will be called by the application
+//! fn print() -> Result<(), core::fmt::Error> {
+//!     let mut stdout = match hio::hstdout() {
+//!         Ok(fd) => fd,
+//!         Err(()) => return Err(core::fmt::Error),
+//!     };
+//!
+//!     let language = "Rust";
+//!     let ranking = 1;
+//!
+//!     write!(stdout, "{} on embedded is #{}!", language, ranking)?;
+//!
+//!     Ok(())
+//! }
+//! ```
+//!
+//! On the host side:
+//!
+//! ``` text
+//! $ openocd -f $INTERFACE -f $TARGET -l /tmp/openocd.log
+//! Open On-Chip Debugger 0.9.0 (2016-04-27-23:18)
+//! Licensed under GNU GPL v2
+//! For bug reports, read
+//!         http://openocd.org/doc/doxygen/bugs.html
+//! # the command will block at this point
+//! ```
+//!
+//! The OpenOCD logs will be redirected to `/tmp/openocd.log`. You can view those logs in "real
+//! time" using `tail`
+//!
+//! ``` text
+//! $ tail -f /tmp/openocd.log
+//! Info : Unable to match requested speed 1000 kHz, using 950 kHz
+//! Info : Unable to match requested speed 1000 kHz, using 950 kHz
+//! Info : clock speed 950 kHz
+//! Info : STLINK v1 JTAG v11 API v2 SWIM v0 VID 0x0483 PID 0x3744
+//! Info : using stlink api v2
+//! Info : nrf51.cpu: hardware has 4 breakpoints, 2 watchpoints
+//! ```
+//!
+//! Alternatively you could omit the `-l` flag from the `openocd` call, and the `tail -f` command
+//! but the OpenOCD output will have intermingled in it logs from its normal operation.
+//!
+//! Then, we run the program:
+//!
+//! ``` text
+//! $ arm-none-eabi-gdb hello-world
+//! (gdb) # Connect to OpenOCD
+//! (gdb) target remote :3333
+//!
+//! (gdb) # Enable OpenOCD's semihosting support
+//! (gdb) monitor arm semihosting enable
+//!
+//! (gdb) # Flash the program
+//! (gdb) load
+//!
+//! (gdb) # Run the program
+//! (gdb) continue
+//! ```
+//!
+//! And you'll see the output under OpenOCD's terminal
+//!
+//! ``` text
+//! # openocd -f $INTERFACE -f $TARGET -l /tmp/openocd.log
+//! (..)
+//! Rust on embedded is #1!
+//! ```
+//! ## Using the syscall interface
+//!
+//! This example will show how to print "Hello, world!" on the host.
+//!
+//! Target program:
+//!
+//! ```
+//! extern crate cortex_m_semihosting;
+//!
+//! // This function will be called by the application
+//! fn print() {
+//!     // File descriptor (on the host)
+//!     const STDOUT: usize = 1; // NOTE the host stdout may not always be fd 1
+//!     static MSG: &'static [u8] = b"Hello, world!\n";
+//!
+//!     // Signature: fn write(fd: usize, ptr: *const u8, len: usize) -> usize
+//!     let r = unsafe { syscall!(WRITE, STDOUT, MSG.as_ptr(), MSG.len()) };
+//! }
+//! ```
+//! Output and monitoring proceed as in the above example.
+//!
+//! # Optional features
+//!
+//! ## `inline-asm`
+//!
+//! When this feature is enabled semihosting is implemented using inline assembly (`asm!`) and
+//! compiling this crate requires nightly.
+//!
+//! When this feature is disabled semihosting is implemented using FFI calls into an external
+//! assembly file and compiling this crate works on stable and beta.
+//!
+//! # Reference
+//!
+//! For documentation about the semihosting operations, check:
+//!
+//! 'Chapter 8 - Semihosting' of the ['ARM Compiler toolchain Version 5.0'][pdf]
+//! manual.
+//!
+//! [pdf]: http://infocenter.arm.com/help/topic/com.arm.doc.dui0471e/DUI0471E_developing_for_arm_processors.pdf
+
+#![cfg_attr(feature = "inline-asm", feature(asm))]
+#![deny(missing_docs)]
+#![deny(warnings)]
+#![no_std]
+
+#[macro_use]
+mod macros;
+
+pub mod debug;
+pub mod hio;
+pub mod nr;
+
+#[cfg(all(thumb, not(feature = "inline-asm")))]
+extern "C" {
+    fn __syscall(nr: usize, arg: usize) -> usize;
+}
+
+/// Performs a semihosting operation, takes a pointer to an argument block
+#[inline(always)]
+pub unsafe fn syscall<T>(nr: usize, arg: &T) -> usize {
+    syscall1(nr, arg as *const T as usize)
+}
+
+/// Performs a semihosting operation, takes one integer as an argument
+#[inline(always)]
+pub unsafe fn syscall1(_nr: usize, _arg: usize) -> usize {
+    match () {
+        #[cfg(all(thumb, not(feature = "inline-asm")))]
+        () => __syscall(_nr, _arg),
+
+        #[cfg(all(thumb, feature = "inline-asm"))]
+        () => {
+            let mut nr = _nr;
+            asm!("bkpt 0xAB" : "+{r0}"(nr) : "{r1}"(_arg) :: "volatile");
+            nr
+        }
+
+        #[cfg(not(thumb))]
+        () => unimplemented!(),
+    }
+}
+
      +
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      +/// Variable argument version of `syscall`
+#[macro_export]
+macro_rules! syscall {
+    ($nr:ident) => {
+        $crate::syscall1($crate::nr::$nr, 0)
+    };
+    ($nr:ident, $a1:expr) => {
+        $crate::syscall($crate::nr::$nr, &[$a1 as usize])
+    };
+    ($nr:ident, $a1:expr, $a2:expr) => {
+        $crate::syscall($crate::nr::$nr, &[$a1 as usize, $a2 as usize])
+    };
+    ($nr:ident, $a1:expr, $a2:expr, $a3:expr) => {
+        $crate::syscall($crate::nr::$nr, &[$a1 as usize, $a2 as usize,
+                                           $a3 as usize])
+    };
+    ($nr:ident, $a1:expr, $a2:expr, $a3:expr, $a4:expr) => {
+        $crate::syscall($crate::nr::$nr, &[$a1 as usize, $a2 as usize,
+                                           $a3 as usize, $a4 as usize])
+    };
+}
+
+/// Macro version of `syscall1`
+#[macro_export]
+macro_rules! syscall1 {
+    ($nr:ident, $a1:expr) => {
+        $crate::syscall1($crate::nr::$nr, $a1 as usize)
+    };
+}
+
      +
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+
      +//! Semihosting operations
+
+// TODO document
+#![allow(missing_docs)]
+
+pub const CLOCK: usize = 0x10;
+pub const CLOSE: usize = 0x02;
+pub const ELAPSED: usize = 0x30;
+pub const ERRNO: usize = 0x13;
+pub const FLEN: usize = 0x0c;
+pub const GET_CMDLINE: usize = 0x15;
+pub const HEAPINFO: usize = 0x16;
+pub const ISERROR: usize = 0x08;
+pub const ISTTY: usize = 0x09;
+pub const OPEN: usize = 0x01;
+pub const READ: usize = 0x06;
+pub const READC: usize = 0x07;
+pub const REMOVE: usize = 0x0e;
+pub const RENAME: usize = 0x0f;
+pub const SEEK: usize = 0x0a;
+pub const SYSTEM: usize = 0x12;
+pub const TICKFREQ: usize = 0x31;
+pub const TIME: usize = 0x11;
+pub const TMPNAM: usize = 0x0d;
+pub const WRITE0: usize = 0x04;
+pub const WRITE: usize = 0x05;
+pub const WRITEC: usize = 0x03;
+pub const ENTER_SVC: usize = 0x17;
+pub const REPORT_EXCEPTION: usize = 0x18;
+
+/// Values for the mode parameter of the OPEN syscall.
+pub mod open {
+    /// Mode corresponding to fopen "r" mode.
+    pub const R: usize = 0;
+    /// Mode corresponding to fopen "rb" mode.
+    pub const R_BINARY: usize = 1;
+    /// Mode corresponding to fopen "r+" mode.
+    pub const RW: usize = 2;
+    /// Mode corresponding to fopen "r+b" mode.
+    pub const RW_BINARY: usize = 3;
+    /// Mode corresponding to fopen "w" mode.
+    pub const W_TRUNC: usize = 4;
+    /// Mode corresponding to fopen "wb" mode.
+    pub const W_TRUNC_BINARY: usize = 5;
+    /// Mode corresponding to fopen "w+" mode.
+    pub const RW_TRUNC: usize = 6;
+    /// Mode corresponding to fopen "w+b" mode.
+    pub const RW_TRUNC_BINARY: usize = 7;
+    /// Mode corresponding to fopen "a" mode.
+    pub const W_APPEND: usize = 8;
+    /// Mode corresponding to fopen "ab" mode.
+    pub const W_APPEND_BINARY: usize = 9;
+    /// Mode corresponding to fopen "a+" mode.
+    pub const RW_APPEND: usize = 10;
+    /// Mode corresponding to fopen "a+b" mode.
+    pub const RW_APPEND_BINARY: usize = 11;
+}
+
      +
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      +//! Report panic messages to the host stderr using semihosting
+//!
+//! This crate contains an implementation of `panic_fmt` that logs panic messages to the host stderr
+//! using [`cortex-m-semihosting`]. Before logging the message the panic handler disables (masks)
+//! the device specific interrupts. After logging the message the panic handler trigger a breakpoint
+//! and then goes into an infinite loop.
+//!
+//! Currently, this crate only supports the ARM Cortex-M architecture.
+//!
+//! [`cortex-m-semihosting`]: https://crates.io/crates/cortex-m-semihosting
+//!
+//! # Usage
+//!
+//! ``` ignore
+//! #![no_std]
+//!
+//! extern crate panic_semihosting;
+//!
+//! fn main() {
+//!     panic!("FOO")
+//! }
+//! ```
+//!
+//! ``` text
+//! (gdb) monitor arm semihosting enable
+//! (gdb) continue
+//! Program received signal SIGTRAP, Trace/breakpoint trap.
+//! rust_begin_unwind (args=..., file=..., line=8, col=5)
+//!     at $CRATE/src/lib.rs:69
+//! 69          asm::bkpt();
+//! ```
+//!
+//! ``` text
+//! $ openocd -f (..)
+//! (..)
+//! panicked at 'FOO', src/main.rs:6:5
+//! ```
+//!
+//! # Optional features
+//!
+//! ## `inline-asm`
+//!
+//! When this feature is enabled semihosting is implemented using inline assembly (`asm!`) and
+//! compiling this crate requires nightly.
+//!
+//! When this feature is disabled semihosting is implemented using FFI calls into an external
+//! assembly file and compiling this crate works on stable and beta.
+
+#![deny(missing_docs)]
+#![deny(warnings)]
+#![feature(panic_handler)]
+#![no_std]
+
+extern crate cortex_m;
+extern crate cortex_m_semihosting as sh;
+
+use core::fmt::Write;
+use core::panic::PanicInfo;
+
+use cortex_m::{asm, interrupt};
+use sh::hio;
+
+#[panic_handler]
+fn panic(info: &PanicInfo) -> ! {
+    interrupt::disable();
+
+    if let Ok(mut hstdout) = hio::hstdout() {
+        writeln!(hstdout, "{}", info).ok();
+    }
+
+    // OK to fire a breakpoint here because we know the microcontroller is connected to a debugger
+    asm::bkpt();
+
+    loop {}
+}
+
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+
      +//! Initialization code ("crt0") written in Rust
+//!
+//! This is for bare metal systems where there is no ELF loader or OS to take
+//! care of initializing RAM for the program.
+//!
+//! # Initializing RAM
+//!
+//! On the linker script side, we must assign names (symbols) to the boundaries
+//! of the `.bss` and `.data` sections.
+//!
+//! ``` text
+//! .bss : ALIGN(4)
+//! {
+//!     _sbss = .;
+//!     *(.bss.*);
+//!     _ebss = ALIGN(4);
+//! } > RAM
+//!
+//! .data : ALIGN(4)
+//! {
+//!     _sdata = .;
+//!     *(.data.*);
+//!     _edata = ALIGN(4);
+//! } > RAM AT > FLASH
+//!
+//! _sidata = LOADADDR(.data);
+//! ```
+//!
+//! On the Rust side, we must bind to those symbols using an `extern` block.
+//!
+//! ```
+//! unsafe fn before_main() {
+//!     // The type, `u32`, indicates that the memory is 4-byte aligned
+//!     extern "C" {
+//!         static mut _sbss: u32;
+//!         static mut _ebss: u32;
+//!
+//!         static mut _sdata: u32;
+//!         static mut _edata: u32;
+//!
+//!         static _sidata: u32;
+//!     }
+//!
+//!     zero_bss(&mut _sbss, &mut _ebss);
+//!     init_data(&mut _sdata, &mut _edata, &_sidata);
+//! }
+//! ```
+//!
+//! # `.init_array` & `.pre_init_array`
+//!
+//! This crate also provides an API to add "life before main" functionality to
+//! bare metal systems.
+//!
+//! On the linker script side, instruct the linker to keep the `.init_array`
+//! sections from input object files. Store the start and end address of the
+//! merged `.init_array` section.
+//!
+//! ``` text
+//! .text :
+//! {
+//!   /* .. */
+//!   _init_array_start = ALIGN(4);
+//!   KEEP(*(.init_array));
+//!   _init_array_end = ALIGN(4);
+//!   /* .. */
+//! }
+//! ```
+//!
+//! On the startup code, invoke the `run_init_array` function *before* you call
+//! the user `main`.
+//!
+//! ```
+//! unsafe fn start() {
+//!     extern "C" {
+//!         static _init_array_start: extern "C" fn();
+//!         static _init_array_end: extern "C" fn();
+//!     }
+//!
+//!     ::r0::run_init_array(&_init_array_start, &_init_array_end);
+//!
+//!     extern "C" {
+//!         fn main(argc: isize, argv: *const *const u8) -> isize;
+//!     }
+//!
+//!     main();
+//! }
+//! ```
+//!
+//! Then the user application can use this crate `init_array!` macro to run code
+//! before `main`.
+//!
+//! ```
+//! init_array!(before_main, {
+//!     println!("Hello");
+//! });
+//!
+//! fn main() {
+//!     println!("World");
+//! }
+//! ```
+
+#![deny(warnings)]
+#![no_std]
+
+use core::{mem, ptr, slice};
+
+/// Initializes the `.data` section
+///
+/// # Arguments
+///
+/// - `sdata`. Pointer to the start of the `.data` section.
+/// - `edata`. Pointer to the open/non-inclusive end of the `.data` section.
+///   (The value behind this pointer will not be modified)
+/// - `sidata`. `.data` section Load Memory Address (LMA)
+/// - Use `T` to indicate the alignment of the `.data` section and its LMA.
+///
+/// # Safety
+///
+/// - Must be called exactly once
+/// - `mem::size_of::<T>()` must be non-zero
+/// - `edata >= sdata`
+/// - The `sdata -> edata` region must not overlap with the `sidata -> ...`
+///   region
+/// - `sdata`, `edata` and `sidata` must be `T` aligned.
+pub unsafe fn init_data<T>(
+    mut sdata: *mut T,
+    edata: *mut T,
+    mut sidata: *const T,
+) where
+    T: Copy,
+{
+    while sdata < edata {
+        ptr::write(sdata, ptr::read(sidata));
+        sdata = sdata.offset(1);
+        sidata = sidata.offset(1);
+    }
+}
+
+pub unsafe fn run_init_array(
+    init_array_start: &extern "C" fn(),
+    init_array_end: &extern "C" fn(),
+) {
+    let n = (init_array_end as *const _ as usize -
+                 init_array_start as *const _ as usize) /
+        mem::size_of::<extern "C" fn()>();
+
+    for f in slice::from_raw_parts(init_array_start, n) {
+        f();
+    }
+}
+
+/// Zeroes the `.bss` section
+///
+/// # Arguments
+///
+/// - `sbss`. Pointer to the start of the `.bss` section.
+/// - `ebss`. Pointer to the open/non-inclusive end of the `.bss` section.
+///   (The value behind this pointer will not be modified)
+/// - Use `T` to indicate the alignment of the `.bss` section.
+///
+/// # Safety
+///
+/// - Must be called exactly once
+/// - `mem::size_of::<T>()` must be non-zero
+/// - `ebss >= sbss`
+/// - `sbss` and `ebss` must be `T` aligned.
+pub unsafe fn zero_bss<T>(mut sbss: *mut T, ebss: *mut T)
+where
+    T: Copy,
+{
+    while sbss < ebss {
+        // NOTE(volatile) to prevent this from being transformed into `memclr`
+        ptr::write_volatile(sbss, mem::zeroed());
+        sbss = sbss.offset(1);
+    }
+}
+
+#[macro_export]
+macro_rules! pre_init_array {
+    ($name:ident, $body:expr) => {
+        #[allow(dead_code)]
+        unsafe extern "C" fn $name() {
+            #[link_section = ".pre_init_array"]
+            #[used]
+            static PRE_INIT_ARRAY_ELEMENT: unsafe extern "C" fn() = $name;
+
+            #[inline(always)]
+            fn inner() {
+                $body
+            }
+
+            inner()
+        }
+    }
+}
+
+#[macro_export]
+macro_rules! init_array {
+    ($name:ident, $body:expr) => {
+        #[allow(dead_code)]
+        unsafe extern "C" fn $name() {
+            #[link_section = ".init_array"]
+            #[used]
+            static INIT_ARRAY_ELEMENT: unsafe extern "C" fn() = $name;
+
+            #[inline(always)]
+            fn inner() {
+                $body
+            }
+
+            inner()
+        }
+    }
+}
+
      +
      \ No newline at end of file diff --git a/src/vcell/lib.rs.html b/src/vcell/lib.rs.html new file mode 100644 index 0000000..8f808a0 --- /dev/null +++ b/src/vcell/lib.rs.html @@ -0,0 +1,115 @@ +lib.rs.html -- source
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+
      +//! Just like [`Cell`] but with [volatile] read / write operations
+//!
+//! [`Cell`]: https://doc.rust-lang.org/std/cell/struct.Cell.html
+//! [volatile]: https://doc.rust-lang.org/std/ptr/fn.read_volatile.html
+
+#![deny(missing_docs)]
+#![deny(warnings)]
+#![cfg_attr(feature = "const-fn", feature(const_fn))]
+#![no_std]
+
+use core::cell::UnsafeCell;
+use core::ptr;
+
+/// Just like [`Cell`] but with [volatile] read / write operations
+///
+/// [`Cell`]: https://doc.rust-lang.org/std/cell/struct.Cell.html
+/// [volatile]: https://doc.rust-lang.org/std/ptr/fn.read_volatile.html
+pub struct VolatileCell<T> {
+    value: UnsafeCell<T>,
+}
+
+impl<T> VolatileCell<T> {
+    /// Creates a new `VolatileCell` containing the given value
+    #[cfg(feature = "const-fn")]
+    pub const fn new(value: T) -> Self {
+        VolatileCell { value: UnsafeCell::new(value) }
+    }
+
+    /// Creates a new `VolatileCell` containing the given value
+    ///
+    /// NOTE A `const fn` variant is available under the "const-fn" Cargo
+    /// feature
+    #[cfg(not(feature = "const-fn"))]
+    pub fn new(value: T) -> Self {
+        VolatileCell { value: UnsafeCell::new(value) }
+    }
+
+    /// Returns a copy of the contained value
+    #[inline(always)]
+    pub fn get(&self) -> T
+        where T: Copy
+    {
+        unsafe { ptr::read_volatile(self.value.get()) }
+    }
+
+    /// Sets the contained value
+    #[inline(always)]
+    pub fn set(&self, value: T)
+        where T: Copy
+    {
+        unsafe { ptr::write_volatile(self.value.get(), value) }
+    }
+}
+
+// NOTE implicit because of `UnsafeCell`
+// unsafe impl<T> !Sync for VolatileCell<T> {}
+
      +
      \ No newline at end of file diff --git a/src/volatile_register/lib.rs.html b/src/volatile_register/lib.rs.html new file mode 100644 index 0000000..817cd8b --- /dev/null +++ b/src/volatile_register/lib.rs.html @@ -0,0 +1,211 @@ +lib.rs.html -- source
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+
      +//! Volatile access to memory mapped hardware registers
+//!
+//! # Usage
+//!
+//! ``` no_run
+//! use volatile_register::RW;
+//!
+//! // Create a struct that represents the memory mapped register block
+//! /// Nested Vector Interrupt Controller
+//! #[repr(C)]
+//! pub struct Nvic {
+//!     /// Interrupt Set-Enable
+//!     pub iser: [RW<u32>; 8],
+//!     reserved0: [u32; 24],
+//!     /// Interrupt Clear-Enable
+//!     pub icer: [RW<u32>; 8],
+//!     reserved1: [u32; 24],
+//!     // .. more registers ..
+//! }
+//!
+//! // Access the registers by casting the base address of the register block
+//! // to the previously declared `struct`
+//! let nvic = 0xE000_E100 as *const Nvic;
+//! // Unsafe because the compiler can't verify the address is correct
+//! unsafe { (*nvic).iser[0].write(1) }
+//! ```
+
+#![deny(missing_docs)]
+#![no_std]
+
+extern crate vcell;
+
+use vcell::VolatileCell;
+
+/// Read-Only register
+pub struct RO<T>
+    where T: Copy
+{
+    register: VolatileCell<T>,
+}
+
+impl<T> RO<T>
+    where T: Copy
+{
+    /// Reads the value of the register
+    #[inline(always)]
+    pub fn read(&self) -> T {
+        self.register.get()
+    }
+}
+
+/// Read-Write register
+pub struct RW<T>
+    where T: Copy
+{
+    register: VolatileCell<T>,
+}
+
+impl<T> RW<T>
+    where T: Copy
+{
+    /// Performs a read-modify-write operation
+    ///
+    /// NOTE: `unsafe` because writes to a register are side effectful
+    #[inline(always)]
+    pub unsafe fn modify<F>(&self, f: F)
+        where F: FnOnce(T) -> T
+    {
+        self.register.set(f(self.register.get()));
+    }
+
+    /// Reads the value of the register
+    #[inline(always)]
+    pub fn read(&self) -> T {
+        self.register.get()
+    }
+
+    /// Writes a `value` into the register
+    ///
+    /// NOTE: `unsafe` because writes to a register are side effectful
+    #[inline(always)]
+    pub unsafe fn write(&self, value: T) {
+        self.register.set(value)
+    }
+}
+
+/// Write-Only register
+pub struct WO<T>
+    where T: Copy
+{
+    register: VolatileCell<T>,
+}
+
+impl<T> WO<T>
+    where T: Copy
+{
+    /// Writes `value` into the register
+    ///
+    /// NOTE: `unsafe` because writes to a register are side effectful
+    #[inline(always)]
+    pub unsafe fn write(&self, value: T) {
+        self.register.set(value)
+    }
+}
+
      +
      \ No newline at end of file diff --git a/storage.js b/storage.js new file mode 100644 index 0000000..f01b7d3 --- /dev/null +++ b/storage.js @@ -0,0 +1,11 @@ +var resourcesSuffix="";/*! + * Copyright 2018 The Rust Project Developers. See the COPYRIGHT + * file at the top-level directory of this distribution and at + * http://rust-lang.org/COPYRIGHT. + * + * Licensed under the Apache License, Version 2.0 or the MIT license + * , at your + * option. This file may not be copied, modified, or distributed + * except according to those terms. + */var currentTheme=document.getElementById("themeStyle");var mainTheme=document.getElementById("mainThemeStyle");var savedHref=[];function onEach(arr,func){if(arr&&arr.length>0&&func){for(var i=0;i + + + + + +

      Redirecting to struct.VolatileCell.html...

      + + + \ No newline at end of file diff --git a/vcell/all.html b/vcell/all.html new file mode 100644 index 0000000..167da2b --- /dev/null +++ b/vcell/all.html @@ -0,0 +1,3 @@ +List of all items in this crate

      [−] + + List of all items

      Structs

      \ No newline at end of file diff --git a/vcell/index.html b/vcell/index.html new file mode 100644 index 0000000..162f5c8 --- /dev/null +++ b/vcell/index.html @@ -0,0 +1,11 @@ +vcell - Rust

      [−][src]Crate vcell

      Just like Cell but with volatile read / write operations

      +

      Structs

      + + + + +
      VolatileCell +

      Just like Cell but with volatile read / write operations

      + +
      \ No newline at end of file diff --git a/vcell/sidebar-items.js b/vcell/sidebar-items.js new file mode 100644 index 0000000..8eb91d3 --- /dev/null +++ b/vcell/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"struct":[["VolatileCell","Just like [`Cell`] but with [volatile] read / write operations"]]}); \ No newline at end of file diff --git a/vcell/struct.VolatileCell.html b/vcell/struct.VolatileCell.html new file mode 100644 index 0000000..9ebb9ce --- /dev/null +++ b/vcell/struct.VolatileCell.html @@ -0,0 +1,19 @@ +vcell::VolatileCell - Rust

      [−][src]Struct vcell::VolatileCell

      pub struct VolatileCell<T> { /* fields omitted */ }

      Just like Cell but with volatile read / write operations

      +

      Methods

      impl<T> VolatileCell<T>
      [src]

      Creates a new VolatileCell containing the given value

      +

      NOTE A const fn variant is available under the "const-fn" Cargo +feature

      +

      Returns a copy of the contained value

      +

      Sets the contained value

      +

      Auto Trait Implementations

      impl<T> Send for VolatileCell<T> where
          T: Send, 

      impl<T> !Sync for VolatileCell<T>

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/volatile_register/RO.t.html b/volatile_register/RO.t.html new file mode 100644 index 0000000..34bb72e --- /dev/null +++ b/volatile_register/RO.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.RO.html...

      + + + \ No newline at end of file diff --git a/volatile_register/RW.t.html b/volatile_register/RW.t.html new file mode 100644 index 0000000..8d9dfa2 --- /dev/null +++ b/volatile_register/RW.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.RW.html...

      + + + \ No newline at end of file diff --git a/volatile_register/WO.t.html b/volatile_register/WO.t.html new file mode 100644 index 0000000..8932da0 --- /dev/null +++ b/volatile_register/WO.t.html @@ -0,0 +1,10 @@ + + + + + + +

      Redirecting to struct.WO.html...

      + + + \ No newline at end of file diff --git a/volatile_register/all.html b/volatile_register/all.html new file mode 100644 index 0000000..db9a9a8 --- /dev/null +++ b/volatile_register/all.html @@ -0,0 +1,3 @@ +List of all items in this crate

      [−] + + List of all items

      Structs

      \ No newline at end of file diff --git a/volatile_register/index.html b/volatile_register/index.html new file mode 100644 index 0000000..e937715 --- /dev/null +++ b/volatile_register/index.html @@ -0,0 +1,49 @@ +volatile_register - Rust

      [−][src]Crate volatile_register

      Volatile access to memory mapped hardware registers

      +

      Usage

      +
      +use volatile_register::RW;
+
+// Create a struct that represents the memory mapped register block
+/// Nested Vector Interrupt Controller
+#[repr(C)]
+pub struct Nvic {
+    /// Interrupt Set-Enable
+    pub iser: [RW<u32>; 8],
+    reserved0: [u32; 24],
+    /// Interrupt Clear-Enable
+    pub icer: [RW<u32>; 8],
+    reserved1: [u32; 24],
+    // .. more registers ..
+}
+
+// Access the registers by casting the base address of the register block
+// to the previously declared `struct`
+let nvic = 0xE000_E100 as *const Nvic;
+// Unsafe because the compiler can't verify the address is correct
+unsafe { (*nvic).iser[0].write(1) }
      +

      Structs

      + + + + + + + + + + + + +
      RO +

      Read-Only register

      + +
      RW +

      Read-Write register

      + +
      WO +

      Write-Only register

      + +
      \ No newline at end of file diff --git a/volatile_register/sidebar-items.js b/volatile_register/sidebar-items.js new file mode 100644 index 0000000..52b4203 --- /dev/null +++ b/volatile_register/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"struct":[["RO","Read-Only register"],["RW","Read-Write register"],["WO","Write-Only register"]]}); \ No newline at end of file diff --git a/volatile_register/struct.RO.html b/volatile_register/struct.RO.html new file mode 100644 index 0000000..615054c --- /dev/null +++ b/volatile_register/struct.RO.html @@ -0,0 +1,15 @@ +volatile_register::RO - Rust

      [−][src]Struct volatile_register::RO

      pub struct RO<T> where
          T: Copy,        { /* fields omitted */ }

      Read-Only register

      +

      Methods

      impl<T> RO<T> where
          T: Copy, 
      [src]

      Reads the value of the register

      +

      Auto Trait Implementations

      impl<T> Send for RO<T> where
          T: Send, 

      impl<T> !Sync for RO<T>

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/volatile_register/struct.RW.html b/volatile_register/struct.RW.html new file mode 100644 index 0000000..9e7baba --- /dev/null +++ b/volatile_register/struct.RW.html @@ -0,0 +1,19 @@ +volatile_register::RW - Rust

      [−][src]Struct volatile_register::RW

      pub struct RW<T> where
          T: Copy,        { /* fields omitted */ }

      Read-Write register

      +

      Methods

      impl<T> RW<T> where
          T: Copy, 
      [src]

      Performs a read-modify-write operation

      +

      NOTE: unsafe because writes to a register are side effectful

      +

      Reads the value of the register

      +

      Writes a value into the register

      +

      NOTE: unsafe because writes to a register are side effectful

      +

      Auto Trait Implementations

      impl<T> Send for RW<T> where
          T: Send, 

      impl<T> !Sync for RW<T>

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/volatile_register/struct.WO.html b/volatile_register/struct.WO.html new file mode 100644 index 0000000..30a7954 --- /dev/null +++ b/volatile_register/struct.WO.html @@ -0,0 +1,16 @@ +volatile_register::WO - Rust

      [−][src]Struct volatile_register::WO

      pub struct WO<T> where
          T: Copy,        { /* fields omitted */ }

      Write-Only register

      +

      Methods

      impl<T> WO<T> where
          T: Copy, 
      [src]

      Writes value into the register

      +

      NOTE: unsafe because writes to a register are side effectful

      +

      Auto Trait Implementations

      impl<T> Send for WO<T> where
          T: Send, 

      impl<T> !Sync for WO<T>

      Blanket Implementations

      impl<T, U> TryFrom for T where
          T: From<U>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T> From for T
      [src]

      Performs the conversion.

      +

      impl<T, U> TryInto for T where
          U: TryFrom<T>, 
      [src]

      +
      🔬 This is a nightly-only experimental API. (try_from)

      The type returned in the event of a conversion error.

      +

      🔬 This is a nightly-only experimental API. (try_from)

      Performs the conversion.

      +

      impl<T, U> Into for T where
          U: From<T>, 
      [src]

      Performs the conversion.

      +

      impl<T> Borrow for T where
          T: ?Sized, 
      [src]

      Immutably borrows from an owned value. Read more

      +

      impl<T> BorrowMut for T where
          T: ?Sized, 
      [src]

      Mutably borrows from an owned value. Read more

      +

      impl<T> Any for T where
          T: 'static + ?Sized, 
      [src]

      🔬 This is a nightly-only experimental API. (get_type_id)

      this method will likely be replaced by an associated static

      +

      Gets the TypeId of self. Read more

      +
      \ No newline at end of file diff --git a/wheel.svg b/wheel.svg new file mode 100644 index 0000000..44381a4 --- /dev/null +++ b/wheel.svg @@ -0,0 +1 @@ + \ No newline at end of file