bump the cortex-m-rt to v0.4.0

src/examples/_0_hello.rs

@@ -10,6 +10,7 @@
 //! extern crate cortex_m;
 //! extern crate cortex_m_rt;
 //! extern crate cortex_m_semihosting;
+//! extern crate panic_abort; // panicking behavior
 //! 
 //! use core::fmt::Write;
 //! 

src/examples/_1_itm.rs

@@ -1,15 +1,14 @@
 //! Sends "Hello, world!" through the ITM port 0
 //!
-//! **IMPORTANT** Not all Cortex-M chips support ITM. You'll have to connect the
-//! microcontroller's SWO pin to the SWD interface. Note that some development
-//! boards don't provide this option.
+//! **IMPORTANT** Not all Cortex-M chips support ITM. You'll have to connect the microcontroller's
+//! SWO pin to the SWD interface. Note that some development boards don't provide this option.
 //!
 //! ITM is much faster than semihosting. Like 4 orders of magnitude or so.
 //!
-//! You'll need [`itmdump`] to receive the message on the host plus you'll need
-//! to uncomment the `monitor` commands in the `.gdbinit` file.
+//! You'll need [`itmdump`] to receive the message on the host plus you'll need to uncomment the
+//! `monitor` commands in the `.gdbinit` file.
 //!
-//! [`itmdump`]: https://docs.rs/itm/0.1.1/itm/
+//! [`itmdump`]: https://docs.rs/itm/0.2.1/itm/
 //!
 //! ---
 //!
@@ -21,6 +20,7 @@
 //! #[macro_use]
 //! extern crate cortex_m;
 //! extern crate cortex_m_rt;
+//! extern crate panic_itm; // panicking behavior
 //! 
 //! use cortex_m::{asm, Peripherals};
 //! 
@@ -29,6 +29,9 @@
 //!     let mut itm = p.ITM;
 //! 
 //!     iprintln!(&mut itm.stim[0], "Hello, world!");
+//! 
+//!     // Also prints the panic message to the ITM
+//!     panic!("Oops");
 //! }
 //! 
 //! // As we are not using interrupts, we just register a dummy catch all handler

src/examples/_2_panic.rs

@@ -1,55 +1,28 @@
-//! Defining the panic handler
+//! Changing the panic handler
 //!
-//! The panic handler can be defined through the `panic_fmt` [language item][1].
-//! Make sure that the "abort-on-panic" feature of the cortex-m-rt crate is
-//! disabled to avoid redefining the language item.
+//! The easiest way to change the panic handler is to use a different [panic implementation
+//! crate][0].
 //!
-//! [1]: https://doc.rust-lang.org/unstable-book/language-features/lang-items.html
+//! [0]: https://crates.io/keywords/panic-impl
 //!
 //! ---
 //!
 //! ```
 //! 
-//! #![feature(core_intrinsics)]
-//! #![feature(lang_items)]
 //! #![feature(used)]
 //! #![no_std]
 //! 
 //! extern crate cortex_m;
 //! extern crate cortex_m_rt;
-//! extern crate cortex_m_semihosting;
-//! 
-//! use core::fmt::Write;
-//! use core::intrinsics;
+//! // extern crate panic_abort;
+//! extern crate panic_semihosting; // reports panic messages to the host stderr using semihosting
 //! 
 //! use cortex_m::asm;
-//! use cortex_m_semihosting::hio;
 //! 
 //! fn main() {
 //!     panic!("Oops");
 //! }
 //! 
-//! #[lang = "panic_fmt"]
-//! #[no_mangle]
-//! pub unsafe extern "C" fn rust_begin_unwind(
-//!     args: core::fmt::Arguments,
-//!     file: &'static str,
-//!     line: u32,
-//!     col: u32,
-//! ) -> ! {
-//!     if let Ok(mut stdout) = hio::hstdout() {
-//!         write!(stdout, "panicked at '")
-//!             .and_then(|_| {
-//!                 stdout
-//!                     .write_fmt(args)
-//!                     .and_then(|_| writeln!(stdout, "', {}:{}:{}", file, line, col))
-//!             })
-//!             .ok();
-//!     }
-//! 
-//!     intrinsics::abort()
-//! }
-//! 
 //! // As we are not using interrupts, we just register a dummy catch all handler
 //! #[link_section = ".vector_table.interrupts"]
 //! #[used]

src/examples/_3_crash.rs

@@ -1,12 +1,11 @@
 //! Debugging a crash (exception)
 //!
-//! The `cortex-m-rt` crate provides functionality for this through a default
-//! exception handler. When an exception is hit, the default handler will
-//! trigger a breakpoint and in this debugging context the stacked registers
-//! are accessible.
+//! The `cortex-m-rt` crate provides functionality for this through a default exception handler.
+//! When an exception is hit, the default handler will trigger a breakpoint and in this debugging
+//! context the stacked registers are accessible.
 //!
-//! In you run the example below, you'll be able to inspect the state of your
-//! program under the debugger using these commands:
+//! In you run the example below, you'll be able to inspect the state of your program under the
+//! debugger using these commands:
 //!
 //! ``` text
 //! (gdb) # Exception frame = program state during the crash
@@ -65,6 +64,7 @@
 //! 
 //! extern crate cortex_m;
 //! extern crate cortex_m_rt;
+//! extern crate panic_abort; // panicking behavior
 //! 
 //! use core::ptr;
 //! 

src/examples/_4_override_exception_handler.rs

@@ -4,8 +4,7 @@
 //!
 //! [1]: https://docs.rs/cortex-m-rt/0.3.2/cortex_m_rt/macro.exception.html
 //!
-//! The default exception handler can be overridden using the
-//! [`default_handler!`][2] macro
+//! The default exception handler can be overridden using the [`default_handler!`][2] macro
 //!
 //! [2]: https://docs.rs/cortex-m-rt/0.3.2/cortex_m_rt/macro.default_handler.html
 //!
@@ -19,6 +18,7 @@
 //! extern crate cortex_m;
 //! #[macro_use(exception)]
 //! extern crate cortex_m_rt;
+//! extern crate panic_abort; // panicking behavior
 //! 
 //! use core::ptr;
 //! 

src/examples/_5_device.rs

@@ -1,25 +1,22 @@
 //! Using a device crate
 //!
-//! Crates generated using [`svd2rust`] are referred to as device crates. These
-//! crates provides an API to access the peripherals of a device. When you
-//! depend on one of these crates and the "rt" feature is enabled you don't need
-//! link to the cortex-m-rt crate.
+//! Crates generated using [`svd2rust`] are referred to as device crates. These crates provides an
+//! API to access the peripherals of a device. When you depend on one of these crates and the "rt"
+//! feature is enabled you don't need link to the cortex-m-rt crate.
 //!
 //! [`svd2rust`]: https://crates.io/crates/svd2rust
 //!
-//! Device crates also provide an `interrupt!` macro to register interrupt
-//! handlers.
+//! Device crates also provide an `interrupt!` macro to register interrupt handlers.
 //!
-//! This example depends on the [`stm32f103xx`] crate so you'll have to add it
-//! to your Cargo.toml.
+//! This example depends on the [`stm32f103xx`] crate so you'll have to add it to your Cargo.toml.
 //!
 //! [`stm32f103xx`]: https://crates.io/crates/stm32f103xx
 //!
 //! ```
-//! $ edit Cargo.toml && cat $_
+//! $ edit Cargo.toml && tail $_
 //! [dependencies.stm32f103xx]
 //! features = ["rt"]
-//! version = "0.8.0"
+//! version = "0.9.0"
 //! ```
 //!
 //! ---
@@ -31,9 +28,11 @@
 //! #![no_std]
 //! 
 //! extern crate cortex_m;
+//! // extern crate cortex_m_rt; // included in the device crate
 //! extern crate cortex_m_semihosting;
 //! #[macro_use(exception, interrupt)]
 //! extern crate stm32f103xx;
+//! extern crate panic_abort; // panicking behavior
 //! 
 //! use core::cell::RefCell;
 //! use core::fmt::Write;
@@ -43,11 +42,9 @@
 //! use cortex_m_semihosting::hio::{self, HStdout};
 //! use stm32f103xx::Interrupt;
 //! 
-//! static HSTDOUT: Mutex<RefCell<Option<HStdout>>> =
-//!     Mutex::new(RefCell::new(None));
+//! static HSTDOUT: Mutex<RefCell<Option<HStdout>>> = Mutex::new(RefCell::new(None));
 //! 
-//! static NVIC: Mutex<RefCell<Option<cortex_m::peripheral::NVIC>>> =
-//!     Mutex::new(RefCell::new(None));
+//! static NVIC: Mutex<RefCell<Option<cortex_m::peripheral::NVIC>>> = Mutex::new(RefCell::new(None));
 //! 
 //! fn main() {
 //!     let global_p = cortex_m::Peripherals::take().unwrap();

src/examples/_6_allocator.rs

@@ -1,7 +1,6 @@
 //! How to use the heap and a dynamic memory allocator
 //!
-//! This example depends on the alloc-cortex-m crate so you'll have to add it
-//! to your Cargo.toml:
+//! This example depends on the alloc-cortex-m crate so you'll have to add it to your Cargo.toml:
 //!
 //! ``` text
 //! # or edit the Cargo.toml file manually
@@ -13,8 +12,8 @@
 //! ```
 //! 
 //! #![feature(alloc)]
-//! #![feature(used)]
 //! #![feature(global_allocator)]
+//! #![feature(used)]
 //! #![no_std]
 //! 
 //! // This is the allocator crate; you can use a different one
@@ -24,26 +23,27 @@
 //! extern crate cortex_m;
 //! extern crate cortex_m_rt;
 //! extern crate cortex_m_semihosting;
+//! extern crate panic_abort; // panicking behavior
 //! 
 //! use core::fmt::Write;
 //! 
+//! use alloc_cortex_m::CortexMHeap;
 //! use cortex_m::asm;
 //! use cortex_m_semihosting::hio;
-//! use alloc_cortex_m::CortexMHeap;
 //! 
 //! #[global_allocator]
 //! static ALLOCATOR: CortexMHeap = CortexMHeap::empty();
 //! 
 //! extern "C" {
 //!     static mut _sheap: u32;
-//!     static mut _eheap: u32;
 //! }
 //! 
+//! const HEAP_SIZE: usize = 1024; // in bytes
+//! 
 //! fn main() {
 //!     // Initialize the allocator
 //!     let start = unsafe { &mut _sheap as *mut u32 as usize };
-//!     let end = unsafe { &mut _eheap as *mut u32 as usize };
-//!     unsafe { ALLOCATOR.init(start, end - start) }
+//!     unsafe { ALLOCATOR.init(start, HEAP_SIZE) }
 //! 
 //!     // Growable array allocated on the heap
 //!     let xs = vec![0, 1, 2];