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adding uart04 example. uses interrupts

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This commit is contained in:
David Welch
2012-07-19 13:05:54 -04:00
parent 708bf26f8a
commit 3ac806e23c
5 changed files with 425 additions and 0 deletions
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71
uart04/Makefile Normal file
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ARMGNU ?= arm-none-eabi
COPS = -Wall -O2 -nostdlib -nostartfiles -ffreestanding
gcc : uart02.hex uart02.bin
all : gcc clang
clean :
rm -f *.o
rm -f *.bin
rm -f *.hex
rm -f *.elf
rm -f *.list
rm -f *.img
rm -f *.bc
rm -f *.clang.opt.s
vectors.o : vectors.s
$(ARMGNU)-as vectors.s -o vectors.o
uart02.o : uart02.c
$(ARMGNU)-gcc $(COPS) -c uart02.c -o uart02.o
uart02.elf : memmap vectors.o uart02.o
$(ARMGNU)-ld vectors.o uart02.o -T memmap -o uart02.elf
$(ARMGNU)-objdump -D uart02.elf > uart02.list
uart02.bin : uart02.elf
$(ARMGNU)-objcopy uart02.elf -O binary uart02.bin
uart02.hex : uart02.elf
$(ARMGNU)-objcopy uart02.elf -O ihex uart02.hex
LOPS = -Wall -m32 -emit-llvm
LLCOPS = -march=arm -mcpu=arm1176jzf-s
LLCOPS0 = -march=arm
LLCOPS1 = -march=arm -mcpu=arm1176jzf-s
COPS = -Wall -O2 -nostdlib -nostartfiles -ffreestanding
OOPS = -std-compile-opts
clang : uart02.clang.hex uart02.clang.bin
uart02.clang.bc : uart02.c
clang $(LOPS) -c uart02.c -o uart02.clang.bc
uart02.clang.opt.elf : memmap vectors.o uart02.clang.bc
opt $(OOPS) uart02.clang.bc -o uart02.clang.opt.bc
llc $(LLCOPS) uart02.clang.opt.bc -o uart02.clang.opt.s
$(ARMGNU)-as uart02.clang.opt.s -o uart02.clang.opt.o
$(ARMGNU)-ld -o uart02.clang.opt.elf -T memmap vectors.o uart02.clang.opt.o
$(ARMGNU)-objdump -D uart02.clang.opt.elf > uart02.clang.opt.list
uart02.clang.hex : uart02.clang.opt.elf
$(ARMGNU)-objcopy uart02.clang.opt.elf uart02.clang.hex -O ihex
uart02.clang.bin : uart02.clang.opt.elf
$(ARMGNU)-objcopy uart02.clang.opt.elf uart02.clang.bin -O binary

22
uart04/README Normal file
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See the top level README for information on where to find the
schematic and programmers reference manual for the ARM processor
on the raspberry pi. Also find information on how to load and run
these programs.
Based on uart02 and blinker05. Like blinker05 this is a multi stage
program killing three birds with one stone. First it uses polling
of the interrupt status lines to show what happens to the registers, etc
when an rx based interrupt occurs. Then it uses interrupt polling to
receive characters rather than the uart status register. Then it
enables the interrupts to the arm and uses an interrupt service routine
to receive characters from the uart.
As with other parts of this mini uart, the documentation has errors,
bits that are marked as not used were required to make this work. When
working with this mini uart also have as a reference a real 16550 manual
if it doesnt work the way the BCM manual says, then pretend it is a
real 16550 and see what happens.
Note that the mini uart interrupt is not interrupt 57 uart_int, it is
interrupt 29 aux_int.

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uart04/memmap Normal file
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MEMORY
{
ram : ORIGIN = 0x8000, LENGTH = 0x10000
}
SECTIONS
{
.text : { *(.text*) } > ram
.bss : { *(.bss*) } > ram
}

224
uart04/uart04.c Normal file
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//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
extern void PUT32 ( unsigned int, unsigned int );
extern unsigned int GET32 ( unsigned int );
extern void dummy ( unsigned int );
extern void enable_irq ( void );
extern void enable_fiq ( void );
#define GPFSEL1 0x20200004
#define GPSET0 0x2020001C
#define GPCLR0 0x20200028
#define GPPUD 0x20200094
#define GPPUDCLK0 0x20200098
#define AUX_ENABLES 0x20215004
#define AUX_MU_IO_REG 0x20215040
#define AUX_MU_IER_REG 0x20215044
#define AUX_MU_IIR_REG 0x20215048
#define AUX_MU_LCR_REG 0x2021504C
#define AUX_MU_MCR_REG 0x20215050
#define AUX_MU_LSR_REG 0x20215054
#define AUX_MU_MSR_REG 0x20215058
#define AUX_MU_SCRATCH 0x2021505C
#define AUX_MU_CNTL_REG 0x20215060
#define AUX_MU_STAT_REG 0x20215064
#define AUX_MU_BAUD_REG 0x20215068
#define IRQ_BASIC 0x2000B200
#define IRQ_PEND1 0x2000B204
#define IRQ_PEND2 0x2000B208
#define IRQ_FIQ_CONTROL 0x2000B210
#define IRQ_ENABLE1 0x2000B210
#define IRQ_ENABLE2 0x2000B214
#define IRQ_ENABLE_BASIC 0x2000B218
#define IRQ_DISABLE1 0x2000B21C
#define IRQ_DISABLE2 0x2000B220
#define IRQ_DISABLE_BASIC 0x2000B224
//GPIO14 TXD0 and TXD1
//GPIO15 RXD0 and RXD1
//alt function 5 for uart1
//alt function 0 for uart0
//((250,000,000/115200)/8)-1 = 270
//------------------------------------------------------------------------
void uart_init ( void )
{
unsigned int ra;
PUT32(AUX_ENABLES,1);
PUT32(AUX_MU_IER_REG,0);
PUT32(AUX_MU_CNTL_REG,0);
PUT32(AUX_MU_LCR_REG,3);
PUT32(AUX_MU_MCR_REG,0);
PUT32(AUX_MU_IER_REG,0x5); //enable rx interrupts
PUT32(AUX_MU_IIR_REG,0xC6);
PUT32(AUX_MU_BAUD_REG,270);
ra=GET32(GPFSEL1);
ra&=~(7<<12); //gpio14
ra|=2<<12; //alt5
ra&=~(7<<15); //gpio15
ra|=2<<15; //alt5
PUT32(GPFSEL1,ra);
PUT32(GPPUD,0);
for(ra=0;ra<150;ra++) dummy(ra);
PUT32(GPPUDCLK0,(1<<14)|(1<<15));
for(ra=0;ra<150;ra++) dummy(ra);
PUT32(GPPUDCLK0,0);
PUT32(AUX_MU_CNTL_REG,3);
}
//------------------------------------------------------------------------
void uart_putc ( unsigned int c )
{
while(1)
{
if(GET32(AUX_MU_LSR_REG)&0x20) break;
}
PUT32(AUX_MU_IO_REG,c);
}
//------------------------------------------------------------------------
void hexstrings ( unsigned int d )
{
//unsigned int ra;
unsigned int rb;
unsigned int rc;
rb=32;
while(1)
{
rb-=4;
rc=(d>>rb)&0xF;
if(rc>9) rc+=0x37; else rc+=0x30;
uart_putc(rc);
if(rb==0) break;
}
uart_putc(0x20);
}
//------------------------------------------------------------------------
void hexstring ( unsigned int d )
{
hexstrings(d);
uart_putc(0x0D);
uart_putc(0x0A);
}
volatile unsigned int rxhead;
volatile unsigned int rxtail;
#define RXBUFMASK 0xFFF
volatile unsigned char rxbuffer[RXBUFMASK+1];
//-------------------------------------------------------------------------
void c_irq_handler ( void )
{
unsigned int rb,rc;
//an interrupt has occurred, find out why
while(1) //resolve all interrupts to uart
{
rb=GET32(AUX_MU_IIR_REG);
if((rb&1)==1) break; //no more interrupts
if((rb&6)==4)
{
//receiver holds a valid byte
rc=GET32(AUX_MU_IO_REG); //read byte from rx fifo
rxbuffer[rxhead]=rc&0xFF;
rxhead=(rxhead+1)&RXBUFMASK;
}
}
}
//------------------------------------------------------------------------
int notmain ( unsigned int earlypc )
{
unsigned int ra;
unsigned int rb;
unsigned int rc;
unsigned int rx;
PUT32(IRQ_DISABLE1,1<<29);
uart_init();
hexstring(0x12345678);
for(ra=0;ra<20;ra++) hexstring(ra);
hexstring(0x12345678);
hexstring(earlypc);
PUT32(IRQ_ENABLE1,1<<29);
for(rx=0;rx<5;)
{
ra=GET32(IRQ_PEND1);
if(ra&(1<<29))
{
hexstrings(ra);
hexstrings(GET32(AUX_MU_IIR_REG));
hexstring(GET32(AUX_MU_STAT_REG));
hexstring(GET32(AUX_MU_IO_REG));
hexstrings(GET32(IRQ_PEND1));
hexstrings(GET32(AUX_MU_IIR_REG));
hexstring(GET32(AUX_MU_STAT_REG));
rx++;
}
}
hexstring(0x12345678);
rxhead=rxtail;
for(rx=0;rx<5;)
{
while(rxtail!=rxhead)
{
uart_putc(rxbuffer[rxtail]);
rxtail=(rxtail+1)&RXBUFMASK;
rx++;
}
ra=GET32(IRQ_PEND1);
if(ra&(1<<29))
{
//an interrupt has occurred, find out why
while(1) //resolve all interrupts to uart
{
rb=GET32(AUX_MU_IIR_REG);
if((rb&1)==1) break; //no more interrupts
if((rb&6)==4)
{
//receiver holds a valid byte
rc=GET32(AUX_MU_IO_REG); //read byte from rx fifo
rxbuffer[rxhead]=rc&0xFF;
rxhead=(rxhead+1)&RXBUFMASK;
}
}
}
}
hexstring(0x12345678);
enable_irq();
while(1)
{
while(rxtail!=rxhead)
{
uart_putc(rxbuffer[rxtail]);
rxtail=(rxtail+1)&RXBUFMASK;
rx++;
}
}
return(0);
}
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//
// Copyright (c) 2012 David Welch dwelch@dwelch.com
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//
//-------------------------------------------------------------------------

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uart04/vectors.s Normal file
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;@-------------------------------------------------------------------------
;@-------------------------------------------------------------------------
.globl _start
_start:
ldr pc,reset_handler
ldr pc,undefined_handler
ldr pc,swi_handler
ldr pc,prefetch_handler
ldr pc,data_handler
ldr pc,unused_handler
ldr pc,irq_handler
ldr pc,fiq_handler
reset_handler: .word reset
undefined_handler: .word hang
swi_handler: .word hang
prefetch_handler: .word hang
data_handler: .word hang
unused_handler: .word hang
irq_handler: .word irq
fiq_handler: .word hang
reset:
mov r0,#0x8000
mov r1,#0x0000
ldmia r0!,{r2,r3,r4,r5,r6,r7,r8,r9}
stmia r1!,{r2,r3,r4,r5,r6,r7,r8,r9}
ldmia r0!,{r2,r3,r4,r5,r6,r7,r8,r9}
stmia r1!,{r2,r3,r4,r5,r6,r7,r8,r9}
;@ (PSR_IRQ_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
mov r0,#0xD2
msr cpsr_c,r0
mov sp,#0x8000
;@ (PSR_FIQ_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
mov r0,#0xD1
msr cpsr_c,r0
mov sp,#0x4000
;@ (PSR_SVC_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
mov r0,#0xD3
msr cpsr_c,r0
mov sp,#0x8000000
;@ SVC MODE, IRQ ENABLED, FIQ DIS
;@mov r0,#0x53
;@msr cpsr_c, r0
bl notmain
hang: b hang
.globl PUT32
PUT32:
str r1,[r0]
bx lr
.globl GET32
GET32:
ldr r0,[r0]
bx lr
.globl dummy
dummy:
bx lr
.globl enable_irq
enable_irq:
mrs r0,cpsr
bic r0,r0,#0x80
msr cpsr_c,r0
bx lr
irq:
push {r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
bl c_irq_handler
pop {r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
subs pc,lr,#4
;@-------------------------------------------------------------------------
;@-------------------------------------------------------------------------
;@-------------------------------------------------------------------------
;@
;@ Copyright (c) 2012 David Welch dwelch@dwelch.com
;@
;@ Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
;@
;@ The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
;@
;@ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
;@
;@-------------------------------------------------------------------------