133 lines
4.3 KiB
C
133 lines
4.3 KiB
C
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//-------------------------------------------------------------------------
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//-------------------------------------------------------------------------
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extern void PUT32 ( unsigned int, unsigned int );
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extern unsigned int GET32 ( unsigned int );
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extern void dummy ( unsigned int );
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extern void enable_irq ( void );
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extern void enable_fiq ( void );
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#define ARM_TIMER_LOD 0x2000B400
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#define ARM_TIMER_VAL 0x2000B404
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#define ARM_TIMER_CTL 0x2000B408
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#define ARM_TIMER_CLI 0x2000B40C
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#define ARM_TIMER_RIS 0x2000B410
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#define ARM_TIMER_MIS 0x2000B414
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#define ARM_TIMER_RLD 0x2000B418
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#define ARM_TIMER_DIV 0x2000B41C
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#define ARM_TIMER_CNT 0x2000B420
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#define SYSTIMERCLO 0x20003004
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#define GPFSEL1 0x20200004
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#define GPSET0 0x2020001C
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#define GPCLR0 0x20200028
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#define GPFSEL3 0x2020000C
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#define GPFSEL4 0x20200010
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#define GPSET1 0x20200020
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#define GPCLR1 0x2020002C
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#define IRQ_BASIC 0x2000B200
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#define IRQ_PEND1 0x2000B204
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#define IRQ_PEND2 0x2000B208
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#define IRQ_FIQ_CONTROL 0x2000B210
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#define IRQ_ENABLE_BASIC 0x2000B218
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#define IRQ_DISABLE_BASIC 0x2000B224
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volatile unsigned int icount;
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//-------------------------------------------------------------------------
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void c_irq_handler ( void )
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{
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icount++;
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if(icount&1)
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{
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PUT32(GPSET1,1<<(47-32));
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PUT32(GPSET1,1<<(35-32));
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}
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else
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{
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PUT32(GPCLR1,1<<(47-32));
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PUT32(GPCLR1,1<<(35-32));
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}
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PUT32(ARM_TIMER_CLI,0);
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}
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//-------------------------------------------------------------------------
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int notmain ( void )
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{
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unsigned int ra;
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PUT32(IRQ_DISABLE_BASIC,1);
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ra=GET32(GPFSEL4);
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ra&=~(7<<21);
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ra|=1<<21;
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PUT32(GPFSEL4,ra);
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ra=GET32(GPFSEL3);
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ra&=~(7<<15);
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ra|=1<<15;
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PUT32(GPFSEL3,ra);
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PUT32(GPSET1,1<<(47-32));
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PUT32(GPCLR1,1<<(35-32));
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PUT32(ARM_TIMER_CTL,0x003E0000);
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PUT32(ARM_TIMER_LOD,1000000-1);
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PUT32(ARM_TIMER_RLD,1000000-1);
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PUT32(ARM_TIMER_DIV,0x000000F9);
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PUT32(ARM_TIMER_CLI,0);
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PUT32(ARM_TIMER_CTL,0x003E00A2);
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for(ra=0;ra<2;ra++)
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{
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PUT32(GPSET1,1<<(47-32));
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PUT32(GPCLR1,1<<(35-32));
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while(1) if(GET32(ARM_TIMER_MIS)) break;
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PUT32(ARM_TIMER_CLI,0);
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PUT32(GPCLR1,1<<(47-32));
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PUT32(GPSET1,1<<(35-32));
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while(1) if(GET32(ARM_TIMER_MIS)) break;
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PUT32(ARM_TIMER_CLI,0);
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}
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PUT32(ARM_TIMER_LOD,2000000-1);
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PUT32(ARM_TIMER_RLD,2000000-1);
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PUT32(ARM_TIMER_CLI,0);
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PUT32(IRQ_ENABLE_BASIC,1);
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for(ra=0;ra<2;ra++)
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{
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PUT32(GPSET1,1<<(47-32));
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PUT32(GPCLR1,1<<(35-32));
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while(1) if(GET32(IRQ_BASIC)&1) break;
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PUT32(ARM_TIMER_CLI,0);
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PUT32(GPCLR1,1<<(47-32));
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PUT32(GPSET1,1<<(35-32));
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while(1) if(GET32(IRQ_BASIC)&1) break;
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PUT32(ARM_TIMER_CLI,0);
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}
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PUT32(ARM_TIMER_LOD,4000000-1);
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PUT32(ARM_TIMER_RLD,4000000-1);
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icount=0;
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enable_irq();
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while(1) continue;
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return(0);
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}
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//-------------------------------------------------------------------------
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//-------------------------------------------------------------------------
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//-------------------------------------------------------------------------
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//
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// Copyright (c) 2012 David Welch dwelch@dwelch.com
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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//
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//-------------------------------------------------------------------------
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