56 lines
2.6 KiB
Plaintext
56 lines
2.6 KiB
Plaintext
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See the top level README for information on where to find the
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schematic and programmers reference manual for the ARM processor
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on the raspberry pi. Also find information on how to load and run
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these programs. And how to hook up your host system to the uart on the
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raspberry pi.
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This example does a couple of things. First it is a simple example of
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using the mmu. It does it such that the physical address = virtual
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address. Why would you do that? To turn on the data cache and not
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have memory mapped I/O (uart ports, timers hardware, etc) be cached.
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Second, the ldrex/strex instruction pair can and have been improperly
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used by programmers. The issue is that programmers are told in the
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ARM ARM that ldrex/strex has been added among other reasons to allow
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for atomic protection in memory shared by the multiple processors.
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Programmers are warned that for uniprocessor systems the hardware may
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not have the protection mechanism (which means DONT use ldrex/strex).
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In the AMBA/AXI spec hardware engineers are told that for normal LDR/STR
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type accesses return OKAY, meaning it worked, no problems. For exclusive
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accesses (LDREX/STREX) return EXOKAY if it was a successfully exclusive
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access. But if you dont support exclusive accesses in your memory
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controller then just return OKAY. Well a return of OKAY for an STREX
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is a fail as far as the exclusive access goes. And you will see in
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very popular, open source, software the LDREX/STREX instruction pair
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used for any ARMv6 or newer processor, uniprocessor or multi. Dumb
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luck prevails because the L1 cache in the ARMv6 and newer handles the
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LDREX/STREX pair and makes it all work. So if L1 is off, and the access
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goes out on the AXI bus where the vendor's memory controller hardware
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lives. You are at the mercy of the hardware vendor, and a very popular
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ARMv6 or newer vendor doesnt necessarily support exclusive access for
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a uniprocessor system.
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Now when trying to remember and find all of these details, I figured it
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would be trivial to test a new system to see if it has this problem.
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Simple right, just two instructions, check the result right? Wrong,
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you need the mmu on. So I had to go revisit all of that as well and
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build this example for myself.
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The good news, is from what I can tell the processor used here does
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appear to work.
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On a system that is not giving a strex fail:
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00001234 00000000 00000000
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00001234 00000000 00000000
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00001234 00000000 00000000
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00001234 00000000 00000000
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On a system that does not support shared memory.
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00001234 00000001 00000001
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00001234 00000001 00000001
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00001234 00000000 00000000
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00001234 00000001 00000001
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