44 lines
1.9 KiB
Plaintext
44 lines
1.9 KiB
Plaintext
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See the top level README file for more information on documentation
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and how to run these programs.
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Derived from uart05
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This is specific to the Raspberry Pi 2 as it experiments with the
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multiple processor cores.
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So the little additional information we have from Broadcom about
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the raspberry pi 2 processor, shows some mailbox addresses that
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cause interrupts. If you disassemble the first 0x100 bytes of memory
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as we find it when kernel7.img runs. At least as of this writing it
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is in that space. There is vbar, mvbar manipulation (moving the
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entry from that interrupt/event to somewhere other than zero) various
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things including the other cores waiting on an interrupt. These
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addresses are one of four mailboxes for each of these cores, writing
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with an address triggers the interrupt which triggers this code to then
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ultimately branch to that address for that core.
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So if you write to address
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0x4000009C for core 1
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0x400000AC for core 2
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0x400000BC for core 3
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With the address to the entry point for the code you want that core
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to run...it will start that core.
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This program starts up the other three cores, lets them fight over the
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memory location at address 0x40. Core 0 reads 0x40 and prints out
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when it sees it change. It is going to look somewhat random.
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So we have to be careful not messing with this first 0x100 bytes, unless
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you know what you are doing or you have started each core. Check
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blinker05 rpi2 version. As of late 2015 the GPU loader (start.elf)
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which leaves this code for the ARM is now putting the ARM in what is
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called hyp mode or hypervisor mode. A little/lot different than the
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supervisor mode that we have been used to for so many years. You dont
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switch modes for an interrupt, etc you are just in hyp mode. With
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or without hyp mode we can move the exception handler table from the
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traditional address zero to other places, and not having to mess with
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this bootcode left for us if we dont want to, yet still do fun things.
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