# Special device for global options always define BUS_DIV 1 define CPU_IDIV 2 define CPU_ODIV 1 define CPU_MUL 20 define CRYSTAL 8 end always option nproc define NPROC %1 end option option nbuf define NBUF %1 end option option nfile define NFILE %1 end option option ninode define NINODE %1 end option option smapsiz define SMAPSIZ %1 end option option hz define HZ %1 end option option haltreboot define HALTREBOOT YES end option option blreboot set BLREBOOT -p end option option partition define PARTITION "%1" end option option nmount define NMOUNT %1 end option # Now for the device config options: option crystal define CRYSTAL %1 end option # DC0 option debug=disabled define DC0_DEBUG DEVCFG0_DEBUG_DISABLED end option option debug=enabled define DC0_DEBUG DEVCFG0_DEBUG_ENABLED end option option debug=ice define DC0_ICE DEVCFG0_ICESEL end option # DC1 option fnosc=frc define DC1_FNOSC DEVCFG1_FNOSC_FRC end option option fnosc=frcdivpll define DC1_FNOSC DEVCFG1_FNOSC_FRCDIVPLL end option option fnosc=pri define DC1_FNOSC DEVCFG1_FNOSC_PRI end option option fnosc=pripll define DC1_FNOSC DEVCFG1_FNOSC_PRIPLL end option option fnosc=sec define DC1_FNOSC DEVCFG1_FNOSC_SEC end option option fnosc=lprc define DC1_FNOSC DEVCFG1_FNOSC_LPRC end option option fnosc=frcdiv define DC1_FNOSC DEVCFG1_FNOSC_FRCDIV end option option secondary=on define DC1_SOSC DEVCFG1_FSOSCEN end option option secondary=off define DC1_SOSC 0 end option option switchover=on define DC1_IESO DEVCFG1_IESO option option switchover=off define DC1_IESO 0 option option osc=ext define DC1_POSCMOD DEVCFG1_POSCMOD_EXT end option option osc=xt define DC1_POSCMOD DEVCFG1_POSCMOD_XT end option option osc=hs define DC1_POSCMOD DEVCFG1_POSCMOD_HS end option option osc=off define DC1_POSCMOD DEVCFG1_POSCMOD_DISABLE end option option oscio=io define DC1_OSCIOFNC 0 end option option oscio=clock define DC1_OSCIOFNC DEVCFG1_OSCIOFNC end option option busdiv=1 define DC1_PBDIV DEVCFG1_FPBDIV_1 define BUS_DIV 1 end option option busdiv=2 define DC1_PBDIV DEVCFG1_FPBDIV_2 define BUS_DIV 2 end option option busdiv=4 define DC1_PBDIV DEVCFG1_FPBDIV_4 define BUS_DIV 4 end option option busdiv=8 define DC1_PBDIV DEVCFG1_FPBDIV_8 define BUS_DIV 8 end option option fsmonitor=on define DC1_CKM 0 end option option fsmonitor=off define DC1_CKM DEVCFG1_FCKM_DISABLE end option option fsswitch=on define DC1_CKS 0 end option option fsswitch=off define DC1_CKS DEVCFG1_FCKS_DISABLE end option option wdtps=1 define DC1_WDTPS DEVCFG1_WDTPS_1 end option option wdtps=2 define DC1_WDTPS DEVCFG1_WDTPS_2 end option option wdtps=4 define DC1_WDTPS DEVCFG1_WDTPS_4 end option option wdtps=8 define DC1_WDTPS DEVCFG1_WDTPS_8 end option option wdtps=16 define DC1_WDTPS DEVCFG1_WDTPS_16 end option option wdtps=32 define DC1_WDTPS DEVCFG1_WDTPS_32 end option option wdtps=64 define DC1_WDTPS DEVCFG1_WDTPS_64 end option option wdtps=128 define DC1_WDTPS DEVCFG1_WDTPS_128 end option option wdtps=256 define DC1_WDTPS DEVCFG1_WDTPS_256 end option option wdtps=512 define DC1_WDTPS DEVCFG1_WDTPS_512 end option option wdtps=1024 define DC1_WDTPS DEVCFG1_WDTPS_1024 end option option wdtps=2048 define DC1_WDTPS DEVCFG1_WDTPS_2048 end option option wdtps=4096 define DC1_WDTPS DEVCFG1_WDTPS_4096 end option option wdtps=8192 define DC1_WDTPS DEVCFG1_WDTPS_8192 end option option wdtps=16384 define DC1_WDTPS DEVCFG1_WDTPS_16384 end option option wdtps=32768 define DC1_WDTPS DEVCFG1_WDTPS_32768 end option option wdtps=65536 define DC1_WDTPS DEVCFG1_WDTPS_65536 end option option wdtps=131072 define DC1_WDTPS DEVCFG1_WDTPS_131072 end option option wdtps=262144 define DC1_WDTPS DEVCFG1_WDTPS_262144 end option option wdtps=524288 define DC1_WDTPS DEVCFG1_WDTPS_524288 end option option wdtps=1048576 define DC1_WDTPS DEVCFG1_WDTPS_1048576 end option option watchdog=on define DC1_WDTEN DEVCFG1_FWDTEN end option option watchdog=off define DC1_WDTEN 0 end option # DC2 option pllidiv=1 define DC2_PLLIDIV DEVCFG2_FPLLIDIV_1 define CPU_IDIV 1 end option option pllidiv=2 define DC2_PLLIDIV DEVCFG2_FPLLIDIV_2 define CPU_IDIV 2 end option option pllidiv=3 define DC2_PLLIDIV DEVCFG2_FPLLIDIV_3 define CPU_IDIV 3 end option option pllidiv=4 define DC2_PLLIDIV DEVCFG2_FPLLIDIV_4 define CPU_IDIV 4 end option option pllidiv=5 define DC2_PLLIDIV DEVCFG2_FPLLIDIV_5 define CPU_IDIV 5 end option option pllidiv=6 define DC2_PLLIDIV DEVCFG2_FPLLIDIV_6 define CPU_IDIV 6 end option option pllidiv=10 define DC2_PLLIDIV DEVCFG2_FPLLIDIV_10 define CPU_IDIV 10 end option option pllidiv=12 define DC2_PLLIDIV DEVCFG2_FPLLIDIV_12 define CPU_IDIV 12 end option option pllmul=15 define DC2_PLLMUL DEVCFG2_FPLLMUL_15 define CPU_MUL 15 end option option pllmul=16 define DC2_PLLMUL DEVCFG2_FPLLMUL_16 define CPU_MUL 16 end option option pllmul=17 define DC2_PLLMUL DEVCFG2_FPLLMUL_17 define CPU_MUL 17 end option option pllmul=18 define DC2_PLLMUL DEVCFG2_FPLLMUL_18 define CPU_MUL 18 end option option pllmul=19 define DC2_PLLMUL DEVCFG2_FPLLMUL_19 define CPU_MUL 19 end option option pllmul=20 define DC2_PLLMUL DEVCFG2_FPLLMUL_20 define CPU_MUL 20 end option option pllmul=21 define DC2_PLLMUL DEVCFG2_FPLLMUL_21 define CPU_MUL 21 end option option pllmul=24 define DC2_PLLMUL DEVCFG2_FPLLMUL_24 define CPU_MUL 24 end option option upllidiv=1 define DC2_UPLLIDIV DEVCFG2_UPLLIDIV_1 end option option upllidiv=2 define DC2_UPLLIDIV DEVCFG2_UPLLIDIV_2 end option option upllidiv=3 define DC2_UPLLIDIV DEVCFG2_UPLLIDIV_3 end option option upllidiv=4 define DC2_UPLLIDIV DEVCFG2_UPLLIDIV_4 end option option upllidiv=5 define DC2_UPLLIDIV DEVCFG2_UPLLIDIV_5 end option option upllidiv=6 define DC2_UPLLIDIV DEVCFG2_UPLLIDIV_6 end option option upllidiv=10 define DC2_UPLLIDIV DEVCFG2_UPLLIDIV_10 end option option upllidiv=12 define DC2_UPLLIDIV DEVCFG2_UPLLIDIV_12 end option option upll=on define DC2_UPLL 0 end option option upll=off define DC2_UPLL DEVCFG2_UPLLDIS end option option pllodiv=1 define DC2_PLLODIV DEVCFG2_FPLLODIV_1 define CPU_ODIV 1 end option option pllodiv=2 define DC2_PLLODIV DEVCFG2_FPLLODIV_2 define CPU_ODIV 2 end option option pllodiv=4 define DC2_PLLODIV DEVCFG2_FPLLODIV_4 define CPU_ODIV 4 end option option pllodiv=8 define DC2_PLLODIV DEVCFG2_FPLLODIV_8 define CPU_ODIV 8 end option option pllodiv=16 define DC2_PLLODIV DEVCFG2_FPLLODIV_16 define CPU_ODIV 16 end option option pllodiv=32 define DC2_PLLODIV DEVCFG2_FPLLODIV_32 define CPU_ODIV 32 end option option pllodiv=64 define DC2_PLLODIV DEVCFG2_FPLLODIV_64 define CPU_ODIV 64 end option option pllodiv=256 define DC2_PLLODIV DEVCFG2_FPLLODIV_256 define CPU_ODIV 256 end option # DC3 option userid define DC3_USERID %1 end option option srs=all define DC3_SRS DEVCFG3_FSRSSEL_ALL end option option srs=1 define DC3_SRS DEVCFG3_FSRSSEL_1 end option option srs=2 define DC3_SRS DEVCFG3_FSRSSEL_2 end option option srs=3 define DC3_SRS DEVCFG3_FSRSSEL_3 end option option srs=4 define DC3_SRS DEVCFG3_FSRSSEL_4 end option option srs=5 define DC3_SRS DEVCFG3_FSRSSEL_5 end option option srs=6 define DC3_SRS DEVCFG3_FSRSSEL_6 end option option srs=7 define DC3_SRS DEVCFG3_FSRSSEL_7 end option option mii=on define DC3_MII DEVCFG3_FMIIEN end option option mii=off define DC3_MII 0 end option option eth=default define DC3_ETH DEVCFG3_FETHIO end option option eth=alternate define DC3_ETH 0 end option option can=default define DC3_CAN DEVCFG3_FCANIO end option option can=alternate define DC3_CAN 0 end option option usbid=usb define DC3_USBID DEVCFG3_FUSBIDIO end option option usbid=io define DC3_USBID 0 end option option vbuson=usb define DC3_VBUSON DEVCFG3_FVBUSONIO end option option vbuson=io define DC3_VBUSON 0 end option