538 lines
18 KiB
C
538 lines
18 KiB
C
/*
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* Cisco router simulation platform.
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* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
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*
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*/
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/*
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* Copyright (C) yajin 2008 <yajinzhou@gmail.com >
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*
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* This file is part of the virtualmips distribution.
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* See LICENSE file for terms of the license.
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*
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*/
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#ifndef __MIPS_H__
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#define __MIPS_H__
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#include "system.h"
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#include "utils.h"
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/*
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* MIPS General Purpose Registers
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*/
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#define MIPS_GPR_ZERO 0 /* zero */
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#define MIPS_GPR_AT 1 /* at */
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#define MIPS_GPR_V0 2 /* v0 */
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#define MIPS_GPR_V1 3 /* v1 */
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#define MIPS_GPR_A0 4 /* a0 */
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#define MIPS_GPR_A1 5 /* a1 */
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#define MIPS_GPR_A2 6 /* a2 */
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#define MIPS_GPR_A3 7 /* a3 */
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#define MIPS_GPR_T0 8 /* t0 */
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#define MIPS_GPR_T1 9 /* t1 */
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#define MIPS_GPR_T2 10 /* t2 */
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#define MIPS_GPR_T3 11 /* t3 */
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#define MIPS_GPR_T4 12 /* t4 */
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#define MIPS_GPR_T5 13 /* t5 */
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#define MIPS_GPR_T6 14 /* t6 */
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#define MIPS_GPR_T7 15 /* t7 */
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#define MIPS_GPR_S0 16 /* s0 */
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#define MIPS_GPR_S1 17 /* s1 */
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#define MIPS_GPR_S2 18 /* s2 */
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#define MIPS_GPR_S3 19 /* s3 */
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#define MIPS_GPR_S4 20 /* s4 */
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#define MIPS_GPR_S5 21 /* s5 */
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#define MIPS_GPR_S6 22 /* s6 */
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#define MIPS_GPR_S7 23 /* s7 */
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#define MIPS_GPR_T8 24 /* t8 */
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#define MIPS_GPR_T9 25 /* t9 */
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#define MIPS_GPR_K0 26 /* k0 */
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#define MIPS_GPR_K1 27 /* k1 */
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#define MIPS_GPR_GP 28 /* gp */
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#define MIPS_GPR_SP 29 /* sp */
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#define MIPS_GPR_FP 30 /* fp */
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#define MIPS_GPR_RA 31 /* ra */
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/*
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* Coprocessor 0 (System Coprocessor) Register definitions
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*/
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#define MIPS_CP0_INDEX 0 /* TLB Index */
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#define MIPS_CP0_RANDOM 1 /* TLB Random */
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#define MIPS_CP0_TLB_LO_0 2 /* TLB Entry Lo0 */
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#define MIPS_CP0_TLB_LO_1 3 /* TLB Entry Lo1 */
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#define MIPS_CP0_CONTEXT 4 /* Kernel PTE pointer */
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#define MIPS_CP0_PAGEMASK 5 /* TLB Page Mask */
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#define MIPS_CP0_WIRED 6 /* TLB Wired */
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#define MIPS_CP0_INFO 7 /* Info (RM7000) */
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#define MIPS_CP0_BADVADDR 8 /* Bad Virtual Address */
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#define MIPS_CP0_COUNT 9 /* Count */
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#define MIPS_CP0_TLB_HI 10 /* TLB Entry Hi */
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#define MIPS_CP0_COMPARE 11 /* Timer Compare */
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#define MIPS_CP0_STATUS 12 /* Status */
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#define MIPS_CP0_CAUSE 13 /* Cause */
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#define MIPS_CP0_EPC 14 /* Exception PC */
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#define MIPS_CP0_PRID 15 /* Proc Rev ID */
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#define MIPS_CP0_CONFIG 16 /* Configuration */
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#define MIPS_CP0_LLADDR 17 /* Load/Link address */
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#define MIPS_CP0_WATCHLO 18 /* Low Watch address */
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#define MIPS_CP0_WATCHHI 19 /* High Watch address */
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#define MIPS_CP0_XCONTEXT 20 /* Extended context */
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#define MIPS_CP0_DEBUG 23 /* Debug */
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#define MIPS_CP0_DEPC 24 /* DEPC */
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#define MIPS_CP0_ECC 26 /* ECC and parity */
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#define MIPS_CP0_CACHERR 27 /* Cache Err/Status */
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#define MIPS_CP0_TAGLO 28 /* Cache Tag Lo */
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#define MIPS_CP0_TAGHI 29 /* Cache Tag Hi */
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#define MIPS_CP0_ERR_EPC 30 /* Error exception PC */
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/*
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* CP0 Status Register
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*/
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#define MIPS_CP0_STATUS_CU0 0x10000000
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#define MIPS_CP0_STATUS_CU1 0x20000000
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#define MIPS_CP0_STATUS_CU2 0x40000000
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#define MIPS_CP0_STATUS_BEV 0x00400000
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#define MIPS_CP0_STATUS_TS 0x00200000
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#define MIPS_CP0_STATUS_SR 0x00100000
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#define MIPS_CP0_STATUS_CH 0x00040000
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#define MIPS_CP0_STATUS_CE 0x00020000
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#define MIPS_CP0_STATUS_DE 0x00010000
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#define MIPS_CP0_STATUS_RP 0x08000000
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#define MIPS_CP0_STATUS_FR 0x04000000
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#define MIPS_CP0_STATUS_RE 0x02000000
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#define MIPS_CP0_STATUS_KX 0x00000080
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#define MIPS_CP0_STATUS_SX 0x00000040
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#define MIPS_CP0_STATUS_UX 0x00000020
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#define MIPS_CP0_STATUS_KSU 0x00000018
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#define MIPS_CP0_STATUS_ERL 0x00000004
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#define MIPS_CP0_STATUS_EXL 0x00000002
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#define MIPS_CP0_STATUS_IE 0x00000001
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#define MIPS_CP0_STATUS_IMASK7 0x00008000
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#define MIPS_CP0_STATUS_IMASK6 0x00004000
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#define MIPS_CP0_STATUS_IMASK5 0x00002000
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#define MIPS_CP0_STATUS_IMASK4 0x00001000
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#define MIPS_CP0_STATUS_IMASK3 0x00000800
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#define MIPS_CP0_STATUS_IMASK2 0x00000400
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#define MIPS_CP0_STATUS_IMASK1 0x00000200
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#define MIPS_CP0_STATUS_IMASK0 0x00000100
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#define MIPS_CP0_STATUS_DS_MASK 0x00770000
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#define MIPS_CP0_STATUS_CU_MASK 0xF0000000
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#define MIPS_CP0_STATUS_IMASK 0x0000FF00
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/* Addressing mode: Kernel, Supervisor and User */
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#define MIPS_CP0_STATUS_KSU_SHIFT 0x03
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#define MIPS_CP0_STATUS_KSU_MASK 0x03
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#define MIPS_CP0_STATUS_KM 0x00
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#define MIPS_CP0_STATUS_SM 0x01
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#define MIPS_CP0_STATUS_UM 0x10
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/*
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* CP0 Cause register
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*/
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#define MIPS_CP0_CAUSE_BD_SLOT 0x80000000
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#define MIPS_CP0_CAUSE_MASK 0x0000007C
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#define MIPS_CP0_CAUSE_CEMASK 0x30000000
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#define MIPS_CP0_CAUSE_CESHIFT 28
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#ifdef SIM_PIC32
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#define MIPS_CP0_CAUSE_IMASK 0x0000FC00 /* mips r2 */
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#else
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#define MIPS_CP0_CAUSE_IMASK 0x0000FF00 /* mips r1 */
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#endif
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#define MIPS_CP0_CAUSE_IV 0x00800000
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#define MIPS_CP0_CAUSE_SHIFT 2
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#define MIPS_CP0_CAUSE_CESHIFT 28
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#define MIPS_CP0_CAUSE_ISHIFT 8
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#define MIPS_CP0_CAUSE_EXC_MASK 0x0000007C
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#define MIPS_CP0_CAUSE_INTERRUPT 0
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#define MIPS_CP0_CAUSE_TLB_MOD 1
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#define MIPS_CP0_CAUSE_TLB_LOAD 2
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#define MIPS_CP0_CAUSE_TLB_SAVE 3
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#define MIPS_CP0_CAUSE_ADDR_LOAD 4 /* ADEL */
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#define MIPS_CP0_CAUSE_ADDR_SAVE 5 /* ADES */
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#define MIPS_CP0_CAUSE_BUS_INSTR 6
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#define MIPS_CP0_CAUSE_BUS_DATA 7
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#define MIPS_CP0_CAUSE_SYSCALL 8
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#define MIPS_CP0_CAUSE_BP 9
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#define MIPS_CP0_CAUSE_ILLOP 10
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#define MIPS_CP0_CAUSE_CP_UNUSABLE 11
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#define MIPS_CP0_CAUSE_OVFLW 12
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#define MIPS_CP0_CAUSE_TRAP 13
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#define MIPS_CP0_CAUSE_FPE 15
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#define MIPS_CP0_CAUSE_WATCH 23
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#define MIPS_CP0_CAUSE_IBIT7 0x00008000
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#define MIPS_CP0_CAUSE_IBIT6 0x00004000
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#define MIPS_CP0_CAUSE_IBIT5 0x00002000
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#define MIPS_CP0_CAUSE_IBIT4 0x00001000
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#define MIPS_CP0_CAUSE_IBIT3 0x00000800
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#define MIPS_CP0_CAUSE_IBIT2 0x00000400
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#define MIPS_CP0_CAUSE_IBIT1 0x00000200
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#define MIPS_CP0_CAUSE_IBIT0 0x00000100
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/* cp0 context */
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#define MIPS_CP0_CONTEXT_PTEBASE_MASK 0xff800000
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#define MIPS_CP0_CONTEXT_BADVPN2_MASK 0x0007ffff0
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/*
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* CP0 Debug register
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*/
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#define MIPS_CP0_DEBUG_DBD 0x80000000 /* Debug exception on delay slot */
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#define MIPS_CP0_DEBUG_DM 0x40000000 /* Debug mode */
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#define MIPS_CP0_DEBUG_IEXI 0x00100000 /* Imprecise Error eXception Inhibit */
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#define MIPS_CP0_DEBUG_DDBSIMPR 0x00080000 /* Debug Data Break Store Impresize exception */
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#define MIPS_CP0_DEBUG_DDBLIMPR 0x00040000 /* Debug Data Break Load Impresize exception */
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#define MIPS_CP0_DEBUG_DEXCCODE 0x00003c00 /* Debug exception code */
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#define MIPS_CP0_DEBUG_DEXCCODE_SHIFT 10
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#define MIPS_CP0_DEBUG_DINT 0x00000020 /* Debug Interrupt exception */
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#define MIPS_CP0_DEBUG_DIB 0x00000010 /* Debug Instruction Break exception */
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#define MIPS_CP0_DEBUG_DDBS 0x00000008 /* Debug Data Break Store exception */
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#define MIPS_CP0_DEBUG_DDBL 0x00000004 /* Debug Data Break Load exception */
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#define MIPS_CP0_DEBUG_DBP 0x00000002 /* Debug Breakpoint exception */
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#define MIPS_CP0_DEBUG_DSS 0x00000001 /* Debug Single Step exception */
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#define MIPS_CP0_DEBUG_WMASK 0x10700180 /* Writable bits */
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/* TLB masks and shifts */
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#define MIPS_TLB_PAGE_MASK 0x01ffe000
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#define MIPS_TLB_PAGE_SHIFT 13
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//#define MIPS_TLB_VPN2_MASK 0xffffe000
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#define MIPS_TLB_VPN2_MASK_32 0xffffe000
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#define MIPS_TLB_VPN2_MASK_64 0xc00000ffffffe000ULL
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#define MIPS_TLB_PFN_MASK 0x3fffffc0
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#define MIPS_TLB_ASID_MASK 0x000000ff /* "asid" in EntryHi */
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#define MIPS_TLB_G_MASK 0x00001000 /* "Global" in EntryHi */
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#define MIPS_TLB_V_MASK 0x2 /* "Valid" in EntryLo */
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#define MIPS_TLB_D_MASK 0x4 /* "Dirty" in EntryLo */
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#define MIPS_TLB_C_MASK 0x38 /* Page Coherency Attribute */
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#define MIPS_TLB_C_SHIFT 3
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#define MIPS_TLB_V_SHIT 1
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#define MIPS_TLB_D_SHIT 2
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#define MIPS_CP0_LO_G_MASK 0x00000001 /* "Global" in Lo0/1 reg */
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#define MIPS_CP0_HI_SAFE_MASK 0xffffe0ff /* Safety mask for Hi reg */
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#define MIPS_CP0_LO_SAFE_MASK 0x7fffffff /* Safety mask for Lo reg */
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/* MIPS "jr ra" instruction */
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#define MIPS_INSN_JR_RA 0x03e00008
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#ifdef SIM_PIC32
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#define MIPS_MIN_PAGE_SHIFT 8
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#define MIPS_MIN_PAGE_SIZE (1 << MIPS_MIN_PAGE_SHIFT)
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#define MIPS_MIN_PAGE_IMASK (MIPS_MIN_PAGE_SIZE - 1)
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#define MIPS_MIN_PAGE_MASK 0xffffffffffffff00ULL
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#else
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/* Minimum page size: 4 Kb */
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#define MIPS_MIN_PAGE_SHIFT 12
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#define MIPS_MIN_PAGE_SIZE (1 << MIPS_MIN_PAGE_SHIFT)
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#define MIPS_MIN_PAGE_IMASK (MIPS_MIN_PAGE_SIZE - 1)
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#define MIPS_MIN_PAGE_MASK 0xfffffffffffff000ULL
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#endif
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/* Addressing mode: Kernel, Supervisor and User */
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#define MIPS_MODE_KERNEL 00
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/* Segments in 32-bit User mode */
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#define MIPS_USEG_BASE 0x00000000
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#define MIPS_USEG_SIZE 0x80000000
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/* Segments in 32-bit Supervisor mode */
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#define MIPS_SUSEG_BASE 0x00000000
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#define MIPS_SUSEG_SIZE 0x80000000
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#define MIPS_SSEG_BASE 0xc0000000
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#define MIPS_SSEG_SIZE 0x20000000
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/* Segments in 32-bit Kernel mode */
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#define MIPS_KUSEG_BASE 0x00000000
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#define MIPS_KUSEG_SIZE 0x80000000
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#define MIPS_KSEG0_BASE 0x80000000
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#define MIPS_KSEG0_SIZE 0x20000000
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#define MIPS_KSEG1_BASE 0xa0000000
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#define MIPS_KSEG1_SIZE 0x20000000
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#define MIPS_KSSEG_BASE 0xc0000000
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#define MIPS_KSSEG_SIZE 0x20000000
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#define MIPS_KSEG3_BASE 0xe0000000
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#define MIPS_KSEG3_SIZE 0x20000000
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/* xkphys mask (36-bit physical address) */
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#define MIPS64_XKPHYS_ZONE_MASK 0xF800000000000000ULL
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#define MIPS64_XKPHYS_PHYS_SIZE (1ULL << 36)
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#define MIPS64_XKPHYS_PHYS_MASK (MIPS64_XKPHYS_PHYS_SIZE - 1)
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#define MIPS64_XKPHYS_CCA_SHIFT 59
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/* Number of GPR (general purpose registers) */
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#define MIPS64_GPR_NR 32
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/* Number of registers in CP0 */
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#define MIPS64_CP0_REG_NR 32
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/*8 configure register in cp0. sel:0-7*/
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#define MIPS64_CP0_CONFIG_REG_NR 8
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/* Number of registers in CP1 */
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#define MIPS64_CP1_REG_NR 32
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/* Number of TLB entries */
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#define MIPS64_TLB_STD_ENTRIES 48
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#define MIPS64_TLB_MAX_ENTRIES 64
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#define MIPS64_TLB_IDX_MASK 0x3f /* 6 bits */
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/* Enable the 64 TLB entries for R7000 CPU */
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#define MIPS64_R7000_TLB64_ENABLE 0x20000000
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/* Number of instructions per page */
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#define MIPS_INSN_PER_PAGE (MIPS_MIN_PAGE_SIZE/sizeof(mips_insn_t))
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/* MIPS CPU Identifiers */
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#define MIPS_PRID_R4600 0x00002012
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#define MIPS_PRID_R4700 0x00002112
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#define MIPS_PRID_R5000 0x00002312
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#define MIPS_PRID_R7000 0x00002721
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#define MIPS_PRID_R527x 0x00002812
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#define MIPS_PRID_BCM1250 0x00040102
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enum {
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MIPS_KUSEG = 0,
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MIPS_KSEG0,
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MIPS_KSEG1,
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MIPS_KSEG2,
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};
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/* Memory operations */
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enum {
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MIPS_MEMOP_LOOKUP = 0,
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MIPS_MEMOP_LB,
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MIPS_MEMOP_LBU,
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MIPS_MEMOP_LH,
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MIPS_MEMOP_LHU,
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MIPS_MEMOP_LW,
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MIPS_MEMOP_LWU,
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MIPS_MEMOP_LD,
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MIPS_MEMOP_SB,
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MIPS_MEMOP_SH,
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MIPS_MEMOP_SW,
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MIPS_MEMOP_SD,
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MIPS_MEMOP_LWL,
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MIPS_MEMOP_LWR,
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MIPS_MEMOP_LDL,
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MIPS_MEMOP_LDR,
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MIPS_MEMOP_SWL,
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MIPS_MEMOP_SWR,
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MIPS_MEMOP_SDL,
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MIPS_MEMOP_SDR,
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MIPS_MEMOP_LL,
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MIPS_MEMOP_SC,
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MIPS_MEMOP_LDC1,
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MIPS_MEMOP_SDC1,
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MIPS_MEMOP_CACHE,
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MIPS_MEMOP_MAX,
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};
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/* Maximum number of breakpoints */
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#define MIPS64_MAX_BREAKPOINTS 8
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#define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */
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#define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
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#define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
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#define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */
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#define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */
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#define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */
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#define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */
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/* MIPS CPU type */
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//typedef struct cpu_mips cpu_mips_t;
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/* Memory operation function prototype */
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typedef u_int fastcall (*mips_memop_fn) (cpu_mips_t * cpu, m_va_t vaddr,
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u_int reg);
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/* TLB entry definition */
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typedef struct {
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m_va_t mask;
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m_va_t hi;
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m_va_t lo0;
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m_va_t lo1;
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} tlb_entry_t;
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/* System Coprocessor (CP0) definition */
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typedef struct {
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m_cp0_reg_t reg[MIPS64_CP0_REG_NR];
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/*because configure has sel 0-7, seperate it to reg */
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m_cp0_reg_t config_reg[MIPS64_CP0_CONFIG_REG_NR];
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m_cp0_reg_t intctl_reg;
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m_cp0_reg_t ebase_reg;
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m_uint8_t config_usable; /*if configure register sel N is useable, set the bit in config_usable to 1 */
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tlb_entry_t tlb[MIPS64_TLB_MAX_ENTRIES];
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/* Number of TLB entries */
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u_int tlb_entries;
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} mips_cp0_t;
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/* mips CPU definition */
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struct cpu_mips {
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/* CPU identifier for MP systems */
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u_int id;
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u_int type;
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m_va_t pc, ret_pc;
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m_va_t jit_pc;
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m_reg_t gpr[MIPS64_GPR_NR];
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m_reg_t lo, hi;
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/* VM instance */
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vm_instance_t *vm;
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/* Next CPU in group */
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cpu_mips_t *next;
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/* System coprocessor (CP0) */
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mips_cp0_t cp0;
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/* CPU states */
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volatile m_uint32_t state, prev_state;
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/* Thread running this CPU */
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pthread_t cpu_thread;
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int cpu_thread_running;
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/*pause request. INTERRUPT will pause cpu */
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m_uint32_t pause_request;
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/* Methods */
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int (*reg_get) (cpu_mips_t * cpu, u_int reg, m_reg_t * val);
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void (*reg_set) (cpu_mips_t * cpu, u_int reg_index, m_reg_t val);
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void (*mts_rebuild) (cpu_mips_t * cpu);
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u_int (*mips_mts_gdb_lb) (cpu_mips_t * cpu, m_va_t vaddr, void *cur);
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/* MTS32/MTS64 caches */
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union {
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mts32_entry_t *mts32_cache;
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mts64_entry_t *mts64_cache;
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} mts_u;
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/* General Purpose Registers, Pointer Counter, LO/HI, IRQ */
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m_uint32_t irq_pending, irq_cause, ll_bit;
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/* Virtual address to physical page translation */
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int (*translate) (cpu_mips_t * cpu, m_va_t vaddr, m_uint32_t * phys_page);
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/* Memory access functions */
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mips_memop_fn mem_op_fn[MIPS_MEMOP_MAX];
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/* Memory lookup function (to load ELF image,...) */
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void *fastcall (*mem_op_lookup) (cpu_mips_t * cpu, m_va_t vaddr);
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|
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/* Address bus mask for physical addresses */
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m_va_t addr_bus_mask;
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|
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/* MTS map/unmap/rebuild operations */
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void (*mts_map) (cpu_mips_t * cpu, m_va_t vaddr, m_pa_t paddr,
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m_uint32_t len, int cache_access, int tlb_index);
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void (*mts_unmap) (cpu_mips_t * cpu, m_va_t vaddr, m_uint32_t len,
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m_uint32_t val, int tlb_index);
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void (*mts_shutdown) (cpu_mips_t * cpu);
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/* MTS cache statistics */
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m_uint64_t mts_misses, mts_lookups;
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|
|
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/* Address mode (32 or 64 bits) */
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u_int addr_mode;
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|
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int is_in_bdslot;
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int insn_len; /* length of last fetched instruction in bytes */
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int is_mips16e; /* 1 if ISA Mode is MIPS16e, 0 if MIPS32 */
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|
|
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int trace_syscall;
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int magic_opcodes;
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|
|
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/* Current exec page (non-JIT) info */
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|
m_va_t njm_exec_page;
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mips_insn_t *njm_exec_ptr;
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|
|
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#ifdef _USE_JIT_
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/* JIT flush method */
|
|
u_int jit_flush_method;
|
|
|
|
/* Number of compiled pages */
|
|
u_int compiled_pages;
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|
|
|
/* Code page translation cache */
|
|
mips_jit_tcb_t **exec_blk_map;
|
|
void *exec_page_area;
|
|
size_t exec_page_area_size; /*M bytes */
|
|
size_t exec_page_count, exec_page_alloc;
|
|
insn_exec_page_t *exec_page_free_list;
|
|
insn_exec_page_t *exec_page_array;
|
|
/* Current and free lists of translated code blocks */
|
|
mips_jit_tcb_t *tcb_list, *tcb_last, *tcb_free_list;
|
|
/* Direct block jump.Optimization */
|
|
u_int exec_blk_direct_jump;
|
|
|
|
#endif
|
|
|
|
};
|
|
|
|
/* Register names */
|
|
extern char *mips_gpr_reg_names[];
|
|
|
|
#define MAJOR_OP(_inst) (((uint)_inst >> 26) & 0x3f )
|
|
|
|
int mips_load_elf_image (cpu_mips_t * cpu, char *filename,
|
|
m_va_t * entry_point);
|
|
|
|
int mips_get_reg_index (char *name);
|
|
int mips_cca_cached (m_uint8_t val);
|
|
void mips_dump_regs (cpu_mips_t * cpu);
|
|
void mips_delete (cpu_mips_t * cpu);
|
|
int mips_reset (cpu_mips_t * cpu);
|
|
int mips_init (cpu_mips_t * cpu);
|
|
int mips_load_elf_image (cpu_mips_t * cpu, char *filename,
|
|
m_va_t * entry_point);
|
|
void mips_delete (cpu_mips_t * cpu);
|
|
int fastcall mips_update_irq_flag (cpu_mips_t * cpu);
|
|
void mips_trigger_exception (cpu_mips_t * cpu, u_int exc_code, int bd_slot);
|
|
void mips_trigger_debug_exception (cpu_mips_t * cpu, u_int dexc_type);
|
|
void fastcall mips_exec_soft_fpu (cpu_mips_t * cpu);
|
|
void fastcall mips_exec_eret (cpu_mips_t * cpu);
|
|
void fastcall mips_exec_deret (cpu_mips_t * cpu);
|
|
void fastcall mips_exec_break (cpu_mips_t * cpu, u_int code);
|
|
void fastcall mips_trigger_trap_exception (cpu_mips_t * cpu);
|
|
void fastcall mips_exec_syscall (cpu_mips_t * cpu);
|
|
void fastcall mips_trigger_irq (cpu_mips_t * cpu);
|
|
void mips_set_irq (cpu_mips_t * cpu, m_uint8_t irq);
|
|
void mips_clear_irq (cpu_mips_t * cpu, m_uint8_t irq);
|
|
|
|
/* Control timer interrupt */
|
|
void set_timer_irq (cpu_mips_t *cpu);
|
|
void clear_timer_irq (cpu_mips_t *cpu);
|
|
|
|
/*
|
|
* Disassemble and print the instruction mnemonics.
|
|
* Opcode size can be 4 or 2 bytes.
|
|
* Parameter `isa' defines an instruction set architecture:
|
|
* 0 - mips32 encoding
|
|
* 1 - mips16e encoding
|
|
* 2 - micromips encoding (someday)
|
|
*/
|
|
void print_mips (unsigned memaddr, unsigned int opcode, int nbytes,
|
|
int isa, FILE *stream);
|
|
|
|
const char *cp0reg_name (unsigned cp0reg, unsigned sel);
|
|
|
|
int mips_fetch_instruction (cpu_mips_t * cpu,
|
|
m_va_t pc, mips_insn_t * insn);
|
|
void *mips_mts32_access (cpu_mips_t * cpu, m_va_t vaddr,
|
|
u_int op_code, u_int op_size,
|
|
u_int op_type, m_reg_t * data, u_int * exc, m_uint8_t * has_set_value,
|
|
u_int is_fromgdb);
|
|
|
|
#endif
|