228 lines
6.9 KiB
C
228 lines
6.9 KiB
C
/*
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* SPI emulation for PIC32.
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* Two SD/MMC disks attached to SPI1.
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*
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* Copyright (C) 2011 Serge Vakulenko <serge@vak.ru>
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*
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* This file is part of the virtualmips distribution.
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* See LICENSE file for terms of the license.
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*/
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#define _GNU_SOURCE
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#include <stdlib.h>
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#include <stdio.h>
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#include <assert.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <string.h>
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#include "device.h"
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#include "mips_memory.h"
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#include "pic32.h"
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#include "cpu.h"
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#include "vp_timer.h"
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#include "dev_sdcard.h"
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#define SPI_REG_SIZE 0x40
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struct pic32_spi_data {
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struct vdevice *dev;
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vm_instance_t *vm;
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pic32_t *pic32;
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u_int irq; /* base irq number */
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#define IRQ_FAULT 0 /* error interrupt */
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#define IRQ_TX 1 /* transmitter interrupt */
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#define IRQ_RX 2 /* receiver interrupt */
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unsigned con; /* 0x00 - Control */
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unsigned stat; /* 0x10 - Status */
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unsigned buf [4]; /* 0x20 - Transmit and receive buffer */
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unsigned brg; /* 0x40 - Baud rate generator */
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unsigned rfifo; /* read fifo counter */
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unsigned wfifo; /* write fifo counter */
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};
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extern cpu_mips_t *current_cpu;
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/*
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* Perform an assign/clear/set/invert operation.
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*/
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static inline unsigned write_op (int a, int b, int op)
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{
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switch (op & 0xc) {
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case 0x0: /* Assign */
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a = b;
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break;
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case 0x4: /* Clear */
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a &= ~b;
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break;
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case 0x8: /* Set */
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a |= b;
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break;
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case 0xc: /* Invert */
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a ^= b;
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break;
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}
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return a;
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}
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void *dev_pic32_spi_access (cpu_mips_t * cpu, struct vdevice *dev,
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m_uint32_t offset, u_int op_size, u_int op_type,
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m_reg_t * data, m_uint8_t * has_set_value)
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{
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struct pic32_spi_data *d = dev->priv_data;
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unsigned newval;
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if (offset >= SPI_REG_SIZE) {
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*data = 0;
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return NULL;
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}
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if (op_type == MTS_READ)
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*data = 0;
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switch (offset & 0x1f0) {
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case PIC32_SPI1CON & 0x1f0: /* SPIx Control */
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if (op_type == MTS_READ) {
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*data = d->con;
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} else {
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d->con = write_op (d->con, *data, offset);
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if (! (d->con & PIC32_SPICON_ON)) {
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d->vm->clear_irq (d->vm, d->irq + IRQ_FAULT);
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d->vm->clear_irq (d->vm, d->irq + IRQ_RX);
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d->vm->clear_irq (d->vm, d->irq + IRQ_TX);
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d->stat = PIC32_SPISTAT_SPITBE;
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} else if (! (d->con & PIC32_SPICON_ENHBUF)) {
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d->rfifo = 0;
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d->wfifo = 0;
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}
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}
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break;
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case PIC32_SPI1STAT & 0x1f0: /* SPIx Status */
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if (op_type == MTS_READ) {
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*data = d->stat;
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} else {
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/* Only ROV bit is writable. */
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newval = write_op (d->stat, *data, offset);
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d->stat = (d->stat & ~PIC32_SPISTAT_SPIROV) |
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(newval & PIC32_SPISTAT_SPIROV);
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}
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break;
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case PIC32_SPI1BUF & 0x1ff: /* SPIx SPIx Buffer */
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if (op_type == MTS_READ) {
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*data = d->buf [d->rfifo];
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if (d->con & PIC32_SPICON_ENHBUF) {
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d->rfifo++;
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d->rfifo &= 3;
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}
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if (d->stat & PIC32_SPISTAT_SPIRBF) {
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d->stat &= ~PIC32_SPISTAT_SPIRBF;
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//d->vm->clear_irq (d->vm, d->irq + IRQ_RX);
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}
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} else {
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unsigned sdcard_port = d->pic32->sdcard_port;
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/* Perform SD card i/o on configured SPI port. */
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if ((dev->phys_addr == PIC32_SPI1CON && sdcard_port == 1) ||
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(dev->phys_addr == PIC32_SPI2CON && sdcard_port == 2) ||
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(dev->phys_addr == PIC32_SPI3CON && sdcard_port == 3) ||
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(dev->phys_addr == PIC32_SPI4CON && sdcard_port == 4))
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{
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unsigned val = *data;
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if (d->con & PIC32_SPICON_MODE32) {
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/* 32-bit data width */
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d->buf [d->wfifo] = (unsigned char) dev_sdcard_io (cpu, val >> 24) << 24;
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d->buf [d->wfifo] |= (unsigned char) dev_sdcard_io (cpu, val >> 16) << 16;
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d->buf [d->wfifo] |= (unsigned char) dev_sdcard_io (cpu, val >> 8) << 8;
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d->buf [d->wfifo] |= (unsigned char) dev_sdcard_io (cpu, val);
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} else if (d->con & PIC32_SPICON_MODE16) {
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/* 16-bit data width */
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d->buf [d->wfifo] = (unsigned char) dev_sdcard_io (cpu, val >> 8) << 8;
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d->buf [d->wfifo] |= (unsigned char) dev_sdcard_io (cpu, val);
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} else {
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/* 8-bit data width */
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d->buf [d->wfifo] = (unsigned char) dev_sdcard_io (cpu, val);
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}
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} else {
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/* No device */
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d->buf [d->wfifo] = ~0;
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}
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if (d->stat & PIC32_SPISTAT_SPIRBF) {
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d->stat |= PIC32_SPISTAT_SPIROV;
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//d->vm->set_irq (d->vm, d->irq + IRQ_FAULT);
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} else if (d->con & PIC32_SPICON_ENHBUF) {
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d->wfifo++;
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d->wfifo &= 3;
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if (d->wfifo == d->rfifo) {
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d->stat |= PIC32_SPISTAT_SPIRBF;
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//d->vm->set_irq (d->vm, d->irq + IRQ_RX);
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}
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} else {
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d->stat |= PIC32_SPISTAT_SPIRBF;
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//d->vm->set_irq (d->vm, d->irq + IRQ_RX);
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}
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}
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break;
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case PIC32_SPI1BRG & 0x1f0: /* SPIx Baud rate */
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if (op_type == MTS_READ) {
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*data = d->brg;
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} else {
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d->brg = write_op (d->brg, *data, offset);
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}
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break;
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default:
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ASSERT (0, "unknown spi offset %x\n", offset);
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}
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*has_set_value = TRUE;
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return NULL;
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}
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void dev_pic32_spi_reset (cpu_mips_t *cpu, struct vdevice *dev)
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{
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struct pic32_spi_data *d = dev->priv_data;
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d->con = 0;
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d->stat = PIC32_SPISTAT_SPITBE; /* Transmit buffer is empty */
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d->wfifo = 0;
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d->rfifo = 0;
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d->brg = 0;
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}
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int dev_pic32_spi_init (vm_instance_t *vm, char *name, unsigned paddr,
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unsigned irq)
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{
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struct pic32_spi_data *d;
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pic32_t *pic32 = (pic32_t *) vm->hw_data;
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/* allocate the private data structure */
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d = malloc (sizeof (*d));
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if (!d) {
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fprintf (stderr, "PIC32 SPI: unable to create device.\n");
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return (-1);
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}
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memset (d, 0, sizeof (*d));
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d->dev = dev_create (name);
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if (! d->dev) {
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free (d);
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return (-1);
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}
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d->dev->priv_data = d;
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d->dev->phys_addr = paddr;
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d->dev->phys_len = SPI_REG_SIZE;
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d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;
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d->vm = vm;
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d->irq = irq;
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d->pic32 = pic32;
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d->dev->handler = dev_pic32_spi_access;
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d->dev->reset_handler = dev_pic32_spi_reset;
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vm_bind_device (vm, d->dev);
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return (0);
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}
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