5cb608d7e1
Delete device names from all the drivers. Move device inslude files from include/sys to include/machine directory. Only include files which have something useful for user layer (like special ioctls codes) should be placed into sys.
183 lines
4.2 KiB
C
183 lines
4.2 KiB
C
#ifndef RD_SDRAMP_CONFIG_H_
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#include "pic32mx.h"
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/* TODO: better support for different sized sdram chips, 16 bit support */
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/*
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* Number of physical address lines on sdram chip
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* one of 11, 12, 13
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*/
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#define SDR_ADDRESS_LINES 12
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/*
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* Ram data width in bytes - 1 (8 bit) or 2 (16 bit)
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*
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* NOT USED YET
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*/
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#define SDR_DATA_BYTES 2
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/*
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* Upper/Lower Byte selection
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*/
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#define SDR_DQM_PORT TRISA
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#if SDR_DATA_BYTES == 2
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#define SDR_DQM_UDQM_BIT 6
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#endif
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#define SDR_DQM_LDQM_BIT 7
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/*
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* Bank Selection
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* BA0 is connected to SDR_BANK_0_BIT
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* BA1 is connected to SDR_BANK_0_BIT + 1
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*
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* So, if SDR_BANK_0_BIT is 4, then bit 5
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* must be connected to BA1.
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*/
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#define SDR_BANK_PORT TRISG
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#define SDR_BANK_0_BIT 0
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/*
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* Clock Enable
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*
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* Connect to CKE on sdram
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*/
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#define SDR_CKE_PORT TRISD
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#define SDR_CKE_BIT 11
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/*
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* Control Lines
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*
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* Connect to /WE, /CAS, /CS and /RAS pins on sdram
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*/
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#define SDR_CONTROL_PORT TRISG
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#define SDR_CONTROL_WE_BIT 15
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#define SDR_CONTROL_CAS_BIT 13
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#define SDR_CONTROL_CS_BIT 14
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#define SDR_CONTROL_RAS_BIT 12
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/*
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* Address Lines
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*
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* At present, the port can be changed, but
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* changing the address line bits is unsupported.
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*/
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#define SDR_ADDRESS_LB_PORT TRISF
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#define SDR_ADDRESS_PORT TRISD
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/***** WARNING - DO NOT CHANGE WITHOUT ALSO CHANGING CODE TO MATCH *****/
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#define SDR_ADDRESS_LB_A0_BIT 0
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#define SDR_ADDRESS_LB_A1_BIT 1
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#define SDR_ADDRESS_LB_A2_BIT 2
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#define SDR_ADDRESS_A3_BIT 1
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#define SDR_ADDRESS_A4_BIT 2
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#define SDR_ADDRESS_A5_BIT 3
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#define SDR_ADDRESS_A6_BIT 4
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#define SDR_ADDRESS_A7_BIT 5
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#define SDR_ADDRESS_A8_BIT 6
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#define SDR_ADDRESS_A9_BIT 7
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#if SDR_ADDRESS_LINES >= 11
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#define SDR_ADDRESS_A10_BIT 8
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#endif
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#if SDR_ADDRESS_LINES >= 12
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#define SDR_ADDRESS_A11_BIT 9
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#endif
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#if SDR_ADDRESS_LINES >= 13
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#define SDR_ADDRESS_A12_BIT 10
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#endif
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/***** END WARNING *****/
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/*
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* Data Lines
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*
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* The low 8 bits (bits 0-7) must be used
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* and connected to the data lines on the sdram.
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* The specific order in which the 8 pins are
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* connected to the data pins of the sdram is
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* not significant, unless you wish for a neat
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* and tidy design that is easy connect to a
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* logic analyzer for debugging purposes.
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*/
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#define SDR_DATA_PORT TRISE
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/*
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* Output Compare
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*
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* Currently supporting OC1CON or OC4CON
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* Timer2 is used in all cases.
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* The appropriate pin should be connected to CLK on the sdram.
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* OC1CON - RD0
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* OC4CON - RD3
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*/
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#define SDR_OCR OC1CON
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/*
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* Additional sdram connections
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*
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* Power and ground as appropriate.
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*/
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/***************************************************************/
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/*
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* Anthing following should not normally need to be modified.
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* There are here in order to share definitions between C and ASM.
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*/
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#ifdef SDR_ADDRESS_A10_BIT
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#define SDR_ADDRESS_A10_BITMASK (1<<SDR_ADDRESS_A10_BIT)
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#else
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#define SDR_ADDRESS_A10_BITMASK 0
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#endif
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#ifdef SDR_ADDRESS_A11_BIT
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#define SDR_ADDRESS_A11_BITMASK (1<<SDR_ADDRESS_A11_BIT)
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#else
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#define SDR_ADDRESS_A11_BITMASK 0
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#endif
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#ifdef SDR_ADDRESS_A12_BIT
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#define SDR_ADDRESS_A12_BITMASK (1<<SDR_ADDRESS_A12_BIT)
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#else
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#define SDR_ADDRESS_A12_BITMASK 0
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#endif
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#define ADDRESS_LB_MASK \
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((1<<SDR_ADDRESS_LB_A0_BIT)|(1<<SDR_ADDRESS_LB_A1_BIT)|(1<<SDR_ADDRESS_LB_A2_BIT))
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#define ADDRESS_MASK \
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((1<<SDR_ADDRESS_A3_BIT)|(1<<SDR_ADDRESS_A4_BIT)|(1<<SDR_ADDRESS_A5_BIT)| \
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(1<<SDR_ADDRESS_A6_BIT)|(1<<SDR_ADDRESS_A7_BIT)|(1<<SDR_ADDRESS_A8_BIT)| \
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(1<<SDR_ADDRESS_A9_BIT)| \
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SDR_ADDRESS_A10_BITMASK| \
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SDR_ADDRESS_A11_BITMASK| \
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SDR_ADDRESS_A12_BITMASK)
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#define CONTROL_ALL_MASK \
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((1<<SDR_CONTROL_CS_BIT)|(1<<SDR_CONTROL_RAS_BIT)| \
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(1<<SDR_CONTROL_CAS_BIT)|(1<<SDR_CONTROL_WE_BIT))
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#define BANK_BITMASK 3
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#define BANK_ALL_MASK (BANK_BITMASK << SDR_BANK_0_BIT)
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#ifdef SDR_DQM_UDQM_BIT
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#define SDR_DQM_MASK \
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((1<<SDR_DQM_LDQM_BIT)|(1<<SDR_DQM_UDQM_BIT))
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#else
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#define SDR_DQM_MASK \
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(1<<SDR_DQM_LDQM_BIT)
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#endif
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#endif
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