112 lines
3.0 KiB
C
112 lines
3.0 KiB
C
/*
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* Cisco router simulation platform.
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* Copyright (c) 2006 Christophe Fillot (cf@utc.fr)
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*/
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/*
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* Copyright (C) yajin 2008 <yajinzhou@gmail.com >
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*
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* This file is part of the virtualmips distribution.
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* See LICENSE file for terms of the license.
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*
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*/
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#ifndef __MIPS64_MEM_H__
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#define __MIPS64_MEM_H__
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#include <sys/types.h>
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#include "utils.h"
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#include "system.h"
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/* MTS operation */
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#define MTS_READ 0
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#define MTS_WRITE 1
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#define MTS_BYTE 1
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#define MTS_HALF_WORD 2
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#define MTS_WORD 4
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/* 0.5GB value */
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#define MTS_SIZE_512M 0x20000000
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/* MTS flag bits: D (device), ACC (memory access), C (chain) */
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#define MTS_FLAG_BITS 4
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#define MTS_FLAG_MASK 0x0000000fUL
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/* Masks for MTS entries */
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#define MTS_CHAIN_MASK 0x00000001
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#define MTS_ACC_MASK 0x00000006
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#define MTS_DEV_MASK 0x00000008
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#define MTS_ADDR_MASK (~MTS_FLAG_MASK)
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/* Device ID mask and shift, device offset mask */
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#define MTS_DEVID_MASK 0xfc000000
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#define MTS_DEVID_SHIFT 26
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#define MTS_DEVOFF_MASK 0x03fffff0
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/* Memory access flags */
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#define MTS_ACC_OK 0x00000000 /* Access OK */
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#define MTS_ACC_AE 0x00000002 /* Address Error */
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#define MTS_ACC_T 0x00000004 /* TLB Exception */
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#define MTS_ACC_U 0x00000006 /* Unexistent */
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#define MTS_ACC_M 0x00000008 /* TLB MODE */
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/* Hash table size for MTS64 (default: [shift:16,bits:12]) */
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#define MTS64_HASH_SHIFT 12
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#define MTS64_HASH_BITS 14
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#define MTS64_HASH_SIZE (1 << MTS64_HASH_BITS)
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#define MTS64_HASH_MASK (MTS64_HASH_SIZE - 1)
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/* MTS64 hash on virtual addresses */
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#define MTS64_HASH(vaddr) (((vaddr) >> MTS64_HASH_SHIFT) & MTS64_HASH_MASK)
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/* Hash table size for MTS32 (default: [shift:15,bits:15]) */
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#define MTS32_HASH_SHIFT 12
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#define MTS32_HASH_BITS 14
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#define MTS32_HASH_SIZE (1 << MTS32_HASH_BITS)
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#define MTS32_HASH_MASK (MTS32_HASH_SIZE - 1)
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/* MTS32 hash on virtual addresses */
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#define MTS32_HASH(vaddr) (((vaddr) >> MTS32_HASH_SHIFT) & MTS32_HASH_MASK)
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/* Number of entries per chunk */
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#define MTS64_CHUNK_SIZE 256
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#define MTS32_CHUNK_SIZE 256
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/* MTS64: chunk definition */
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struct mts64_chunk {
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mts64_entry_t entry[MTS64_CHUNK_SIZE];
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struct mts64_chunk *next;
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u_int count;
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};
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/* MTS32: chunk definition */
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struct mts32_chunk {
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mts32_entry_t entry[MTS32_CHUNK_SIZE];
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struct mts32_chunk *next;
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u_int count;
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};
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/*check whether vaddr need map*/
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static int forced_inline vaddr_mapped (m_va_t vaddr)
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{
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int zone = (vaddr >> 29) & 0x7;
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if ((zone == 0x4) || (zone == 0x5)) {
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return 0;
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} else {
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return 1;
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}
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}
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/* Shutdown the MTS subsystem */
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void mips_mem_shutdown (cpu_mips_t * cpu);
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/* Set the address mode */
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int mips_set_addr_mode (cpu_mips_t * cpu, u_int addr_mode);
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void physmem_dma_transfer (vm_instance_t * vm, m_pa_t src, m_pa_t dst,
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size_t len);
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void *physmem_get_hptr (vm_instance_t * vm, m_pa_t paddr, u_int op_size,
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u_int op_type, m_uint32_t * data);
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#endif
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