5cb608d7e1
Delete device names from all the drivers. Move device inslude files from include/sys to include/machine directory. Only include files which have something useful for user layer (like special ioctls codes) should be placed into sys.
529 lines
14 KiB
ArmAsm
529 lines
14 KiB
ArmAsm
/*
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* SDRAM Access Routines for PIC32.
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*
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* Retromaster - 10.05.2010
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*
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* This file is in the public domain. You can use, modify, and distribute the source code
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* and executable programs based on the source code. This file is provided "as is" and
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* without any express or implied warranties whatsoever. Use at your own risk!
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*
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* Changes by jmcgee for inclusion in the retrobsd project.
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*/
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/* SDRAM Used: HY57V281620 */
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/*
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* See rd_sdramp_config.h for sdramp port/pin configuration
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*/
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#include <machine/sdramp_config.h>
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/* Offsets (from TRISA) for the various port control registers */
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#define TRIS_OFFSET 0x0
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#define PORT_OFFSET (PORTA-TRISA)
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#define LAT_OFFSET (LATA-TRISA)
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#define ODCF_OFFSET (ODCA-TRISA)
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/* Offsets (from TRISA) for the various io port bit manipulator registers */
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#define NOP_OP_OFFSET 0x0
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#define CLR_OP_OFFSET (TRISACLR-TRISA)
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#define SET_OP_OFFSET (TRISASET-TRISA)
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#define INV_OP_OFFSET (TRISAINV-TRISA)
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/* Global Symbols */
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.globl sdram_init
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.globl sdram_read
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.globl sdram_write
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.globl sdram_active
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.globl sdram_auto_refresh
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.globl sdram_precharge
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.globl sdram_precharge_all
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.globl sdram_sleep
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.globl sdram_wake
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.globl sdram_bank
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.type sdram_init, @function
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.type sdram_read, @function
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.type sdram_write, @function
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.type sdram_active, @function
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.type sdram_auto_refresh, @function
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.type sdram_precharge, @function
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.type sdram_precharge_all, @function
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.type sdram_sleep, @function
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.type sdram_wake, @function
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.type sdram_bank, @function
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/*
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* This code MUST execute from ram and the ram MUST be configured
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* for zero wait states. Interrupts MUST disabled before
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* calling any of these functions, and any DMA MUST also be
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* disabled.
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*
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* Also, the peripheral bus divisor must be set to 1.
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*/
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.section .ramfunc,"ax",@progbits
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/* No instruction reordering */
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.set noreorder
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#define clock4 nop;nop;nop;nop
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#define clock3 nop;nop;nop
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#define clock2 nop;nop
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#define clock1 nop
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/*
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* The SDRAM clock is output from the output compare unit.
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* This macro synchronizes with that clock so that we are
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* sure to have at least two clock cycles to issue control
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* line changes and access the data bus before the rising
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* edge.
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*/
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#define sync_clock \
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la $t8, TMR2; \
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li $v0, 2; \
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lw $v1, ($t8); \
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bge $v1, $v0, 1f; \
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nop; \
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nop; \
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nop; \
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1: \
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nop;
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/*
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* Initializes the SDRAM.
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* Should be called once sometime after startup
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* C Prototype:
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* extern __attribute__((far)) void sdram_init();
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* This should only be called from sdram_init_c,
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* which does all of the preliminary setup.
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*/
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sdram_init:
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/* Initialize address lines */
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la $t0, TRISA /* base of io addresses */
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/* Get ready for the commands we are about to issue. */
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li $t4, (1<<SDR_CONTROL_CAS_BIT)
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li $t5, (1<<SDR_CONTROL_WE_BIT)
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/* Mode Register: CL:2, BL:8 (0x23) */
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/*li $t6, 0x1810*/
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//li $t3, (1<<SDR_ADDRESS_LB_A1_BIT)|(1<<SDR_ADDRESS_LB_A0_BIT)
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//li $t6, (1<<SDR_ADDRESS_A5_BIT)
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li $t7, CONTROL_ALL_MASK
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li $t8, (1<<SDR_ADDRESS_A10_BIT) /* A10 */
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sw $t8, (SDR_ADDRESS_PORT-TRISA) + LAT_OFFSET + SET_OP_OFFSET($t0) /* A10 = 1 for Precharge ALL */
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sync_clock
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.set nomacro
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/* Precharge All */
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sw $t7, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + CLR_OP_OFFSET($t0) /* LLLL */
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sw $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + SET_OP_OFFSET($t0) /* LLHL */
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clock2
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/* Auto Refresh 1 */
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sw $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + CLR_OP_OFFSET($t0) /* LLLL */
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sw $t5, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + SET_OP_OFFSET($t0) /* LLLH */
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clock2
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/* Auto Refresh 2 */
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clock4
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/* Auto Refresh 3 */
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clock4
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/* Auto Refresh 4 */
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clock4
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/* Auto Refresh 5 */
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li $t4, ADDRESS_LB_MASK
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li $t5, ADDRESS_MASK
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clock2
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/* Auto Refresh 6 */
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sw $t4, (SDR_ADDRESS_LB_PORT-TRISA) + LAT_OFFSET + CLR_OP_OFFSET($t0)
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sw $t5, (SDR_ADDRESS_PORT-TRISA) + LAT_OFFSET + CLR_OP_OFFSET($t0)
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clock2
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/* Mode Register: CL:2, BL:8 (0x23) */
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/* Auto Refresh 7 */
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li $t4, (1<<SDR_ADDRESS_LB_A1_BIT)|(1<<SDR_ADDRESS_LB_A0_BIT)
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sw $t4, (SDR_ADDRESS_LB_PORT-TRISA) + LAT_OFFSET + SET_OP_OFFSET($t0)
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clock2
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/* Auto Refresh 8 */
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li $t4, (1<<SDR_ADDRESS_A5_BIT)
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sw $t4, (SDR_ADDRESS_PORT-TRISA) + LAT_OFFSET + SET_OP_OFFSET($t0)
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clock2
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/* Load Mode Register */
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sw $t7, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + CLR_OP_OFFSET($t0)
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clock3
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/* Command Inhibit */
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sw $t7, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + SET_OP_OFFSET($t0)
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clock3
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/* Command Inhibit */
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clock4
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.set macro
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jr $ra
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nop
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/*.end sdram_init*/
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/*
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* Sends ACTIVE command
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* C Prototype:
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* extern __attribute__((far)) void sdram_active();
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* Responsiblity of caller to output row address before calling this function.
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* See sdram_active_c( unsigned );
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*/
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sdram_active:
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la $t0, TRISA /* Port Base */
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li $t7, (1<<SDR_CONTROL_CS_BIT)|(1<<SDR_CONTROL_RAS_BIT)
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sync_clock
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.set nomacro
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/* Active */
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sw $t7, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0)
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clock3
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/* Command Inhibit */
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sw $t7, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0)
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clock3
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/* Command Inhibit */
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clock4
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.set macro
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jr $ra
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nop
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/*
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* Sends WRITE command
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* C Prototype:
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* extern __attribute__((far)) void sdram_write(uint64_t val);
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* Each pseudo column contains 8 bytes of data (consists of 8 ram columns)
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* Responsiblity of caller to output pseudo column address before calling this function.
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* See sdram_write_c( unsigned, uint64_t );
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*/
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sdram_write:
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la $t0, TRISA /* Port Base */
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li $t4, 0xFF
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li $t7, (1<<SDR_CONTROL_CS_BIT) | (1<<SDR_CONTROL_CAS_BIT) | (1<<SDR_CONTROL_WE_BIT)
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//#ifdef SDRAM_FPGA_DIR_SUPPORT
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// li $t3, (1<<SDR_DATA_DIR_BIT)
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// sw $t3, (SDR_DATA_DIR_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0)
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//#endif
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/* Set data lines */
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srl $t5, $a0, 24
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sb $t5, (SDR_DATA_PORT-TRISA) + LAT_OFFSET + NOP_OP_OFFSET($t0)
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sync_clock
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.set nomacro
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/* Write */
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sw $t7, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LHLL */
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sw $t4, (SDR_DATA_PORT-TRISA) + TRIS_OFFSET + CLR_OP_OFFSET($t0) /* 1 - enable data lines */
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srl $t5, $a0, 16
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clock1
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/* Command Inhibit */
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sw $t7, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* HHHH */
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sb $t5, (SDR_DATA_PORT-TRISA) + LAT_OFFSET + NOP_OP_OFFSET($t0) /* 2 */
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srl $t5, $a0, 8
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clock1
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/* Command Inhibit */
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sb $t5, (SDR_DATA_PORT-TRISA) + LAT_OFFSET + NOP_OP_OFFSET($t0) /* 3 */
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clock3
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/* Command Inhibit */
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sb $a0, (SDR_DATA_PORT-TRISA) + LAT_OFFSET + NOP_OP_OFFSET($t0) /* 4 */
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srl $t5, $a1, 24
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clock2
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/* Command Inhibit */
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sb $t5, (SDR_DATA_PORT-TRISA) + LAT_OFFSET + NOP_OP_OFFSET($t0) /* 5 */
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srl $t5, $a1, 16
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clock2
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/* Command Inhibit */
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sb $t5, (SDR_DATA_PORT-TRISA) + LAT_OFFSET + NOP_OP_OFFSET($t0) /* 6 */
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srl $t5, $a1, 8
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clock2
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/* Command Inhibit */
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sb $t5, (SDR_DATA_PORT-TRISA) + LAT_OFFSET + NOP_OP_OFFSET($t0) /* 7 */
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clock3
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/* Command Inhibit */
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sb $a1, (SDR_DATA_PORT-TRISA) + LAT_OFFSET + NOP_OP_OFFSET($t0) /* 8 */
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clock3
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sw $t4, (SDR_DATA_PORT-TRISA) + LAT_OFFSET + CLR_OP_OFFSET($t0) /* PIC32 errata - thanks Pito. */
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sw $t4, (SDR_DATA_PORT-TRISA) + TRIS_OFFSET + SET_OP_OFFSET($t0) /* Data lines input again */
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.set macro
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//#ifdef SDRAM_FPGA_DIR_SUPPORT
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// clock4
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// li $t3, (1<<SDR_DATA_DIR_BIT)
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// sw $t3, (SDR_DATA_DIR_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0)
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//#endif
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jr $ra
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nop
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/*
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* Sends READ command
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* C Prototype:
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* extern __attribute__((far)) uint64_t sdram_read();
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* Each pseudo column contains 8 bytes of data (consists of 8 ram columns)
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* Responsiblity of caller to output pseudo column address before calling this function.
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* See sdram_read_c()
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*/
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sdram_read:
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la $t0, TRISA /* Port Base */
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li $t7, (1<<SDR_CONTROL_CS_BIT) | (1<<SDR_CONTROL_CAS_BIT)
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sync_clock
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.set nomacro
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/* Read */
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sw $t7, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LHLH */
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clock3
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/* Command Inhibit */
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sw $t7, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* HHHH */
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clock3
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/* Command Inhibit */
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clock3
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lbu $v0, (SDR_DATA_PORT-TRISA) + PORT_OFFSET + NOP_OP_OFFSET($t0) /* 1 */
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/* Command Inhibit */
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clock3
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lbu $t5, (SDR_DATA_PORT-TRISA) + PORT_OFFSET + NOP_OP_OFFSET($t0) /* 2 */
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/* Command Inhibit */
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sll $v0, $v0, 8
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or $v0, $v0, $t5
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clock1
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lbu $t5, (SDR_DATA_PORT-TRISA) + PORT_OFFSET + NOP_OP_OFFSET($t0) /* 3 */
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/* Command Inhibit */
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sll $v0, $v0, 8
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or $v0, $v0, $t5
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clock1
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lbu $t5, (SDR_DATA_PORT-TRISA) + PORT_OFFSET + NOP_OP_OFFSET($t0) /* 4 */
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/* Command Inhibit */
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sll $v0, $v0, 8
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or $v0, $v0, $t5
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clock1
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lbu $v1, (SDR_DATA_PORT-TRISA) + PORT_OFFSET + NOP_OP_OFFSET($t0) /* 5 */
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/* Command Inhibit */
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clock3
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lbu $t5, (SDR_DATA_PORT-TRISA) + PORT_OFFSET + NOP_OP_OFFSET($t0) /* 6 */
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/* Command Inhibit */
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sll $v1, $v1, 8
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or $v1, $v1, $t5
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clock1
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lbu $t5, (SDR_DATA_PORT-TRISA) + PORT_OFFSET + NOP_OP_OFFSET($t0) /* 7 */
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/* Command Inhibit */
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sll $v1, $v1, 8
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or $v1, $v1, $t5
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clock1
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lbu $t5, (SDR_DATA_PORT-TRISA) + PORT_OFFSET + NOP_OP_OFFSET($t0) /* 8 */
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/* Command Inhibit */
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sll $v1, $v1, 8
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or $v1, $v1, $t5
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.set macro
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jr $ra
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nop
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/*
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* Sends PRECHARGE ALL command
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* C Prototype:
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* extern __attribute__((far)) void sdram_precharge_all(void);
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*/
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sdram_precharge_all:
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la $t0, TRISA /* Port Base */
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li $t3, (1<<SDR_ADDRESS_A10_BIT) /* A10 */
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li $t4, (1<<SDR_CONTROL_CS_BIT) | (1<<SDR_CONTROL_RAS_BIT) | (1<<SDR_CONTROL_WE_BIT)
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sw $t3, (SDR_ADDRESS_PORT-TRISA) + LAT_OFFSET + SET_OP_OFFSET($t0) /* A10 = 1 for Precharge ALL */
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sync_clock
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.set nomacro
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/* Precharge All */
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sw $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LLHL */
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clock3
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/* Command Inhibit */
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sw $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LLLL */
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clock3
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.set macro
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jr $ra
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nop
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/*
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* Sends PRECHARGE command
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* C Prototype:
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* extern __attribute__((far)) void sdram_precharge(void);
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*/
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sdram_precharge:
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la $t0, TRISA /* Port Base */
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li $t3, (1<<SDR_ADDRESS_A10_BIT) /* A10 */
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li $t4, (1<<SDR_CONTROL_CS_BIT) | (1<<SDR_CONTROL_RAS_BIT) | (1<<SDR_CONTROL_WE_BIT)
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sw $t3, (SDR_ADDRESS_PORT-TRISA) + LAT_OFFSET + CLR_OP_OFFSET($t0) /* A10 = 0 for Precharge */
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sync_clock
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.set nomacro
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/* Precharge All */
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sw $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LLHL */
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clock3
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/* Command Inhibit */
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sw $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LLLL */
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clock3
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.set macro
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jr $ra
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nop
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/*
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* Sends AUTO REFRESH command
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* All banks must be in PRECHARGEd state
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* C Prototype:
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* extern __attribute__((far)) void sdram_auto_refresh(void);
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*/
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sdram_auto_refresh:
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la $t0, TRISA /* Port Base */
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li $t4, (1<<SDR_CONTROL_CS_BIT)|(1<<SDR_CONTROL_RAS_BIT)|(1<<SDR_CONTROL_CAS_BIT)
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sync_clock
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.set nomacro
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/* Auto Refresh */
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sw $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LLLH */
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clock3
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/* Command Inhibit */
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sw $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LLLL */
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clock3
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.set macro
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jr $ra
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nop
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/*
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* Puts the SDRAM into the self refresh mode.
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* SDRAM retains data in this state.
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* C Prototype:
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* extern __attribute__((far)) void sdram_sleep(void);
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*/
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sdram_sleep:
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la $t0, TRISA /* Port Base */
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li $t1, (1<<SDR_CKE_BIT)
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li $t4, (1<<SDR_CONTROL_CS_BIT)|(1<<SDR_CONTROL_RAS_BIT)|(1<<SDR_CONTROL_CAS_BIT)
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sync_clock
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.set nomacro
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/* Auto Refresh */
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sw $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LLLH */
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sw $t1, (SDR_CKE_PORT-TRISA) + LAT_OFFSET + CLR_OP_OFFSET($t0) /* CKE low */
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clock2
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/* Command Inhibit */
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sw $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LLLL */
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clock3
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.set macro
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jr $ra
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nop
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/*
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* Takes the SDRAM out of the self refresh mode.
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* Parameters: none
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* C Prototype:
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* extern __attribute__((far)) void sdram_wake(void);
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*/
|
|
sdram_wake:
|
|
|
|
la $t0, TRISA /* Port Base */
|
|
li $t1, (1<<SDR_CKE_BIT)
|
|
|
|
sync_clock
|
|
|
|
.set nomacro
|
|
|
|
/* Command Inhibit */
|
|
sw $t1, (SDR_CKE_PORT-TRISA) + LAT_OFFSET + SET_OP_OFFSET($t0) /* CKE low */
|
|
clock3
|
|
|
|
/* Command Inhibit */
|
|
clock4
|
|
|
|
/* Command Inhibit */
|
|
clock4
|
|
|
|
.set macro
|
|
|
|
jr $ra
|
|
nop
|