426 lines
13 KiB
C
426 lines
13 KiB
C
/*
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* Copyright (C) yajin 2008 <yajinzhou@gmail.com >
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*
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* This file is part of the virtualmips distribution.
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* See LICENSE file for terms of the license.
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*
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*/
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#ifndef __ADM5120_H__
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#define __ADM5120_H__
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#include "types.h"
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/*virtual address and physical address*/
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typedef m_uint32_t m_va_t;
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typedef m_uint32_t m_pa_t;
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typedef m_uint32_t m_reg_t;
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typedef m_int32_t m_ireg_t;
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typedef m_uint32_t m_cp0_reg_t;
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#define DATA_WIDTH 32 /*64 */
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#define LL
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/*ADM5120 use soft fpu*/
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#define SOFT_FPU 1
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/*Guest endian*/
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#define GUEST_BYTE_ORDER ARCH_LITTLE_ENDIAN
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#ifndef GUEST_BYTE_ORDER
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#error Please define guest architecture in utils.h!
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#endif
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/* Host to VM conversion functions */
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#if HOST_BYTE_ORDER == GUEST_BYTE_ORDER
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#define htovm16(x) (x)
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#define htovm32(x) (x)
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#define htovm64(x) (x)
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#define vmtoh16(x) (x)
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#define vmtoh32(x) (x)
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#define vmtoh64(x) (x)
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#elif HOST_BYTE_ORDER==ARCH_LITTLE_ENDIAN //host:little guest:big
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#define htovm16(x) (htons(x))
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#define htovm32(x) (htonl(x))
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#define htovm64(x) (swap64(x))
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#define vmtoh16(x) (ntohs(x))
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#define vmtoh32(x) (ntohl(x))
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#define vmtoh64(x) (swap64(x))
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#else //host:big guest:little
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#define htovm16(x) (ntohs(x))
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#define htovm32(x) (ntohl(x))
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#define htovm64(x) (swap64(x))
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#define vmtoh16(x) (htons(x))
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#define vmtoh32(x) (htonl(x))
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#define vmtoh64(x) (swap64(x))
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#endif
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#define ADM5120_DEFAULT_CONFIG_FILE "adm5120.conf"
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#define ADM5120_DEFAULT_RAM_SIZE 16
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#define ADM5120_DEFAULT_BOOT_METHOD BOOT_ELF
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#define ADM5120_DEFAULT_KERNEL_FILENAME "vmlinux"
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#define ADM5120_ADDR_BUS_MASK 0xffffffff /*32bit phy address */
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#define ADM5120_CONFIG0 0x80000082
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#define ADM5120_CONFIG1 0x3E613080 /*CACHE (128SET*32 BYTES*2 WAY)= 8K */
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//#define ADM5120_CONFIG7 0x0
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//#define SOC_CONFIG0 ADM5120_CONFIG0
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//#define SOC_CONFIG1 ADM5120_CONFIG1
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//#define SOC_CONFIG7 ADM5120_CONFIG7
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#define ADM5120_ROM_PC 0xbfc00000UL
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#define ADM5120_PRID 0x0001800b
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#define ADM5120_DEFAULT_TLB_ENTRYNO 16
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struct adm5120_system {
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/* Associated VM instance */
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vm_instance_t *vm;
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};
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typedef struct adm5120_system adm5120_t;
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#define VM_ADM5120(vm) ((adm5120_t *)vm->hw_data)
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vm_instance_t *create_instance (char *conf);
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int init_instance (vm_instance_t * vm);
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//void virtual_timer(cpu_mips_t *cpu);
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/*---------ADM5120 SOC releated--------------------*/
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/*========================= Physical Memory Map ============================*/
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#define ADM5120_SDRAM_BASE 0
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#define ADM5120_SMEM1_BASE 0x10000000
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#define ADM5120_EXTIO0_BASE 0x10C00000
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#define ADM5120_EXTIO1_BASE 0x10E00000
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#define ADM5120_MPMC_BASE 0x11000000
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#define ADM5120_USBHOST_BASE 0x11200000
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#define ADM5120_PCIMEM_BASE 0x11400000
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#define ADM5120_PCIIO_BASE 0x11500000
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#define ADM5120_PCICFG_BASE 0x115FFFF0
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#define ADM5120_MIPS_BASE 0x11A00000
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#define ADM5120_SWCTRL_BASE 0x12000000
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#define ADM5120_INTC_BASE 0x12200000
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#define ADM5120_SYSC_BASE 0x12400000
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#define ADM5120_UART0_BASE 0x12600000
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#define ADM5120_UART1_BASE 0x12800000
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#define ADM5120_SMEM0_BASE 0x1FC00000
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/*========================= Switch Control Register ========================*/
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/* Control Register */
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#define CODE_REG 0x0000
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#define SftRest_REG 0x0004
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#define Boot_done_REG 0x0008
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#define SWReset_REG 0x000C
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#define Global_St_REG 0x0010
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#define PHY_st_REG 0x0014
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#define Port_st_REG 0x0018
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#define Mem_control_REG 0x001C
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#define SW_conf_REG 0x0020
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#define CPUp_conf_REG 0x0024
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#define Port_conf0_REG 0x0028
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#define Port_conf1_REG 0x002C
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#define Port_conf2_REG 0x0030
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#define VLAN_G1_REG 0x0040
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#define VLAN_G2_REG 0x0044
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#define Send_trig_REG 0x0048
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#define Srch_cmd_REG 0x004C
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#define ADDR_st0_REG 0x0050
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#define ADDR_st1_REG 0x0054
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#define MAC_wt0_REG 0x0058
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#define MAC_wt1_REG 0x005C
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#define BW_cntl0_REG 0x0060
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#define BW_cntl1_REG 0x0064
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#define PHY_cntl0_REG 0x0068
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#define PHY_cntl1_REG 0x006C
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#define FC_th_REG 0x0070
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#define Adj_port_th_REG 0x0074
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#define Port_th_REG 0x0078
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#define PHY_cntl2_REG 0x007C
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#define PHY_cntl3_REG 0x0080
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#define Pri_cntl_REG 0x0084
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#define VLAN_pri_REG 0x0088
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#define TOS_en_REG 0x008C
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#define TOS_map0_REG 0x0090
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#define TOS_map1_REG 0x0094
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#define Custom_pri1_REG 0x0098
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#define Custom_pri2_REG 0x009C
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#define PHY_cntl4_REG 0x00A0
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#define Empty_cnt_REG 0x00A4
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#define Port_cnt_sel_REG 0x00A8
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#define Port_cnt_REG 0x00AC
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#define SW_Int_st_REG 0x00B0
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#define SW_Int_mask_REG 0x00B4
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// GPIO config
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#define GPIO_conf0_REG 0x00B8
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#define GPIO_conf2_REG 0x00BC
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// Watch dog
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#define Watchdog0_REG 0x00C0
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#define Watchdog1_REG 0x00C4
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#define Swap_in_REG 0x00C8
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#define Swap_out_REG 0x00CC
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// Tx/Rx Descriptors
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#define Send_HBaddr_REG 0x00D0
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#define Send_LBaddr_REG 0x00D4
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#define Recv_HBaddr_REG 0x00D8
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#define Recv_LBaddr_REG 0x00DC
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#define Send_HWaddr_REG 0x00E0
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#define Send_LWaddr_REG 0x00E4
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#define Recv_HWaddr_REG 0x00E8
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#define Recv_LWaddr_REG 0x00EC
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// Timer Control
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#define Timer_int_REG 0x00F0
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#define Timer_REG 0x00F4
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// LED control
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#define Port0_LED_REG 0x0100
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#define Port1_LED_REG 0x0104
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#define Port2_LED_REG 0x0108
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#define Port3_LED_REG 0x010c
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#define Port4_LED_REG 0x0110
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#define SW_INDEX_MAX 0x45 //0x0114/4
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/* Timer_int_REG */
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#define SW_TIMER_INT_DISABLE 0x10000
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#define SW_TIMER_INT 0x1
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/* Timer_REG */
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#define SW_TIMER_EN 0x10000
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#define SW_TIMER_MASK 0xffff
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#define SW_TIMER_10MS_TICKS 0x3D09
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#define SW_TIMER_1MS_TICKS 0x61A
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#define SW_TIMER_100US_TICKS 0x9D
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/*==================== MultiPort Memory Controller (MPMC) ==================*/
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/* registers offset */
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#define MPMC_CONTROL_REG 0x0000
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#define MPMC_STATUS_REG 0x0004
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#define MPMC_CONFIG_REG 0x0008
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#define MPMC_DM_CONTROL_REG 0x0020
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#define MPMC_DM_REFRESH_REG 0x0024
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#define MPMC_DM_TRP_REG 0x0030
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#define MPMC_DM_TRAS_REG 0x0034
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#define MPMC_DM_TSREX_REG 0x0038
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#define MPMC_DM_TAPR_REG 0x003C
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#define MPMC_DM_TDAL_REG 0x0040
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#define MPMC_DM_TWR_REG 0x0044
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#define MPMC_DM_TRC_REG 0x0048
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#define MPMC_DM_TRFC_REG 0x004C
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#define MPMC_DM_TXSR_REG 0x0050
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#define MPMC_DM_TRRD_REG 0x0054
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#define MPMC_DM_TMRD_REG 0x0058
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#define MPMC_SM_EXTWAIT_REG 0x0080
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#define MPMC_DM_CONFIG0_REG 0x0100
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#define MPMC_DM_RASCAS0_REG 0x0104
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#define MPMC_DM_CONFIG1_REG 0x0120
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#define MPMC_DM_RASCAS1_REG 0x0124
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#define MPMC_SM_CONFIG0_REG 0x0200
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#define MPMC_SM_WAITWEN0_REG 0x0204
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#define MPMC_SM_WAITOEN0_REG 0x0208
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#define MPMC_SM_WAITRD0_REG 0x020C
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#define MPMC_SM_WAITPAGE0_REG 0x0210
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#define MPMC_SM_WAITWR0_REG 0x0214
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#define MPMC_SM_WAITTURN0_REG 0x0218
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#define MPMC_SM_CONFIG1_REG 0x0220
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#define MPMC_SM_WAITWEN1_REG 0x0224
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#define MPMC_SM_WAITOEN1_REG 0x0228
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#define MPMC_SM_WAITRD1_REG 0x022C
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#define MPMC_SM_WAITPAGE1_REG 0x0230
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#define MPMC_SM_WAITWR1_REG 0x0234
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#define MPMC_SM_WAITTURN1_REG 0x0238
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#define MPMC_SM_CONFIG2_REG 0x0240
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#define MPMC_SM_WAITWEN2_REG 0x0244
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#define MPMC_SM_WAITOEN2_REG 0x0248
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#define MPMC_SM_WAITRD2_REG 0x024C
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#define MPMC_SM_WAITPAGE2_REG 0x0250
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#define MPMC_SM_WAITWR2_REG 0x0254
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#define MPMC_SM_WAITTURN2_REG 0x0258
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#define MPMC_SM_CONFIG3_REG 0x0260
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#define MPMC_SM_WAITWEN3_REG 0x0264
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#define MPMC_SM_WAITOEN3_REG 0x0268
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#define MPMC_SM_WAITRD3_REG 0x026C
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#define MPMC_SM_WAITPAGE3_REG 0x0270
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#define MPMC_SM_WAITWR3_REG 0x0274
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#define MPMC_SM_WAITTURN3_REG 0x0278
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#define MPMC_INDEX_MAX 0x9f //0x027C/4
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/*=========================== UART Control Register
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========================*/
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#define UART_DR_REG 0x00
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#define UART_RSR_REG 0x04
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#define UART_ECR_REG 0x04
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#define UART_LCR_H_REG 0x08
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#define UART_LCR_M_REG 0x0c
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#define UART_LCR_L_REG 0x10
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#define UART_CR_REG 0x14
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#define UART_FR_REG 0x18
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#define UART_IIR_REG 0x1c
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#define UART_ICR_REG 0x1C
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#define UART_ILPR_REG 0x20
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/* rsr/ecr reg */
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#define UART_OVERRUN_ERR 0x08
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#define UART_BREAK_ERR 0x04
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#define UART_PARITY_ERR 0x02
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#define UART_FRAMING_ERR 0x01
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#define UART_RX_STATUS_MASK 0x0f
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#define UART_RX_ERROR ( UART_BREAK_ERR \
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| UART_PARITY_ERR \
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| UART_FRAMING_ERR)
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/* lcr_h reg */
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#define UART_SEND_BREAK 0x01
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#define UART_PARITY_EN 0x02
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#define UART_EVEN_PARITY 0x04
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#define UART_TWO_STOP_BITS 0x08
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#define UART_ENABLE_FIFO 0x10
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#define UART_WLEN_5BITS 0x00
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#define UART_WLEN_6BITS 0x20
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#define UART_WLEN_7BITS 0x40
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#define UART_WLEN_8BITS 0x60
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#define UART_WLEN_MASK 0x60
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/* cr reg */
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#define UART_PORT_EN 0x01
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#define UART_SIREN 0x02
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#define UART_SIRLP 0x04
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#define UART_MODEM_STATUS_INT_EN 0x08
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#define UART_RX_INT_EN 0x10
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#define UART_TX_INT_EN 0x20
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#define UART_RX_TIMEOUT_INT_EN 0x40
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#define UART_LOOPBACK_EN 0x80
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/* fr reg */
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#define UART_CTS 0x01
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#define UART_DSR 0x02
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#define UART_DCD 0x04
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#define UART_BUSY 0x08
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#define UART_RX_FIFO_EMPTY 0x10
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#define UART_TX_FIFO_FULL 0x20
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#define UART_RX_FIFO_FULL 0x40
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#define UART_TX_FIFO_EMPTY 0x80
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/* iir/icr reg */
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#define UART_MODEM_STATUS_INT 0x01
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#define UART_RX_INT 0x02
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#define UART_TX_INT 0x04
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#define UART_RX_TIMEOUT_INT 0x08
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#define UART_INT_MASK 0x0f
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#define ADM5120_UARTCLK_FREQ 62500000
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/* uart_baudrate */
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#define UART_230400bps_DIVISOR UART_BAUDDIV(230400)
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// #define UART_115200bps_DIVISOR UART_BAUDDIV(115200)
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#define UART_115200bps_DIVISOR 33
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// #define UART_76800bps_DIVISOR UART_BAUDDIV(76800)
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#define UART_76800bps_DIVISOR 50
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// #define UART_57600bps_DIVISOR UART_BAUDDIV(57600)
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#define UART_57600bps_DIVISOR 67
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//#define UART_38400bps_DIVISOR UART_BAUDDIV(38400)
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#define UART_38400bps_DIVISOR 102
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//#define UART_19200bps_DIVISOR UART_BAUDDIV(19200)
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#define UART_19200bps_DIVISOR 202
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//#define UART_14400bps_DIVISOR UART_BAUDDIV(14400)
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#define UART_14400bps_DIVISOR 270
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//#define UART_9600bps_DIVISOR UART_BAUDDIV(9600)
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#define UART_9600bps_DIVISOR 406
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//#define UART_2400bps_DIVISOR UART_BAUDDIV(2400)
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#define UART_2400bps_DIVISOR 1627
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//#define UART_1200bps_DIVISOR UART_BAUDDIV(1200)
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#define UART_INDEX_MAX 0x9 //0x024/4
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/* pci space
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pci memory 0x1140 0000- 0x114f ffff
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pci io 0x1150 0000 - 0x 115f ffef
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pci configuration address port 0x115ffff0
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pci configuration data port 0x115ffff8
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*/
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#define ADM5120_PCI_BASE 0x11400000
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#define PCI_INDEX_MAX 0X80000 //0X200000/4
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/*========================== Interrupt Controller ==========================*/
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/* registers offset */
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#define IRQ_STATUS_REG 0x00 /* Read */
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#define IRQ_RAW_STATUS_REG 0x04 /* Read */
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#define IRQ_ENABLE_REG 0x08 /* Read/Write */
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#define IRQ_DISABLE_REG 0x0C /* Write */
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#define IRQ_SOFT_REG 0x10 /* Write */
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#define IRQ_MODE_REG 0x14 /* Read/Write */
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#define FIQ_STATUS_REG 0x18 /* Read */
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/* test registers */
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#define IRQ_TESTSRC_REG 0x1c /* Read/Write */
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#define IRQ_SRCSEL_REG 0x20 /* Read/Write */
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#define IRQ_LEVEL_REG 0x24 /* Read/Write */
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#define INTCTRL_INDEX_MAX 0xa //0x028/4
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/* interrupt levels */
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#define INT_LVL_TIMER 0 /* Timer */
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#define INT_LVL_UART0 1 /* Uart 0 */
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#define INT_LVL_UART1 2 /* Uart 1 */
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#define INT_LVL_USBHOST 3 /* USB Host */
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#define INT_LVL_EXTIO_0 4 /* External I/O 0 */
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#define INT_LVL_EXTIO_1 5 /* External I/O 1 */
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#define INT_LVL_PCI_0 6 /* PCI 0 */
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#define INT_LVL_PCI_1 7 /* PCI 1 */
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#define INT_LVL_PCI_2 8 /* PCI 2 */
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#define INT_LVL_SWITCH 9 /* Switch */
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#define INT_LVL_MAX INT_LVL_SWITCH
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/* interrupts */
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#define IRQ_TIMER (0x1 << INT_LVL_TIMER)
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#define IRQ_UART0 (0x1 << INT_LVL_UART0)
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#define IRQ_UART1 (0x1 << INT_LVL_UART1)
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#define IRQ_USBHOST (0x1 << INT_LVL_USBHOST)
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#define IRQ_EXTIO_0 (0x1 << INT_LVL_EXTIO_0)
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#define IRQ_EXTIO_1 (0x1 << INT_LVL_EXTIO_1)
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#define IRQ_PCI_INT0 (0x1 << INT_LVL_PCI_0)
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#define IRQ_PCI_INT1 (0x1 << INT_LVL_PCI_1)
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#define IRQ_PCI_INT2 (0x1 << INT_LVL_PCI_2)
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#define IRQ_SWITCH (0x1 << INT_LVL_SWITCH)
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#define IRQ_MASK 0x3ff
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#define ADM5120_MIPSINT_SOFT0 0
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#define ADM5120_MIPSINT_SOFT1 1
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#define ADM5120_MIPSINT_IRQ 2
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#define ADM5120_MIPSINT_FIQ 3
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#define ADM5120_MIPSINT_REV0 4
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#define ADM5120_MIPSINT_REV1 5
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#define ADM5120_MIPSINT_REV2 6
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#define ADM5120_MIPSINT_TIMER 7
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#endif
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