234 lines
5.4 KiB
C
234 lines
5.4 KiB
C
/*
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* Driver for external SRAM-CPLD based Swap and Filesystem devices
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*
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* This version is for 8MB RAMDISK v.1.1 and compatible
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* Pito 7.4.2014 - PIC32MX PMP bus version
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* Under by retrobsd.org used Licence
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* No warranties of any kind
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*
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* Interface:
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* PMD<7:0> - connected to PMP data bus
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* PMRD - fetch a byte from memory to data<7:0>, increment address, PMRD
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* PMWR - write a byte data[7:0] to memory, increment address, PMWR
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* PMA0 - HIGH - write Address from data<3:0> in 6 steps: high nibble ... low nibble
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* - LOW - write/read Data
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*
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* Signals PMRD, PMWR are active LOW and idle HIGH
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* Signal PMA0 is LOW when accessing RAM Data, and HIGH when accessing RAM Addresses
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*
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*
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*/
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#include "param.h"
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#include "systm.h"
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#include "buf.h"
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#include "errno.h"
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#include "dk.h"
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#include "rdisk.h"
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#include "debug.h"
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int sw_dkn = -1; /* Statistics slot number */
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// Ramdisk v.1.1. wiring
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// PMP RAMDISK
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// ===================
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// PMD<D0-D7> D0-D7
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// PMRD /RD
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// PMWR /WR
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// PMA<0> /DATA
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// RD and WR pulses duration settings
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// Minimal recommended settings, increase them when unstable
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// No warranties of any kind
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// for 120MHz clock, 70ns PSRAM, Ramdisk v.1.1.
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#define ADR_PULSE 1
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#define WR_PULSE 5
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#define RD_PULSE 11
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// for 80MHz clock, 70ns PSRAM, Ramdisk v.1.1.
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//#define ADR_PULSE 1
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//#define WR_PULSE 3
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//#define RD_PULSE 8
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// for 120MHz clock, 55ns SRAM
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//#define ADR_PULSE 1
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//#define WR_PULSE 3
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//#define RD_PULSE 6
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// for 80MHz clock, 55ns SRAM
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//#define ADR_PULSE 1
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//#define WR_PULSE 2
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//#define RD_PULSE 4
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typedef union {
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unsigned value;
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struct {
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unsigned nib1: 4; // lowest nibble
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unsigned nib2: 4;
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unsigned nib3: 4;
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unsigned nib4: 4;
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unsigned nib5: 4;
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unsigned nib6: 4;
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unsigned nib7: 4;
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unsigned nib8: 4; // highest nibble
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};
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} nybbles ;
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/*
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* Load the 24 bit address to Ramdisk.
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*
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*/
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inline static void
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dev_load_address (addr)
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unsigned addr;
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{
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nybbles temp;
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temp.value = addr;
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while(PMMODE & 0x8000); // Poll - if busy, wait
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PMADDR = 1; // set ADR mode (1) to write the Address
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PMMODE = 0b10<<8 | (ADR_PULSE<<2); // full ADR speed
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PMDIN = temp.nib6; /* write 4 bits */
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while(PMMODE & 0x8000); // Poll - if busy, wait
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PMDIN = temp.nib5; /* write 4 bits */
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while(PMMODE & 0x8000); // Poll - if busy, wait
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PMDIN = temp.nib4; /* write 4 bits */
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while(PMMODE & 0x8000); // Poll - if busy, wait
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PMDIN = temp.nib3; /* write 4 bits */
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while(PMMODE & 0x8000); // Poll - if busy, wait
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PMDIN = temp.nib2; /* write 4 bits */
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while(PMMODE & 0x8000); // Poll - if busy, wait
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PMDIN = temp.nib1; /* write 4 bits */
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}
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/*
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* Get number of kBytes on the disk.
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* Return nonzero if successful.
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*/
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int sramc_size ( int unit )
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{
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return 8192; // 4096 for 4MB ramdisk
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}
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/*
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* Read a block of data.
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*/
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inline int sramc_read (int unit, unsigned int blockno, char *data, unsigned int nbytes)
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{
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int i;
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//DEBUG9("sramc%d: read block %u, length %u bytes, addr %p\n",
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// major(dev), blockno, nbytes, data);
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dev_load_address (blockno * DEV_BSIZE);
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/* Read data. */
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while(PMMODE & 0x8000); // Poll - if busy, wait
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PMADDR = 0; // set DATA mode (0)
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PMMODE = 0b10<<8 | (RD_PULSE<<2); // read slowly
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PMDIN; // Read the PMDIN to clear previous data and latch new data
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for (i=0; i<nbytes; i++) {
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while(PMMODE & 0x8000); // Poll - if busy, wait before reading
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*data++ = PMDIN; /* read a byte of data */
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}
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return 1;
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}
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/*
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* Write a block of data.
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*/
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inline int sramc_write (int unit, unsigned int blockno, char *data, unsigned int nbytes)
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{
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unsigned i;
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//DEBUG9("sramc%d: write block %u, length %u bytes, addr %p\n",
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// major(dev), blockno, nbytes, data);
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dev_load_address (blockno * DEV_BSIZE);
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/* Write data. */
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while (PMMODE & 0x8000); // Poll - if busy, wait
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PMADDR = 0; // set DATA mode (0)
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PMMODE = 0b10<<8 | (WR_PULSE<<2); // faster with write
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for (i=0; i<nbytes; i++) {
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while(PMMODE & 0x8000); // Poll - if busy, wait
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PMDIN = (*data++); /* write a byte of data */
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}
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return 1;
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}
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/*
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* Init the disk.
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*/
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void sramc_init (int unit)
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{
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struct buf *bp;
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// Initialize PMP hardware
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PMCON = 0; // disable PMP
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asm volatile ("nop"); // Errata
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PMCON = 1<<9 | 1<<8; // Enable RD and WR
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// MODE WAITB WAITM WAITE
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PMMODE = 0b10<<8 | 0 | (14<<2) | 0 ; // Mode2 Master 8bit
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PMAEN = 1; // PMA<0>, use A0 only
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PMADDR = 0; // start with DATA mode
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PMCONSET = 1<<15; // PMP enabled
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asm volatile ("nop");
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// make a couple of dummy reads - it refreshes the cpld internals a little bit :)
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while(PMMODE & 0x8000); // Poll - if busy, wait before reading
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PMDIN; /* read a byte of data */
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while(PMMODE & 0x8000); // Poll - if busy, wait before reading
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PMDIN; /* read a byte of data */
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PMADDR = 1; // go with with ADDRESS mode now
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DEBUG3("sramc%d: init done\n",unit);
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bp = prepartition_device("sramc0");
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if(bp)
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{
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sramc_write(0, 0, bp->b_addr, 512);
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brelse(bp);
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}
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return;
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}
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/*
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* Open the disk.
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*/
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int sramc_open (int unit)
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{
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DEBUG3("sramc%d: open\n",unit);
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return 0;
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}
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