158 lines
7.1 KiB
C
158 lines
7.1 KiB
C
/*
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* SSD1926 hardware definitions
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*
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* Copyright (C) 2008 Microchip Technology Inc. All rights reserved.
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* Microchip licenses to you the right to use, modify, copy and distribute
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* Software only when embedded on a Microchip microcontroller or digital
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* signal controller, which is integrated into your product or third party
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* product (pursuant to the sublicense terms in the accompanying license
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* agreement).
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*
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* You should refer to the license agreement accompanying this Software
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* for additional information regarding your rights and obligations.
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*
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* SOFTWARE AND DOCUMENTATION ARE PROVIDED 'AS IS' WITHOUT WARRANTY OF ANY
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* KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY
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* OF MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
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* PURPOSE. IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR
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* OBLIGATED UNDER CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION,
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* BREACH OF WARRANTY, OR OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT
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* DAMAGES OR EXPENSES INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL,
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* INDIRECT, PUNITIVE OR CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA,
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* COST OF PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY
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* CLAIMS BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
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* OR OTHER SIMILAR COSTS.
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*
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* Author Date Comments
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* -----------------------------------------------------
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* Sean Justice 15_Sept-2008 First release
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* Anton Alkhimenok 06_Jun-2009 Ported to PIC24
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*/
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#ifndef _SSD1926_H
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#define _SSD1926_H
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/*
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* User Defines
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*/
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#define SSD_SYS_CLOCK (DWORD) (4000000) /* SSD1926 crystal frequncy */
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#define SSD_SD_CLK_INIT (DWORD) (400000)
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#define SD_TIMEOUT (DWORD) (3000000)
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/*
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* Registers
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*/
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#define SSD_REG_PLL_CONFIG0 0x0126
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#define SSD_REG_PLL_CONFIG1 0x0127
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#define SSD_REG_MCLK_CONIG 0x0004
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#define SSD_SDCARD_SD_CLK 0x1001
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#define SSD_SDCARD_REG_DMA_ADDR 0x1100
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#define SSD_SDCARD_REG_BLK_SIZE 0x1104
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#define SSD_SDCARD_REG_BLK_CNT 0x1106
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#define SSD_SDCARD_REG_ARG_32BIT 0x1108
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#define SSD_SDCARD_REG_XFR_MODE 0x110c
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#define SSD_SDCARD_REG_CMD 0x110e
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#define SSD_SDCARD_REG_RSP 0x1110
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#define SSD_SDCARD_REG_DATA_PORT 0x1120
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#define SSD_SDCARD_REG_RSVD1 0x1121
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#define SSD_SDCARD_REG_PRSNT_STATE_0 0x1124
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#define SSD_SDCARD_REG_PRSNT_STATE_1 0x1125
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#define SSD_SDCARD_REG_PRSNT_STATE_2 0x1126
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#define SSD_SDCARD_REG_PRSNT_STATE_3 0x1127
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#define SSD_SDCARD_REG_HST_CNTL 0x1128
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#define SSD_SDCARD_REG_PWR_CNTL 0x1129
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#define SSD_SDCARD_REG_BLK_GAP_CNTL 0x112a
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#define SSD_SDCARD_REG_WKUP_CNTL 0x112b
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#define SSD_SDCARD_REG_CLK_CNTL 0x112c
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#define SSD_SDCARD_REG_CLK_DIV 0x112d
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#define SSD_SDCARD_REG_TOUT_CNTL 0x112e
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#define SSD_SDCARD_REG_SW_RESET 0x112f
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#define SSD_SDCARD_REG_NRM_INTR_STATUS 0x1130
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#define SSD_SDCARD_REG_ERR_INTR_STATUS 0x1132
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#define SSD_SDCARD_REG_NRM_INTR_STATUS_EN 0x1134
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#define SSD_SDCARD_REG_ERR_INTR_STATUS_EN 0x1136
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#define SSD_SDCARD_REG_NRM_INTR_SIG_EN 0x1138
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#define SSD_SDCARD_REG_ERR_INTR_SIG_EN 0x113a
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#define SSD_SDCARD_REG_ACMD12_ERR_STATUS 0x113c
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#define SSD_SDCARD_REG_RSVD2 0x113e
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#define SSD_SDCARD_REG_CAPABILITIES 0x1140
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#define SSD_SDCARD_REG_CAP_RSVD 0x1144
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#define SSD_SDCARD_REG_MAX_CURR_CAP 0x1148
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#define SSD_SDCARD_REG_MAX_CURR_CAP_RSVD 0x114c
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#define SSD_SDCARD_REG_RSVD3 0x1150
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#define SSD_SDCARD_REG_SLOT_INTR_STATUS 0x11fc
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#define SSD_SDCARD_REG_HCVER 0x11fe
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/*
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* SD Commands
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*/
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#define CMD_RESET 0
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#define CMD_SEND_OCR 1 // used exclusively in MMC
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#define CMD_SEND_ALL_CID 2 // R2: R136
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#define CMD_SEND_RCA 3 // R1 (MMC) or R6(SDMEM)
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#define CMD_SET_DSR 4
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#define CMD_IO_SEND_OCR 5 // R4, unique to IO cards
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#define CMD_SELECT_CARD 7 // R1, arg=rca[31..16] or 0
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#define CMD_SEND_IF_COND 8
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#define CMD_SEND_CSD 9 // R2: R136
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#define CMD_SEND_CID 10 // R2: R136
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#define CMD_STOP_TRANSMISSION 12 // R1b: arg=stuff bits
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#define CMD_SEND_STATUS 13 // R1
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#define CMD_GO_INACTIVE 15 // None, arg=rca[31..16], stuff[15..0]
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#define CMD_SET_BLKLEN 16 // R1, arg=block len[31..0]
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#define CMD_RD_SINGLE 17 // R1, arg=block address[31..0]
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#define CMD_RD_MULTIPLE 18 // R1, arg=block address[31..0]
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#define CMD_WR_SINGLE 24 // R1, arg=block address[31..0]
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#define CMD_WR_MULTIPLE 25 // R1, arg=block address[31..0]
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#define CMD_SET_WP 28 // R1b, arg=wp address[31..0]
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#define CMD_CLR_WP 29 // R1b, arg=wp address[31..0]
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#define CMD_SEND_WP 30 // R1, DATA, arg=wp address[31..0]
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#define CMD_ERASE_SADDR 32 // R1, arg=block address[31..0]
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#define CMD_ERASE_EADDR 33 // R1, arg=block address[31..0]
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#define CMD_ERASE_GRP_SADDR 35 // R1, arg=block address[31..0]
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#define CMD_ERASE_GRP_EADDR 36 // R1, arg=block address[31..0]
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#define CMD_ERASE 38 // R1b, arg=stuff bits[31..0]
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#define CMD_IO_RW_DIRECT 52 // R5
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#define CMD_IO_RW_EXTENDED 53 // R1, data transfer
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#define CMD_APP_CMD 55 // R1, arg=rca[31..16], stuff[15..0]
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#define CMD_GEN_CMD 56 // R1, data, arg=stuff[31..1], RD/WR[0]
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#define ACMD_SET_BUS_WIDTH 6 // R1, arg=[1..0] = bus width, [31:2] stuff bits
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#define ACMD_SEND_STATUS 13 // R1, DATA, arg=stuff bits [31..0]
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#define ACMD_SEND_NUM_WR_BLK 22 // R1, DATA, arg=stuff bits [31..0]
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#define ACMD_SEND_OCR 41
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#define ACMD_SEND_SCR 51 // R1, arg=stuff bits[31..0]
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/*
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* Flags
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*/
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#define SSD_SD_CLK_CTRL_ON (DWORD) 0x80000000
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#define SSD_SD_CLK_ENABLE (DWORD) 0x00000004
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#define SSD_SD_INT_CLK_STABLE (DWORD) 0x00000002
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#define SSD_SD_INT_CLK_ENABLE (DWORD) 0x00000001
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#define SSD_SD_CLK_FLAGS (SSD_SD_CLK_CTRL_ON | SSD_SD_CLK_ENABLE | SSD_SD_INT_CLK_ENABLE)
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#define SSD_CMD_TYPE_ABORT 0xC0
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#define SDD_CMD_TYPE_RESUME 0x80
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#define SDD_CMD_TYPE_SUSPEND 0x40
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#define SDD_CMD_TYPE_NORMAL 0x00
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#define SSD_DATA_PRESENT 0x20
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#define SSD_CMD_IDX_CHK 0x10
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#define SSD_CMD_CRC_CHK 0x08
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#define SSD_NO_RESPONSE 0x00
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#define SSD_RESPONSE_136 0x01
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#define SSD_RESPONSE_48 0x02
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#define SSD_RESPONSE_48_BUSY 0x03
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#define SSD_CARD_DETECT 0x04
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#define SSD_CARD_STABLE 0x02
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#define SSD_CARD_INSERTED 0x01
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#define SSD_WRITE_PROTECT 0x08
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#define SSD_RESET_ALL 0x01
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#define SSD_RESET_CMD 0x02
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#define SSD_RESET_DATA 0x04
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#define WAIT_CNT (DWORD) 10000000l
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#endif /* _SSD1926_H */
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