commit e70e2b210475d1751d60d2eff1fee67d7da9c2ff Author: Lionel Sambuc Date: Fri Oct 11 20:01:36 2024 +0200 Initial Setup for the microbit v1 diff --git a/.cargo/config.toml b/.cargo/config.toml new file mode 100644 index 0000000..ea2637c --- /dev/null +++ b/.cargo/config.toml @@ -0,0 +1,42 @@ +[target.thumbv7m-none-eabi] +# uncomment this to make `cargo run` execute programs on QEMU +# runner = "qemu-system-arm -cpu cortex-m3 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel" + +[target.'cfg(all(target_arch = "arm", target_os = "none"))'] +# TODO(2) replace `$CHIP` with your chip's name (see `probe-rs chip list` output) +runner = "probe-rs run --chip nRF51822_xxAA" +# runner = ["probe-rs", "run", "--chip", "nRF51822_xxAA", "--log-format", "{L} {s}"] + +# uncomment ONE of these three option to make `cargo run` start a GDB session +# which option to pick depends on your system +#runner = "arm-none-eabi-gdb -q -x openocd.gdb" +# runner = "gdb-multiarch -q -x openocd.gdb" +# runner = "gdb -q -x openocd.gdb" + +rustflags = [ + # Previously, the linker arguments --nmagic and -Tlink.x were set here. + # They are now set by build.rs instead. The linker argument can still + # only be set here, if a custom linker is needed. + "-C", "linker=flip-link", + "-C", "link-arg=-Tdefmt.x", + # By default, the LLD linker is used, which is shipped with the Rust + # toolchain. If you run into problems with LLD, you can switch to the + # GNU linker by uncommenting this line: + # "-C", "linker=arm-none-eabi-ld", + + # If you need to link to pre-compiled C libraries provided by a C toolchain + # use GCC as the linker by uncommenting the three lines below: + # "-C", "linker=arm-none-eabi-gcc", + # "-C", "link-arg=-Wl,-Tlink.x", + # "-C", "link-arg=-nostartfiles", +] + +[build] +# Pick ONE of these default compilation targets +target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+ +# target = "thumbv7m-none-eabi" # Cortex-M3 +# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU) +# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU) +# target = "thumbv8m.base-none-eabi" # Cortex-M23 +# target = "thumbv8m.main-none-eabi" # Cortex-M33 (no FPU) +# target = "thumbv8m.main-none-eabihf" # Cortex-M33 (with FPU) diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..96ef6c0 --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +/target +Cargo.lock diff --git a/.idea/.gitignore b/.idea/.gitignore new file mode 100644 index 0000000..13566b8 --- /dev/null +++ b/.idea/.gitignore @@ -0,0 +1,8 @@ +# Default ignored files +/shelf/ +/workspace.xml +# Editor-based HTTP Client requests +/httpRequests/ +# Datasource local storage ignored files +/dataSources/ +/dataSources.local.xml diff --git a/.idea/customTargets.xml b/.idea/customTargets.xml new file mode 100644 index 0000000..db81084 --- /dev/null +++ b/.idea/customTargets.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/modules.xml b/.idea/modules.xml new file mode 100644 index 0000000..dbe530d --- /dev/null +++ b/.idea/modules.xml @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/.idea/runConfigurations/Build.xml b/.idea/runConfigurations/Build.xml new file mode 100644 index 0000000..cf0c363 --- /dev/null +++ b/.idea/runConfigurations/Build.xml @@ -0,0 +1,22 @@ + + + + \ No newline at end of file diff --git a/.idea/runConfigurations/Embed.xml b/.idea/runConfigurations/Embed.xml new file mode 100644 index 0000000..b2e4339 --- /dev/null +++ b/.idea/runConfigurations/Embed.xml @@ -0,0 +1,21 @@ + + + + \ No newline at end of file diff --git a/.idea/runConfigurations/_template__of_Cargo_Command.xml b/.idea/runConfigurations/_template__of_Cargo_Command.xml new file mode 100644 index 0000000..b8622a9 --- /dev/null +++ b/.idea/runConfigurations/_template__of_Cargo_Command.xml @@ -0,0 +1,21 @@ + + + + \ No newline at end of file diff --git a/.idea/runConfigurations/_template__of_com_jetbrains_cidr_embedded_openocd_conf_factory.xml b/.idea/runConfigurations/_template__of_com_jetbrains_cidr_embedded_openocd_conf_factory.xml new file mode 100644 index 0000000..0907646 --- /dev/null +++ b/.idea/runConfigurations/_template__of_com_jetbrains_cidr_embedded_openocd_conf_factory.xml @@ -0,0 +1,10 @@ + + + + + + + + + \ No newline at end of file diff --git a/.idea/test-microbit.iml b/.idea/test-microbit.iml new file mode 100644 index 0000000..c3cf374 --- /dev/null +++ b/.idea/test-microbit.iml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/tools/External Tools.xml b/.idea/tools/External Tools.xml new file mode 100644 index 0000000..655ae7c --- /dev/null +++ b/.idea/tools/External Tools.xml @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/vcs.xml b/.idea/vcs.xml new file mode 100644 index 0000000..35eb1dd --- /dev/null +++ b/.idea/vcs.xml @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 0000000..c684c24 --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,9 @@ +{ + // override the default setting (`cargo check --all-targets`) which produces the following error + // "can't find crate for `test`" when the default compilation target is a no_std target + // with these changes RA will call `cargo check --bins` on save + "rust-analyzer.checkOnSave.allTargets": false, + "rust-analyzer.checkOnSave.extraArgs": [ + "--bins" + ] +} diff --git a/Cargo.toml b/Cargo.toml new file mode 100644 index 0000000..d2079c6 --- /dev/null +++ b/Cargo.toml @@ -0,0 +1,84 @@ +[package] +authors = ["Lionel Sambuc "] +name = "template-microbit" +edition = "2021" +version = "0.1.0" + +[lib] +harness = false + +# needed for each integration test +[[test]] +name = "integration" +harness = false + +[dependencies.microbit-v2] +version = "0.15.1" +optional = true + +[dependencies.microbit] +version = "0.15.1" +optional = true + +[dependencies] +cortex-m = { version = "0.7", features = ["critical-section-single-core", "inline-asm"] } +cortex-m-rt = "0.7" +#cortex-m-semihosting = "0.5.0" +#panic-halt = "0.2.0" +panic-rtt-target = "0.1" + +defmt = "0.3" +# Either rtt-target or defmt-rtt +#rtt-target = "0.5" +defmt-rtt = "0.4" +panic-probe = { version = "0.3", features = ["print-defmt"] } + +embedded-hal = "1.0.0" +embedded-alloc = "0.6.0" + +[dev-dependencies] +defmt-test = "0.3" + +[features] +default = ["v1"] +v2 = ["microbit-v2"] +v1 = ["microbit"] + +# cargo build/run +[profile.dev] +codegen-units = 1 +debug = 2 +debug-assertions = true # <- +incremental = false +opt-level = 'z' # <- +overflow-checks = true # <- + +# cargo test +[profile.test] +codegen-units = 1 +debug = 2 +debug-assertions = true # <- +incremental = false +opt-level = 3 # <- +overflow-checks = true # <- + +# cargo build/run --release +[profile.release] +codegen-units = 1 +debug = 2 +debug-assertions = false # <- +incremental = false +lto = 'fat' +opt-level = 3 # <- +overflow-checks = false # <- + +# cargo test --release +[profile.bench] +codegen-units = 1 +debug = 2 +debug-assertions = false # <- +incremental = false +lto = 'fat' +opt-level = 3 # <- +overflow-checks = false # <- + diff --git a/Embed.toml b/Embed.toml new file mode 100644 index 0000000..9009309 --- /dev/null +++ b/Embed.toml @@ -0,0 +1,12 @@ +[default.general] +# chip = "nrf52833_xxAA" # uncomment this line for micro:bit V2 +chip = "nrf51822_xxAA" # uncomment this line for micro:bit V1 + +[default.reset] +halt_afterwards = true + +[default.rtt] +enabled = true + +[default.gdb] +enabled = false diff --git a/LICENSE-MIT b/LICENSE-MIT new file mode 100644 index 0000000..468cd79 --- /dev/null +++ b/LICENSE-MIT @@ -0,0 +1,23 @@ +Permission is hereby granted, free of charge, to any +person obtaining a copy of this software and associated +documentation files (the "Software"), to deal in the +Software without restriction, including without +limitation the rights to use, copy, modify, merge, +publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software +is furnished to do so, subject to the following +conditions: + +The above copyright notice and this permission notice +shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF +ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A +PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT +SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR +IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. \ No newline at end of file diff --git a/README.md b/README.md new file mode 100644 index 0000000..cb03593 --- /dev/null +++ b/README.md @@ -0,0 +1,67 @@ +# Template for `BBC micro:bit` + +This template as been setup for the BBC micro:bit. + +## Run + +You are now all set to `cargo-run` your first `defmt`-powered application! +There are some examples in the `src/bin` directory. + +Start by `cargo run`-ning `my-app/src/bin/hello.rs`: + +``` console +$ # `rb` is an alias for `run --bin` +$ cargo rb hello + Finished dev [optimized + debuginfo] target(s) in 0.03s +flashing program .. +DONE +resetting device +0.000000 INFO Hello, world! +(..) + +$ echo $? +0 +``` + +If you're running out of memory (`flip-link` bails with an overflow error), you can decrease the size of the device memory buffer by setting the `DEFMT_RTT_BUFFER_SIZE` environment variable. The default value is 1024 bytes, and powers of two should be used for optimal performance: + +``` console +$ DEFMT_RTT_BUFFER_SIZE=64 cargo rb hello +``` + +## Running tests + +The template comes configured for running unit tests and integration tests on the target. + +Unit tests reside in the library crate and can test private API; the initial set of unit tests are in `src/lib.rs`. +`cargo test --lib` will run those unit tests. + +``` console +$ cargo test --lib +(1/1) running `it_works`... +└─ app::unit_tests::__defmt_test_entry @ src/lib.rs:33 +all tests passed! +└─ app::unit_tests::__defmt_test_entry @ src/lib.rs:28 +``` + +Integration tests reside in the `tests` directory; the initial set of integration tests are in `tests/integration.rs`. +`cargo test --test integration` will run those integration tests. +Note that the argument of the `--test` flag must match the name of the test file in the `tests` directory. + +``` console +$ cargo test --test integration +(1/1) running `it_works`... +└─ integration::tests::__defmt_test_entry @ tests/integration.rs:13 +all tests passed! +└─ integration::tests::__defmt_test_entry @ tests/integration.rs:8 +``` + +Note that to add a new test file to the `tests` directory you also need to add a new `[[test]]` section to `Cargo.toml`. + +## Generated using app-template + +`app-template` is part of the [Knurling] project, [Ferrous Systems]' effort at +improving tooling used to develop for embedded systems. + +[Knurling]: https://knurling.ferrous-systems.com +[Ferrous Systems]: https://ferrous-systems.com/ diff --git a/SETUP.md b/SETUP.md new file mode 100644 index 0000000..752fe97 --- /dev/null +++ b/SETUP.md @@ -0,0 +1,29 @@ +# Install tools + +```shell +cargo install cargo-binutils +cargo install probe-rs-tools +rustup component add llvm-tools +``` + +## MacOS + +```shell +brew install arm-none-eabi-gdb picocom lsusb +``` + +## Other OSes + +Please refer to the instructions from: + +* Linux : https://docs.rust-embedded.org/discovery/microbit/03-setup/linux.html +* Windows : https://docs.rust-embedded.org/discovery/microbit/03-setup/windows.html + +# Verifying installation + +With the BBC micro:bit connected through USB: + +```shell +probe-rs list +probe-rs info +``` diff --git a/build.rs b/build.rs new file mode 100644 index 0000000..4f6cfd9 --- /dev/null +++ b/build.rs @@ -0,0 +1,43 @@ +//! This build script copies the `memory.x` file from the crate root into +//! a directory where the linker can always find it at build time. +//! For many projects this is optional, as the linker always searches the +//! project root directory -- wherever `Cargo.toml` is. However, if you +//! are using a workspace or have a more complicated build setup, this +//! build script becomes required. Additionally, by requesting that +//! Cargo re-run the build script whenever `memory.x` is changed, +//! updating `memory.x` ensures a rebuild of the application with the +//! new memory settings. +//! +//! The build script also sets the linker flags to tell it which link script to use. + +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; + +fn main() { + // Put `memory.x` in our output directory and ensure it's + // on the linker search path. + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("memory.x")) + .unwrap() + .write_all(include_bytes!("memory.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + + // By default, Cargo will re-run a build script whenever + // any file in the project changes. By specifying `memory.x` + // here, we ensure the build script is only re-run when + // `memory.x` is changed. + println!("cargo:rerun-if-changed=memory.x"); + + // Specify linker arguments. + + // `--nmagic` is required if memory section addresses are not aligned to 0x10000, + // for example the FLASH and RAM sections in your `memory.x`. + // See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 + println!("cargo:rustc-link-arg=--nmagic"); + + // Set the linker script to the one provided by cortex-m-rt. + println!("cargo:rustc-link-arg=-Tlink.x"); +} \ No newline at end of file diff --git a/examples/bitfield.rs b/examples/bitfield.rs new file mode 100644 index 0000000..abb2eb8 --- /dev/null +++ b/examples/bitfield.rs @@ -0,0 +1,13 @@ +#![no_main] +#![no_std] + +use template_microbit as _; // global logger + panicking-behavior + memory layout + +#[cortex_m_rt::entry] +fn main() -> ! { + // value of the FREQUENCY register (nRF52840 device; RADIO peripheral) + let frequency: u32 = 276; + defmt::info!("FREQUENCY: {0=0..7}, MAP: {0=8..9}", frequency); + + template_microbit::exit() +} diff --git a/examples/format.rs b/examples/format.rs new file mode 100644 index 0000000..31a357e --- /dev/null +++ b/examples/format.rs @@ -0,0 +1,29 @@ +#![no_main] +#![no_std] + +use template_microbit as _; // global logger + panicking-behavior + memory layout +use defmt::Format; // <- derive attribute + +#[derive(Format)] +struct S1 { + x: u8, + y: T, +} + +#[derive(Format)] +struct S2 { + z: u8, +} + +#[cortex_m_rt::entry] +fn main() -> ! { + let s = S1 { + x: 42, + y: S2 { z: 43 }, + }; + defmt::println!("s={:?}", s); + let x = 42; + defmt::println!("x={=u8}", x); + + template_microbit::exit() +} diff --git a/examples/hello.rs b/examples/hello.rs new file mode 100644 index 0000000..36d8bc1 --- /dev/null +++ b/examples/hello.rs @@ -0,0 +1,18 @@ +#![no_main] +#![no_std] + +// global logger + panicking-behavior + memory layout + +use microbit::board::Board; +use microbit::hal::gpio::Level::High; + +#[cortex_m_rt::entry] +fn main() -> ! { + let board = Board::take().unwrap(); + board.display_pins.col1.into_pulldown_input(); + board.display_pins.row1.into_push_pull_output(High); + + defmt::println!("Hello, world! freq ", ); + + template_microbit::exit() +} diff --git a/examples/levels.rs b/examples/levels.rs new file mode 100644 index 0000000..e0e5a6c --- /dev/null +++ b/examples/levels.rs @@ -0,0 +1,20 @@ +#![no_main] +#![no_std] + +use template_microbit as _; +use template_microbit::exit; +// global logger + panicking-behavior + memory layout + +#[cortex_m_rt::entry] +fn main() -> ! { + // try setting the DEFMT_LOG environment variable + // e.g. `export DEFMT_LOG=info` or `DEFMT_LOG=trace cargo rb levels` + defmt::info!("info"); + defmt::trace!("trace"); + defmt::warn!("warn"); + defmt::debug!("debug"); + defmt::error!("error"); + exit(); + + template_microbit::exit() +} diff --git a/examples/overflow.rs b/examples/overflow.rs new file mode 100644 index 0000000..fc433b0 --- /dev/null +++ b/examples/overflow.rs @@ -0,0 +1,28 @@ +#![no_main] +#![no_std] + +use template_microbit as _; // global logger + panicking-behavior + memory layout + +#[cortex_m_rt::entry] +fn main() -> ! { + ack(10, 10); + template_microbit::exit() +} + +fn ack(m: u32, n: u32) -> u32 { + // waste stack space to trigger a stack overflow + let mut buffer = [0u8; 16 * 1024]; + // estimate of the Stack Pointer register + let sp = buffer.as_mut_ptr(); + defmt::println!("ack(m={=u32}, n={=u32}, SP={:x})", m, n, sp); + + if m == 0 { + n + 1 + } else { + if n == 0 { + ack(m - 1, 1) + } else { + ack(m - 1, ack(m, n - 1)) + } + } +} diff --git a/examples/panic.rs b/examples/panic.rs new file mode 100644 index 0000000..6850984 --- /dev/null +++ b/examples/panic.rs @@ -0,0 +1,11 @@ +#![no_main] +#![no_std] + +use template_microbit as _; // global logger + panicking-behavior + memory layout + +#[cortex_m_rt::entry] +fn main() -> ! { + defmt::println!("main"); + + defmt::panic!() +} diff --git a/memory.x b/memory.x new file mode 100644 index 0000000..1c75909 --- /dev/null +++ b/memory.x @@ -0,0 +1,11 @@ +MEMORY +{ + /* NOTE K = KiBi = 1024 bytes */ + FLASH : ORIGIN = 0x00000000, LENGTH = 256K + RAM : ORIGIN = 0x20000000, LENGTH = 16K +} + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); diff --git a/nrf51.svd b/nrf51.svd new file mode 100644 index 0000000..27686a2 --- /dev/null +++ b/nrf51.svd @@ -0,0 +1,20978 @@ + + + + Nordic Semiconductor + Nordic + nrf51 + nrf51 + 522 + nRF51 reference description for radio MCU with ARM 32-bit Cortex-M0 Microcontroller at 16MHz CPU clock + +Copyright (c) 2010 - 2017, Nordic Semiconductor ASA\n +\n +All rights reserved.\n +\n +Redistribution and use in source and binary forms, with or without modification,\n +are permitted provided that the following conditions are met:\n +\n +1. Redistributions of source code must retain the above copyright notice, this\n + list of conditions and the following disclaimer.\n +\n +2. Redistributions in binary form, except as embedded into a Nordic\n + Semiconductor ASA integrated circuit in a product or a software update for\n + such product, must reproduce the above copyright notice, this list of\n + conditions and the following disclaimer in the documentation and/or other\n + materials provided with the distribution.\n +\n +3. Neither the name of Nordic Semiconductor ASA nor the names of its\n + contributors may be used to endorse or promote products derived from this\n + software without specific prior written permission.\n +\n +4. This software, with or without modification, must only be used with a\n + Nordic Semiconductor ASA integrated circuit.\n +\n +5. Any software provided in binary form under this license must not be reverse\n + engineered, decompiled, modified and/or disassembled.\n +\n +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS\n +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\n +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE\n +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\n +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\n +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n + + + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + + CM0 + r3p1 + little + 0 + 0 + 2 + 0 + + + system_nrf51 + NRF_ + + + 2048 + 2048 + 32 + + + + + + POWER + 522 + Power Control. + POWER + 0x40000000 + 32 + read-write + + + 0 + 0x1000 + registers + + + + POWER_CLOCK + 0 + + + + + TASKS_CONSTLAT + Enable constant latency mode. + 0x078 + write-only + + + TASKS_LOWPWR + Enable low power mode (variable latency). + 0x07C + write-only + + + + EVENTS_POFWARN + Power failure warning. + 0x108 + + + + INTENSET + Interrupt enable set register. + 0x304 + + + POFWARN + Enable interrupt on POFWARN event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + + + INTENCLR + Interrupt enable clear register. + 0x308 + + + POFWARN + Disable interrupt on POFWARN event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + + + + RESETREAS + Reset reason. + 0x400 + + + RESETPIN + Reset from pin-reset detected. + 0 0 + + + NotDetected + Reset not detected. + 0 + + + Detected + Reset detected. + 1 + + + + + DOG + Reset from watchdog detected. + 1 1 + + + NotDetected + Reset not detected. + 0 + + + Detected + Reset detected. + 1 + + + + + SREQ + Reset from AIRCR.SYSRESETREQ detected. + 2 2 + + + NotDetected + Reset not detected. + 0 + + + Detected + Reset detected. + 1 + + + + + LOCKUP + Reset from CPU lock-up detected. + 3 3 + + + NotDetected + Reset not detected. + 0 + + + Detected + Reset detected. + 1 + + + + + OFF + Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. + 16 16 + + + NotDetected + Reset not detected. + 0 + + + Detected + Reset detected. + 1 + + + + + LPCOMP + Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. + 17 17 + + + NotDetected + Reset not detected. + 0 + + + Detected + Reset detected. + 1 + + + + + DIF + Reset from wake-up from OFF mode detected by entering into debug interface mode. + 18 18 + + + NotDetected + Reset not detected. + 0 + + + Detected + Reset detected. + 1 + + + + + + + + RAMSTATUS + Ram status register. + 0x428 + read-only + + + RAMBLOCK0 + RAM block 0 status. + 0 0 + + + Off + RAM block 0 is off or powering up. + 0 + + + On + RAM block 0 is on. + 1 + + + + + RAMBLOCK1 + RAM block 1 status. + 1 1 + + + Off + RAM block 1 is off or powering up. + 0 + + + On + RAM block 1 is on. + 1 + + + + + RAMBLOCK2 + RAM block 2 status. + 2 2 + + + Off + RAM block 2 is off or powering up. + 0 + + + On + RAM block 2 is on. + 1 + + + + + RAMBLOCK3 + RAM block 3 status. + 3 3 + + + Off + RAM block 3 is off or powering up. + 0 + + + On + RAM block 3 is on. + 1 + + + + + + + + SYSTEMOFF + System off register. + 0x500 + write-only + + + SYSTEMOFF + Enter system off mode. + 0 0 + + + Enter + Enter system off mode. + 1 + + + + + + + + POFCON + Power failure configuration. + 0x510 + + + POF + Power failure comparator enable. + 0 0 + + + Disabled + Disabled. + 0 + + + Enabled + Enabled. + 1 + + + + + THRESHOLD + Set threshold level. + 1 2 + + + V21 + Set threshold to 2.1Volts. + 0x00 + + + V23 + Set threshold to 2.3Volts. + 0x01 + + + V25 + Set threshold to 2.5Volts. + 0x02 + + + V27 + Set threshold to 2.7Volts. + 0x03 + + + + + + + + GPREGRET + General purpose retention register. This register is a retained register. + 0x51C + + + GPREGRET + General purpose retention register. + 0 7 + + + + + + RAMON + Ram on/off. + 0x524 + 0x00000003 + + + ONRAM0 + RAM block 0 behaviour in ON mode. + 0 0 + + + RAM0Off + RAM block 0 OFF in ON mode. + 0 + + + RAM0On + RAM block 0 ON in ON mode. + 1 + + + + + ONRAM1 + RAM block 1 behaviour in ON mode. + 1 1 + + + RAM1Off + RAM block 1 OFF in ON mode. + 0 + + + RAM1On + RAM block 1 ON in ON mode. + 1 + + + + + OFFRAM0 + RAM block 0 behaviour in OFF mode. + 16 16 + + + RAM0Off + RAM block 0 OFF in OFF mode. + 0 + + + RAM0On + RAM block 0 ON in OFF mode. + 1 + + + + + OFFRAM1 + RAM block 1 behaviour in OFF mode. + 17 17 + + + RAM1Off + RAM block 1 OFF in OFF mode. + 0 + + + RAM1On + RAM block 1 ON in OFF mode. + 1 + + + + + + + + RESET + Pin reset functionality configuration register. This register is a retained register. + 0x544 + + + RESET + Enable or disable pin reset in debug interface mode. + 0 0 + + + Disabled + Pin reset in debug interface mode disabled. + 0 + + + Enabled + Pin reset in debug interface mode enabled. + 1 + + + + + + + + RAMONB + Ram on/off. + 0x554 + 0x00000003 + + + ONRAM2 + RAM block 2 behaviour in ON mode. + 0 0 + + + RAM2Off + RAM block 2 OFF in ON mode. + 0 + + + RAM2On + RAM block 2 ON in ON mode. + 1 + + + + + ONRAM3 + RAM block 3 behaviour in ON mode. + 1 1 + + + RAM3Off + RAM block 33 OFF in ON mode. + 0 + + + RAM3On + RAM block 3 ON in ON mode. + 1 + + + + + OFFRAM2 + RAM block 2 behaviour in OFF mode. + 16 16 + + + RAM2Off + RAM block 2 OFF in OFF mode. + 0 + + + RAM2On + RAM block 2 ON in OFF mode. + 1 + + + + + OFFRAM3 + RAM block 3 behaviour in OFF mode. + 17 17 + + + RAM3Off + RAM block 3 OFF in OFF mode. + 0 + + + RAM3On + RAM block 3 ON in OFF mode. + 1 + + + + + + + + DCDCEN + DCDC converter enable configuration register. + 0x578 + + + DCDCEN + Enable DCDC converter. + 0 0 + + + Disabled + DCDC converter disabled. + 0 + + + Enabled + DCDC converter enabled. + 1 + + + + + + + DCDCFORCE + DCDC power-up force register. + 0xA08 + + + FORCEOFF + DCDC power-up force off. + 0 0 + + + NoForce + No force. + 0 + + + Force + Force. + 1 + + + + + FORCEON + DCDC power-up force on. + 1 1 + + + NoForce + No force. + 0 + + + Force + Force. + 1 + + + + + + + + + + + CLOCK + 522 + Clock control. + CLOCK + 0x40000000 + 32 + read-write + POWER + + + 0 + 0x1000 + registers + + + + POWER_CLOCK + 0 + + + + + TASKS_HFCLKSTART + Start HFCLK clock source. + 0x000 + write-only + + + TASKS_HFCLKSTOP + Stop HFCLK clock source. + 0x004 + write-only + + + TASKS_LFCLKSTART + Start LFCLK clock source. + 0x008 + write-only + + + TASKS_LFCLKSTOP + Stop LFCLK clock source. + 0x00C + write-only + + + TASKS_CAL + Start calibration of LFCLK RC oscillator. + 0x010 + write-only + + + TASKS_CTSTART + Start calibration timer. + 0x014 + write-only + + + TASKS_CTSTOP + Stop calibration timer. + 0x018 + write-only + + + + EVENTS_HFCLKSTARTED + HFCLK oscillator started. + 0x100 + + + EVENTS_LFCLKSTARTED + LFCLK oscillator started. + 0x104 + + + EVENTS_DONE + Calibration of LFCLK RC oscillator completed. + 0x10C + + + EVENTS_CTTO + Calibration timer timeout. + 0x110 + + + + INTENSET + Interrupt enable set register. + 0x304 + + + HFCLKSTARTED + Enable interrupt on HFCLKSTARTED event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + LFCLKSTARTED + Enable interrupt on LFCLKSTARTED event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + DONE + Enable interrupt on DONE event. + 3 3 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + CTTO + Enable interrupt on CTTO event. + 4 4 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + + + INTENCLR + Interrupt enable clear register. + 0x308 + + + HFCLKSTARTED + Disable interrupt on HFCLKSTARTED event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + LFCLKSTARTED + Disable interrupt on LFCLKSTARTED event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + DONE + Disable interrupt on DONE event. + 3 3 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + CTTO + Disable interrupt on CTTO event. + 4 4 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + + + + HFCLKRUN + Task HFCLKSTART trigger status. + 0x408 + read-only + + + STATUS + Task HFCLKSTART trigger status. + 0 0 + + + NotTriggered + Task HFCLKSTART has not been triggered. + 0 + + + Triggered + Task HFCLKSTART has been triggered. + 1 + + + + + + + + HFCLKSTAT + High frequency clock status. + 0x40C + read-only + + + SRC + Active clock source for the HF clock. + 0 0 + + + RC + Internal 16MHz RC oscillator running and generating the HFCLK clock. + 0 + + + Xtal + External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. + 1 + + + + + STATE + State for the HFCLK. + 16 16 + + + NotRunning + HFCLK clock not running. + 0 + + + Running + HFCLK clock running. + 1 + + + + + + + + LFCLKRUN + Task LFCLKSTART triggered status. + 0x414 + read-only + + + STATUS + Task LFCLKSTART triggered status. + 0 0 + + + NotTriggered + Task LFCLKSTART has not been triggered. + 0 + + + Triggered + Task LFCLKSTART has been triggered. + 1 + + + + + + + + LFCLKSTAT + Low frequency clock status. + 0x418 + read-only + + + SRC + Active clock source for the LF clock. + 0 1 + + + RC + Internal 32KiHz RC oscillator running and generating the LFCLK clock. + 0 + + + Xtal + External 32KiHz crystal oscillator running and generating the LFCLK clock. + 1 + + + Synth + Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. + 2 + + + + + STATE + State for the LF clock. + 16 16 + + + NotRunning + LFCLK clock not running. + 0 + + + Running + LFCLK clock running. + 1 + + + + + + + + LFCLKSRCCOPY + Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. + 0x41C + read-only + + + SRC + Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. + 0 1 + + + RC + Internal 32KiHz RC oscillator. + 0 + + + Xtal + External 32KiHz crystal. + 1 + + + Synth + Internal 32KiHz synthesizer from HFCLK system clock. + 2 + + + + + + + + LFCLKSRC + Clock source for the LFCLK clock. + 0x518 + + + SRC + Clock source. + 0 1 + + + RC + Internal 32KiHz RC oscillator. + 0 + + + Xtal + External 32KiHz crystal. + 1 + + + Synth + Internal 32KiHz synthesizer from HFCLK system clock. + 2 + + + + + + + + CTIV + Calibration timer interval. + 0x538 + + + CTIV + Calibration timer interval in 0.25s resolution. + 0 6 + + + + + + XTALFREQ + Crystal frequency. + 0x550 + 0xFFFFFFFF + + + XTALFREQ + External Xtal frequency selection. + 0 7 + + + 16MHz + 16MHz xtal is used as source for the HFCLK oscillator. + 0xFF + + + 32MHz + 32MHz xtal is used as source for the HFCLK oscillator. + 0x00 + + + + + + + + + + MPU + 522 + Memory Protection Unit. + MPU + 0x40000000 + 32 + read-write + POWER + + + 0 + 0x1000 + registers + + + + + PERR0 + Configuration of peripherals in mpu regions. + 0x528 + + + POWER_CLOCK + POWER_CLOCK region configuration. + 0 0 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + RADIO + RADIO region configuration. + 1 1 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + UART0 + UART0 region configuration. + 2 2 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + SPI0_TWI0 + SPI0 and TWI0 region configuration. + 3 3 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + SPI1_TWI1 + SPI1 and TWI1 region configuration. + 4 4 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + GPIOTE + GPIOTE region configuration. + 6 6 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + ADC + ADC region configuration. + 7 7 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + TIMER0 + TIMER0 region configuration. + 8 8 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + TIMER1 + TIMER1 region configuration. + 9 9 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + TIMER2 + TIMER2 region configuration. + 10 10 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + RTC0 + RTC0 region configuration. + 11 11 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + TEMP + TEMP region configuration. + 12 12 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + RNG + RNG region configuration. + 13 13 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + ECB + ECB region configuration. + 14 14 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + CCM_AAR + CCM and AAR region configuration. + 15 15 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + WDT + WDT region configuration. + 16 16 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + RTC1 + RTC1 region configuration. + 17 17 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + QDEC + QDEC region configuration. + 18 18 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + LPCOMP + LPCOMP region configuration. + 19 19 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + NVMC + NVMC region configuration. + 30 30 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + PPI + PPI region configuration. + 31 31 + + + InRegion0 + Peripheral configured in region 0. + 1 + + + InRegion1 + Peripheral configured in region 1. + 0 + + + + + + + + RLENR0 + Length of RAM region 0. + 0x52C + + + + PROTENSET0 + Erase and write protection bit enable set register. + 0x600 + + + PROTREG0 + Protection enable for region 0. + 0 0 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG1 + Protection enable for region 1. + 1 1 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG2 + Protection enable for region 2. + 2 2 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG3 + Protection enable for region 3. + 3 3 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG4 + Protection enable for region 4. + 4 4 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG5 + Protection enable for region 5. + 5 5 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG6 + Protection enable for region 6. + 6 6 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG7 + Protection enable for region 7. + 7 7 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG8 + Protection enable for region 8. + 8 8 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG9 + Protection enable for region 9. + 9 9 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG10 + Protection enable for region 10. + 10 10 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG11 + Protection enable for region 11. + 11 11 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG12 + Protection enable for region 12. + 12 12 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG13 + Protection enable for region 13. + 13 13 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG14 + Protection enable for region 14. + 14 14 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG15 + Protection enable for region 15. + 15 15 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG16 + Protection enable for region 16. + 16 16 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG17 + Protection enable for region 17. + 17 17 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG18 + Protection enable for region 18. + 18 18 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG19 + Protection enable for region 19. + 19 19 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG20 + Protection enable for region 20. + 20 20 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG21 + Protection enable for region 21. + 21 21 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG22 + Protection enable for region 22. + 22 22 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG23 + Protection enable for region 23. + 23 23 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG24 + Protection enable for region 24. + 24 24 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG25 + Protection enable for region 25. + 25 25 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG26 + Protection enable for region 26. + 26 26 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG27 + Protection enable for region 27. + 27 27 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG28 + Protection enable for region 28. + 28 28 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG29 + Protection enable for region 29. + 29 29 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG30 + Protection enable for region 30. + 30 30 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG31 + Protection enable for region 31. + 31 31 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + + + + PROTENSET1 + Erase and write protection bit enable set register. + 0x604 + + + PROTREG32 + Protection enable for region 32. + 0 0 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG33 + Protection enable for region 33. + 1 1 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG34 + Protection enable for region 34. + 2 2 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG35 + Protection enable for region 35. + 3 3 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG36 + Protection enable for region 36. + 4 4 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG37 + Protection enable for region 37. + 5 5 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG38 + Protection enable for region 38. + 6 6 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG39 + Protection enable for region 39. + 7 7 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG40 + Protection enable for region 40. + 8 8 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG41 + Protection enable for region 41. + 9 9 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG42 + Protection enable for region 42. + 10 10 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG43 + Protection enable for region 43. + 11 11 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG44 + Protection enable for region 44. + 12 12 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG45 + Protection enable for region 45. + 13 13 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG46 + Protection enable for region 46. + 14 14 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG47 + Protection enable for region 47. + 15 15 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG48 + Protection enable for region 48. + 16 16 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG49 + Protection enable for region 49. + 17 17 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG50 + Protection enable for region 50. + 18 18 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG51 + Protection enable for region 51. + 19 19 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG52 + Protection enable for region 52. + 20 20 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG53 + Protection enable for region 53. + 21 21 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG54 + Protection enable for region 54. + 22 22 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG55 + Protection enable for region 55. + 23 23 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG56 + Protection enable for region 56. + 24 24 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG57 + Protection enable for region 57. + 25 25 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG58 + Protection enable for region 58. + 26 26 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG59 + Protection enable for region 59. + 27 27 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG60 + Protection enable for region 60. + 28 28 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG61 + Protection enable for region 61. + 29 29 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG62 + Protection enable for region 62. + 30 30 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + PROTREG63 + Protection enable for region 63. + 31 31 + + read + + Disabled + Protection disabled. + 0 + + + Enabled + Protection enabled. + 1 + + + + write + + Set + Enable protection on write. + 1 + + + + + + + + DISABLEINDEBUG + Disable erase and write protection mechanism in debug mode. + 0x608 + 0x00000001 + + + DISABLEINDEBUG + Disable protection mechanism in debug mode. + 0 0 + + + Enabled + Protection enabled. + 0 + + + Disabled + Protection disabled. + 1 + + + + + + + + PROTBLOCKSIZE + Erase and write protection block size. + 0x60C + + + PROTBLOCKSIZE + Erase and write protection block size. + 0 1 + + + 4k + Erase and write protection block size is 4k. + 0 + + + + + + + + + + + RADIO + 522 + The radio. + 0x40001000 + RADIO + 32 + read-write + + + 0 + 0x1000 + registers + + + + RADIO + 1 + + + + + TASKS_TXEN + Enable radio in TX mode. + 0x000 + write-only + + + TASKS_RXEN + Enable radio in RX mode. + 0x004 + write-only + + + TASKS_START + Start radio. + 0x008 + write-only + + + TASKS_STOP + Stop radio. + 0x00C + write-only + + + TASKS_DISABLE + Disable radio. + 0x010 + write-only + + + TASKS_RSSISTART + Start the RSSI and take one sample of the receive signal strength. + 0x014 + write-only + + + TASKS_RSSISTOP + Stop the RSSI measurement. + 0x018 + write-only + + + TASKS_BCSTART + Start the bit counter. + 0x01C + write-only + + + TASKS_BCSTOP + Stop the bit counter. + 0x020 + write-only + + + + EVENTS_READY + Ready event. + 0x100 + + + EVENTS_ADDRESS + Address event. + 0x104 + + + EVENTS_PAYLOAD + Payload event. + 0x108 + + + EVENTS_END + End event. + 0x10C + + + EVENTS_DISABLED + Disable event. + 0x110 + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet. + 0x114 + + + EVENTS_DEVMISS + No device address match occurred on the last received packet. + 0x118 + + + EVENTS_RSSIEND + Sampling of the receive signal strength complete. A new RSSI sample is ready for readout at the RSSISAMPLE register. + 0x11C + + + EVENTS_BCMATCH + Bit counter reached bit count value specified in BCC register. + 0x128 + + + + SHORTS + Shortcuts for the radio. + 0x200 + + + READY_START + Shortcut between READY event and START task. + 0 0 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + END_DISABLE + Shortcut between END event and DISABLE task. + 1 1 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + DISABLED_TXEN + Shortcut between DISABLED event and TXEN task. + 2 2 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + DISABLED_RXEN + Shortcut between DISABLED event and RXEN task. + 3 3 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + ADDRESS_RSSISTART + Shortcut between ADDRESS event and RSSISTART task. + 4 4 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + END_START + Shortcut between END event and START task. + 5 5 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + ADDRESS_BCSTART + Shortcut between ADDRESS event and BCSTART task. + 6 6 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + DISABLED_RSSISTOP + Shortcut between DISABLED event and RSSISTOP task. + 8 8 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + + + + INTENSET + Interrupt enable set register. + 0x304 + + + READY + Enable interrupt on READY event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + ADDRESS + Enable interrupt on ADDRESS event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + PAYLOAD + Enable interrupt on PAYLOAD event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + END + Enable interrupt on END event. + 3 3 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + DISABLED + Enable interrupt on DISABLED event. + 4 4 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + DEVMATCH + Enable interrupt on DEVMATCH event. + 5 5 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + DEVMISS + Enable interrupt on DEVMISS event. + 6 6 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + RSSIEND + Enable interrupt on RSSIEND event. + 7 7 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + BCMATCH + Enable interrupt on BCMATCH event. + 10 10 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + + + INTENCLR + Interrupt enable clear register. + 0x308 + + + READY + Disable interrupt on READY event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + ADDRESS + Disable interrupt on ADDRESS event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + PAYLOAD + Disable interrupt on PAYLOAD event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + END + Disable interrupt on END event. + 3 3 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + DISABLED + Disable interrupt on DISABLED event. + 4 4 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + DEVMATCH + Disable interrupt on DEVMATCH event. + 5 5 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + DEVMISS + Disable interrupt on DEVMISS event. + 6 6 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + RSSIEND + Disable interrupt on RSSIEND event. + 7 7 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + BCMATCH + Disable interrupt on BCMATCH event. + 10 10 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + + + + CRCSTATUS + CRC status of received packet. + 0x400 + read-only + + + CRCSTATUS + CRC status of received packet. + 0 0 + + + CRCError + Packet received with CRC error. + 0 + + + CRCOk + Packet received with CRC ok. + 1 + + + + + + + + RXMATCH + Received address. + 0x408 + read-only + + + RXMATCH + Logical address in which previous packet was received. + 0 2 + + + + + + RXCRC + Received CRC. + 0x40C + read-only + + + RXCRC + CRC field of previously received packet. + 0 23 + + + + + + DAI + Device address match index. + 0x410 + read-only + + + DAI + Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. + 0 2 + + + + + + PACKETPTR + Packet pointer. Decision point: START task. + 0x504 + + + + FREQUENCY + Frequency. + 0x508 + 0x00000002 + + + FREQUENCY + Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. + 0 6 + + + + + TXPOWER + Output power. + 0x50C + + + TXPOWER + Radio output power. Decision point: TXEN task. + 0 7 + + + Pos4dBm + +4dBm. + 0x04 + + + 0dBm + 0dBm. + 0x00 + + + Neg4dBm + -4dBm. + 0xFC + + + Neg8dBm + -8dBm. + 0xF8 + + + Neg12dBm + -12dBm. + 0xF4 + + + Neg16dBm + -16dBm. + 0xF0 + + + Neg20dBm + -20dBm. + 0xEC + + + Neg30dBm + -30dBm. + 0xD8 + + + + + + + MODE + Data rate and modulation. + 0x510 + + + MODE + Radio data rate and modulation setting. Decision point: TXEN or RXEN task. + 0 1 + + + Nrf_1Mbit + 1Mbit/s Nordic propietary radio mode. + 0x00 + + + Nrf_2Mbit + 2Mbit/s Nordic propietary radio mode. + 0x01 + + + Nrf_250Kbit + 250kbit/s Nordic propietary radio mode. + 0x02 + + + Ble_1Mbit + 1Mbit/s Bluetooth Low Energy + 0x03 + + + + + + + PCNF0 + Packet configuration 0. + 0x514 + + + LFLEN + Length of length field in number of bits. Decision point: START task. + 0 3 + + + S0LEN + Length of S0 field in number of bytes. Decision point: START task. + 8 8 + + + S1LEN + Length of S1 field in number of bits. Decision point: START task. + 16 19 + + + + + PCNF1 + Packet configuration 1. + 0x518 + + + MAXLEN + Maximum length of packet payload in number of bytes. + 0 7 + + + STATLEN + Static length in number of bytes. Decision point: START task. + 8 15 + + + BALEN + Base address length in number of bytes. Decision point: START task. + 16 18 + + + ENDIAN + On air endianness of packet length field. Decision point: START task. + 24 24 + + + Little + Least significant bit on air first + 0 + + + Big + Most significant bit on air first + 1 + + + + + WHITEEN + Packet whitening enable. + 25 25 + + + Disabled + Whitening disabled. + 0 + + + Enabled + Whitening enabled. + 1 + + + + + + + BASE0 + Radio base address 0. Decision point: START task. + 0x51C + + + BASE1 + Radio base address 1. Decision point: START task. + 0x520 + + + PREFIX0 + Prefixes bytes for logical addresses 0 to 3. + 0x524 + + + AP0 + Address prefix 0. Decision point: START task. + 0 7 + + + AP1 + Address prefix 1. Decision point: START task. + 8 15 + + + AP2 + Address prefix 2. Decision point: START task. + 16 23 + + + AP3 + Address prefix 3. Decision point: START task. + 24 31 + + + + + PREFIX1 + Prefixes bytes for logical addresses 4 to 7. + 0x528 + + + AP4 + Address prefix 4. Decision point: START task. + 0 7 + + + AP5 + Address prefix 5. Decision point: START task. + 8 15 + + + AP6 + Address prefix 6. Decision point: START task. + 16 23 + + + AP7 + Address prefix 7. Decision point: START task. + 24 31 + + + + + TXADDRESS + Transmit address select. + 0x52C + + + TXADDRESS + Logical address to be used when transmitting a packet. Decision point: START task. + 0 2 + + + + + RXADDRESSES + Receive address select. + 0x530 + + + ADDR0 + Enable reception on logical address 0. Decision point: START task. + 0 0 + + + Disabled + Reception disabled. + 0 + + + Enabled + Reception enabled. + 1 + + + + + ADDR1 + Enable reception on logical address 1. Decision point: START task. + 1 1 + + + Disabled + Reception disabled. + 0 + + + Enabled + Reception enabled. + 1 + + + + + ADDR2 + Enable reception on logical address 2. Decision point: START task. + 2 2 + + + Disabled + Reception disabled. + 0 + + + Enabled + Reception enabled. + 1 + + + + + ADDR3 + Enable reception on logical address 3. Decision point: START task. + 3 3 + + + Disabled + Reception disabled. + 0 + + + Enabled + Reception enabled. + 1 + + + + + ADDR4 + Enable reception on logical address 4. Decision point: START task. + 4 4 + + + Disabled + Reception disabled. + 0 + + + Enabled + Reception enabled. + 1 + + + + + ADDR5 + Enable reception on logical address 5. Decision point: START task. + 5 5 + + + Disabled + Reception disabled. + 0 + + + Enabled + Reception enabled. + 1 + + + + + ADDR6 + Enable reception on logical address 6. Decision point: START task. + 6 6 + + + Disabled + Reception disabled. + 0 + + + Enabled + Reception enabled. + 1 + + + + + ADDR7 + Enable reception on logical address 7. Decision point: START task. + 7 7 + + + Disabled + Reception disabled. + 0 + + + Enabled + Reception enabled. + 1 + + + + + + + CRCCNF + CRC configuration. + 0x534 + + + LEN + CRC length. Decision point: START task. + 0 1 + + + Disabled + CRC calculation disabled. + 0 + + + One + One byte long CRC. + 1 + + + Two + Two bytes long CRC. + 2 + + + Three + Three bytes long CRC. + 3 + + + + + SKIPADDR + Leave packet address field out of the CRC calculation. Decision point: START task. + 8 8 + + + Include + Include packet address in CRC calculation. + 0 + + + Skip + Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. + 1 + + + + + + + CRCPOLY + CRC polynomial. + 0x538 + + + CRCPOLY + CRC polynomial. Decision point: START task. + 0 23 + + + + + CRCINIT + CRC initial value. + 0x53C + + + CRCINIT + Initial value for CRC calculation. Decision point: START task. + 0 23 + + + + + TEST + Test features enable register. + 0x540 + + + CONSTCARRIER + Constant carrier. Decision point: TXEN task. + 0 0 + + + Disabled + Constant carrier disabled. + 0 + + + Enabled + Constant carrier enabled. + 1 + + + + + PLLLOCK + PLL lock. Decision point: TXEN or RXEN task. + 1 1 + + + Disabled + PLL lock disabled. + 0 + + + Enabled + PLL lock enabled. + 1 + + + + + + + + TIFS + Inter Frame Spacing in microseconds. + 0x544 + + + TIFS + Inter frame spacing in microseconds. Decision point: START rask + 0 7 + + + + + + RSSISAMPLE + RSSI sample. + 0x548 + read-only + + + RSSISAMPLE + RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm + 0 6 + + + + + STATE + Current radio state. + 0x550 + read-only + + + STATE + Current radio state. + 0 3 + + + Disabled + Radio is in the Disabled state. + 0x00 + + + RxRu + Radio is in the Rx Ramp Up state. + 0x01 + + + RxIdle + Radio is in the Rx Idle state. + 0x02 + + + Rx + Radio is in the Rx state. + 0x03 + + + RxDisable + Radio is in the Rx Disable state. + 0x04 + + + TxRu + Radio is in the Tx Ramp Up state. + 0x09 + + + TxIdle + Radio is in the Tx Idle state. + 0x0A + + + Tx + Radio is in the Tx state. + 0x0B + + + TxDisable + Radio is in the Tx Disable state. + 0x0C + + + + + + + DATAWHITEIV + Data whitening initial value. + 0x554 + 0x00000040 + + + DATAWHITEIV + Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. + 0 6 + + + + + + BCC + Bit counter compare. + 0x560 + + + + 8 + 0x04 + DAB[%s] + Device address base segment. + 0x600 + + + 8 + 0x04 + DAP[%s] + Device address prefix. + 0x620 + + + DAP + Device address prefix. + 0 15 + + + + + DACNF + Device address match configuration. + 0x640 + + + ENA0 + Enable or disable device address matching using device address 0. + 0 0 + + + Disabled + Disabled. + 0 + + + Enabled + Enabled. + 1 + + + + + ENA1 + Enable or disable device address matching using device address 1. + 1 1 + + + Disabled + Disabled. + 0 + + + Enabled + Enabled. + 1 + + + + + ENA2 + Enable or disable device address matching using device address 2. + 2 2 + + + Disabled + Disabled. + 0 + + + Enabled + Enabled. + 1 + + + + + ENA3 + Enable or disable device address matching using device address 3. + 3 3 + + + Disabled + Disabled. + 0 + + + Enabled + Enabled. + 1 + + + + + ENA4 + Enable or disable device address matching using device address 4. + 4 4 + + + Disabled + Disabled. + 0 + + + Enabled + Enabled. + 1 + + + + + ENA5 + Enable or disable device address matching using device address 5. + 5 5 + + + Disabled + Disabled. + 0 + + + Enabled + Enabled. + 1 + + + + + ENA6 + Enable or disable device address matching using device address 6. + 6 6 + + + Disabled + Disabled. + 0 + + + Enabled + Enabled. + 1 + + + + + ENA7 + Enable or disable device address matching using device address 7. + 7 7 + + + Disabled + Disabled. + 0 + + + Enabled + Enabled. + 1 + + + + + TXADD0 + TxAdd for device address 0. + 8 8 + + + TXADD1 + TxAdd for device address 1. + 9 9 + + + TXADD2 + TxAdd for device address 2. + 10 10 + + + TXADD3 + TxAdd for device address 3. + 11 11 + + + TXADD4 + TxAdd for device address 4. + 12 12 + + + TXADD5 + TxAdd for device address 5. + 13 13 + + + TXADD6 + TxAdd for device address 6. + 14 14 + + + TXADD7 + TxAdd for device address 7. + 15 15 + + + + + + OVERRIDE0 + Trim value override register 0. + 0x724 + + + OVERRIDE0 + Trim value override 0. + 0 31 + + + + + OVERRIDE1 + Trim value override register 1. + 0x728 + + + OVERRIDE1 + Trim value override 1. + 0 31 + + + + + OVERRIDE2 + Trim value override register 2. + 0x72C + + + OVERRIDE2 + Trim value override 2. + 0 31 + + + + + OVERRIDE3 + Trim value override register 3. + 0x730 + + + OVERRIDE3 + Trim value override 3. + 0 31 + + + + + OVERRIDE4 + Trim value override register 4. + 0x734 + + + OVERRIDE4 + Trim value override 4. + 0 27 + + + ENABLE + Enable or disable override of default trim values. + 31 31 + + + Disabled + Override trim values disabled. + 0 + + + Enabled + Override trim values enabled. + 1 + + + + + + + + POWER + Peripheral power control. + 0xFFC + + + POWER + Peripheral power control. + 0 0 + + + Disabled + Module power disabled. + 0 + + + Enabled + Module power enabled. + 1 + + + + + + + + + + + UART0 + 522 + Universal Asynchronous Receiver/Transmitter. + 0x40002000 + UART + 32 + read-write + UART + + + 0 + 0x1000 + registers + + + + UART0 + 2 + + + + + TASKS_STARTRX + Start UART receiver. + 0x000 + write-only + + + TASKS_STOPRX + Stop UART receiver. + 0x004 + write-only + + + TASKS_STARTTX + Start UART transmitter. + 0x008 + write-only + + + TASKS_STOPTX + Stop UART transmitter. + 0x00C + write-only + + + TASKS_SUSPEND + Suspend UART. + 0x01C + write-only + + + + EVENTS_CTS + CTS activated. + 0x100 + + + EVENTS_NCTS + CTS deactivated. + 0x104 + + + EVENTS_RXDRDY + Data received in RXD. + 0x108 + + + EVENTS_TXDRDY + Data sent from TXD. + 0x11C + + + EVENTS_ERROR + Error detected. + 0x124 + + + EVENTS_RXTO + Receiver timeout. + 0x144 + + + + SHORTS + Shortcuts for UART. + 0x200 + + + CTS_STARTRX + Shortcut between CTS event and STARTRX task. + 3 + 3 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + NCTS_STOPRX + Shortcut between NCTS event and STOPRX task. + 4 + 4 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + + + + INTENSET + Interrupt enable set register. + 0x304 + + + CTS + Enable interrupt on CTS event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + NCTS + Enable interrupt on NCTS event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + RXDRDY + Enable interrupt on RXRDY event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + TXDRDY + Enable interrupt on TXRDY event. + 7 7 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + ERROR + Enable interrupt on ERROR event. + 9 9 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + RXTO + Enable interrupt on RXTO event. + 17 17 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + + + INTENCLR + Interrupt enable clear register. + 0x308 + + + CTS + Disable interrupt on CTS event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + NCTS + Disable interrupt on NCTS event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + RXDRDY + Disable interrupt on RXRDY event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + TXDRDY + Disable interrupt on TXRDY event. + 7 7 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + ERROR + Disable interrupt on ERROR event. + 9 9 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + RXTO + Disable interrupt on RXTO event. + 17 17 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + + + + ERRORSRC + Error source. Write error field to 1 to clear error. + 0x480 + + + OVERRUN + A start bit is received while the previous data still lies in RXD. (Data loss). + 0 0 + + read + + NotPresent + Error not present. + 0 + + + Present + Error present. + 1 + + + + write + + Clear + Clear error on write. + 1 + + + + + PARITY + A character with bad parity is received. Only checked if HW parity control is enabled. + 1 1 + + read + + NotPresent + Error not present. + 0 + + + Present + Error present. + 1 + + + + write + + Clear + Clear error on write. + 1 + + + + + FRAMING + A valid stop bit is not detected on the serial data input after all bits in a character have been received. + 2 2 + + read + + NotPresent + Error not present. + 0 + + + Present + Error present. + 1 + + + + write + + Clear + Clear error on write. + 1 + + + + + BREAK + The serial data input is '0' for longer than the length of a data frame. + 3 3 + + read + + NotPresent + Error not present. + 0 + + + Present + Error present. + 1 + + + + write + + Clear + Clear error on write. + 1 + + + + + + + + ENABLE + Enable UART and acquire IOs. + 0x500 + + + ENABLE + Enable or disable UART and acquire IOs. + 0 2 + + + Disabled + UART disabled. + 0x00 + + + Enabled + UART enabled. + 0x04 + + + + + + + PSELRTS + Pin select for RTS. + 0x508 + 0xFFFFFFFF + + + PSELTXD + Pin select for TXD. + 0x50C + 0xFFFFFFFF + + + PSELCTS + Pin select for CTS. + 0x510 + 0xFFFFFFFF + + + PSELRXD + Pin select for RXD. + 0x514 + 0xFFFFFFFF + + + + RXD + RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. + 0x518 + read-only + modifyExternal + + + RXD + RX data from previous transfer. Double buffered. + 0 7 + + + + + TXD + TXD register. + 0x51C + write-only + + + TXD + TX data for transfer. + 0 7 + + + + + + BAUDRATE + UART Baudrate. + 0x524 + + + BAUDRATE + UART baudrate. + 0 31 + + + Baud1200 + 1200 baud. + 0x0004F000 + + + Baud2400 + 2400 baud. + 0x0009D000 + + + Baud4800 + 4800 baud. + 0x0013B000 + + + Baud9600 + 9600 baud. + 0x00275000 + + + Baud14400 + 14400 baud. + 0x003B0000 + + + Baud19200 + 19200 baud. + 0x004EA000 + + + Baud28800 + 28800 baud. + 0x0075F000 + + + Baud31250 + 31250 baud. + 0x00800000 + + + Baud38400 + 38400 baud. + 0x009D5000 + + + Baud56000 + 56000 baud. + 0x00E50000 + + + Baud57600 + 57600 baud. + 0x00EBF000 + + + Baud76800 + 76800 baud. + 0x013A9000 + + + Baud115200 + 115200 baud. + 0x01D7E000 + + + Baud230400 + 230400 baud. + 0x03AFB000 + + + Baud250000 + 250000 baud. + 0x04000000 + + + Baud460800 + 460800 baud. + 0x075F7000 + + + Baud921600 + 921600 baud. + 0x0EBED000 + + + Baud1M + 1M baud. + 0x10000000 + + + + + + + CONFIG + Configuration of parity and hardware flow control register. + 0x56C + + + HWFC + Hardware flow control. + 0 0 + + + Disabled + Hardware flow control disabled. + 0 + + + Enabled + Hardware flow control enabled. + 1 + + + + + PARITY + Include parity bit. + 1 3 + + + Excluded + Parity bit excluded. + 0 + + + Included + Parity bit included. + 7 + + + + + + + + POWER + Peripheral power control. + 0xFFC + + + POWER + Peripheral power control. + 0 0 + + + Disabled + Module power disabled. + 0 + + + Enabled + Module power enabled. + 1 + + + + + + + + + + + SPI0 + 522 + SPI master 0. + 0x40003000 + SPI + 32 + read-write + SPI + + + 0 + 0x1000 + registers + + + + SPI0_TWI0 + 3 + + + + + + EVENTS_READY + TXD byte sent and RXD byte received. + 0x108 + + + + INTENSET + Interrupt enable set register. + 0x304 + + + READY + Enable interrupt on READY event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + + + INTENCLR + Interrupt enable clear register. + 0x308 + + + READY + Disable interrupt on READY event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + + + + ENABLE + Enable SPI. + 0x500 + + + ENABLE + Enable or disable SPI. + 0 2 + + + Disabled + Disabled SPI. + 0x00 + + + Enabled + Enable SPI. + 0x01 + + + + + + + + PSELSCK + Pin select for SCK. + 0x508 + 0xFFFFFFFF + + + PSELMOSI + Pin select for MOSI. + 0x50C + 0xFFFFFFFF + + + PSELMISO + Pin select for MISO. + 0x510 + 0xFFFFFFFF + + + + RXD + RX data. + 0x518 + read-only + modifyExternal + + + RXD + RX data from last transfer. + 0 7 + + + + + TXD + TX data. + 0x51C + + + TXD + TX data for next transfer. + 0 7 + + + + + FREQUENCY + SPI frequency + 0x524 + 0x04000000 + + + FREQUENCY + SPI data rate. + 0 31 + + + K125 + 125kbps. + 0x02000000 + + + K250 + 250kbps. + 0x04000000 + + + K500 + 500kbps. + 0x08000000 + + + M1 + 1Mbps. + 0x10000000 + + + M2 + 2Mbps. + 0x20000000 + + + M4 + 4Mbps. + 0x40000000 + + + M8 + 8Mbps. + 0x80000000 + + + + + + + CONFIG + Configuration register. + 0x554 + + + ORDER + Bit order. + 0 0 + + + MsbFirst + Most significant bit transmitted out first. + 0 + + + LsbFirst + Least significant bit transmitted out first. + 1 + + + + + CPHA + Serial clock (SCK) phase. + 1 1 + + + Leading + Sample on leading edge of the clock. Shift serial data on trailing edge. + 0 + + + Trailing + Sample on trailing edge of the clock. Shift serial data on leading edge. + 1 + + + + + CPOL + Serial clock (SCK) polarity. + 2 2 + + + ActiveHigh + Active high. + 0 + + + ActiveLow + Active low. + 1 + + + + + + + + POWER + Peripheral power control. + 0xFFC + + + POWER + Peripheral power control. + 0 0 + + + Disabled + Module power disabled. + 0 + + + Enabled + Module power enabled. + 1 + + + + + + + + + + + TWI0 + 522 + Two-wire interface master 0. + 0x40003000 + TWI + 32 + read-write + TWI + SPI0 + + + 0 + 0x1000 + registers + + + + SPI0_TWI0 + 3 + + + + + TASKS_STARTRX + Start 2-Wire master receive sequence. + 0x000 + write-only + + + TASKS_STARTTX + Start 2-Wire master transmit sequence. + 0x008 + write-only + + + TASKS_STOP + Stop 2-Wire transaction. + 0x014 + write-only + + + TASKS_SUSPEND + Suspend 2-Wire transaction. + 0x01C + write-only + + + TASKS_RESUME + Resume 2-Wire transaction. + 0x020 + write-only + + + + EVENTS_STOPPED + Two-wire stopped. + 0x104 + + + EVENTS_RXDREADY + Two-wire ready to deliver new RXD byte received. + 0x108 + + + EVENTS_TXDSENT + Two-wire finished sending last TXD byte. + 0x11C + + + EVENTS_ERROR + Two-wire error detected. + 0x124 + + + EVENTS_BB + Two-wire byte boundary. + 0x138 + + + EVENTS_SUSPENDED + Two-wire suspended. + 0x148 + + + + SHORTS + Shortcuts for TWI. + 0x200 + + + BB_SUSPEND + Shortcut between BB event and the SUSPEND task. + 0 0 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + BB_STOP + Shortcut between BB event and the STOP task. + 1 1 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + + + + INTENSET + Interrupt enable set register. + 0x304 + + + STOPPED + Enable interrupt on STOPPED event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + RXDREADY + Enable interrupt on READY event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + TXDSENT + Enable interrupt on TXDSENT event. + 7 7 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + ERROR + Enable interrupt on ERROR event. + 9 9 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + BB + Enable interrupt on BB event. + 14 14 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + SUSPENDED + Enable interrupt on SUSPENDED event. + 18 18 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + + + INTENCLR + Interrupt enable clear register. + 0x308 + + + STOPPED + Disable interrupt on STOPPED event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + RXDREADY + Disable interrupt on RXDREADY event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + TXDSENT + Disable interrupt on TXDSENT event. + 7 7 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + ERROR + Disable interrupt on ERROR event. + 9 9 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + BB + Disable interrupt on BB event. + 14 14 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + SUSPENDED + Disable interrupt on SUSPENDED event. + 18 18 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + + + + ERRORSRC + Two-wire error source. Write error field to 1 to clear error. + 0x4C4 + + + OVERRUN + Byte received in RXD register before read of the last received byte (data loss). + 0 0 + + read + + NotPresent + Error not present. + 0 + + + Present + Error present. + 1 + + + + write + + Clear + Clear error on write. + 1 + + + + + ANACK + NACK received after sending the address. + 1 1 + + read + + NotPresent + Error not present. + 0 + + + Present + Error present. + 1 + + + + write + + Clear + Clear error on write. + 1 + + + + + DNACK + NACK received after sending a data byte. + 2 2 + + read + + NotPresent + Error not present. + 0 + + + Present + Error present. + 1 + + + + write + + Clear + Clear error on write. + 1 + + + + + + + + ENABLE + Enable two-wire master. + 0x500 + + + ENABLE + Enable or disable W2M + 0 2 + + + Disabled + Disabled. + 0x00 + + + Enabled + Enabled. + 0x05 + + + + + + + + PSELSCL + Pin select for SCL. + 0x508 + 0xFFFFFFFF + + + PSELSDA + Pin select for SDA. + 0x50C + 0xFFFFFFFF + + + + RXD + RX data register. + 0x518 + read-only + modifyExternal + + + RXD + RX data from last transfer. + 0 7 + + + + + TXD + TX data register. + 0x51C + + + TXD + TX data for next transfer. + 0 7 + + + + + FREQUENCY + Two-wire frequency. + 0x524 + 0x04000000 + + + FREQUENCY + Two-wire master clock frequency. + 0 31 + + + K100 + 100 kbps. + 0x01980000 + + + K250 + 250 kbps. + 0x04000000 + + + K400 + 400 kbps (actual rate 410.256 kbps). + 0x06680000 + + + + + + + + ADDRESS + Address used in the two-wire transfer. + 0x588 + + + ADDRESS + Two-wire address. + 0 6 + + + + + + POWER + Peripheral power control. + 0xFFC + + + POWER + Peripheral power control. + 0 0 + + + Disabled + Module power disabled. + 0 + + + Enabled + Module power enabled. + 1 + + + + + + + + + + + SPI1 + 522 + SPI master 1. + 0x40004000 + SPI + 32 + read-write + + SPI1_TWI1 + 4 + + + + + TWI1 + 522 + Two-wire interface master 1. + 0x40004000 + TWI + 32 + read-write + SPI1 + + SPI1_TWI1 + 4 + + + + + SPIS1 + 522 + SPI slave 1. + 0x40004000 + SPIS + 32 + read-write + SPI1 + SPIS + + + 0 + 0x1000 + registers + + + + SPI1_TWI1 + 4 + + + + + TASKS_ACQUIRE + Acquire SPI semaphore. + 0x024 + write-only + + + TASKS_RELEASE + Release SPI semaphore. + 0x028 + write-only + + + + EVENTS_END + Granted transaction completed. + 0x104 + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ACQUIRED + Semaphore acquired. + 0x128 + + + + SHORTS + Shortcuts for SPIS. + 0x200 + + + END_ACQUIRE + Shortcut between END event and the ACQUIRE task. + 2 2 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + + + + INTENSET + Interrupt enable set register. + 0x304 + + + END + Enable interrupt on END event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + ENDRX + enable interrupt on ENDRX event. + 4 + 4 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + ACQUIRED + Enable interrupt on ACQUIRED event. + 10 10 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + + + INTENCLR + Interrupt enable clear register. + 0x308 + + + END + Disable interrupt on END event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + ENDRX + Disable interrupt on ENDRX event. + 4 4 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + ACQUIRED + Disable interrupt on ACQUIRED event. + 10 10 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + + + + SEMSTAT + Semaphore status. + 0x400 + read-only + 0x00000001 + + + SEMSTAT + Semaphore status. + 0 1 + + + Free + Semaphore is free. + 0x00 + + + CPU + Semaphore is assigned to the CPU. + 0x01 + + + SPIS + Semaphore is assigned to the SPIS. + 0x02 + + + CPUPending + Semaphore is assigned to the SPIS, but a handover to the CPU is pending. + 0x03 + + + + + + + STATUS + Status from last transaction. + 0x440 + + + OVERREAD + TX buffer overread detected, and prevented. + 0 0 + + read + + NotPresent + Error not present. + 0 + + + Present + Error present. + 1 + + + + write + + Clear + Clear on write. + 1 + + + + + OVERFLOW + RX buffer overflow detected, and prevented. + 1 1 + + read + + NotPresent + Error not present. + 0 + + + Present + Error present. + 1 + + + + write + + Clear + Clear on write. + 1 + + + + + + + + ENABLE + Enable SPIS. + 0x500 + + + ENABLE + Enable or disable SPIS. + 0 2 + + + Disabled + Disabled SPIS. + 0x00 + + + Enabled + Enable SPIS. + 0x02 + + + + + + + + PSELSCK + Pin select for SCK. + 0x508 + 0xFFFFFFFF + + + PSELMISO + Pin select for MISO. + 0x50C + 0xFFFFFFFF + + + PSELMOSI + Pin select for MOSI. + 0x510 + 0xFFFFFFFF + + + PSELCSN + Pin select for CSN. + 0x514 + 0xFFFFFFFF + + + + RXDPTR + RX data pointer. + 0x534 + + + MAXRX + Maximum number of bytes in the receive buffer. + 0x538 + + + MAXRX + Maximum number of bytes in the receive buffer. + 0 7 + + + + + AMOUNTRX + Number of bytes received in last granted transaction. + 0x53C + read-only + + + AMOUNTRX + Number of bytes received in last granted transaction. + 0 7 + + + + + + TXDPTR + TX data pointer. + 0x544 + + + MAXTX + Maximum number of bytes in the transmit buffer. + 0x548 + + + MAXTX + Maximum number of bytes in the transmit buffer. + 0 7 + + + + + AMOUNTTX + Number of bytes transmitted in last granted transaction. + 0x54C + read-only + + + AMOUNTTX + Number of bytes transmitted in last granted transaction. + 0 7 + + + + + + CONFIG + Configuration register. + 0x554 + + + ORDER + Bit order. + 0 0 + + + MsbFirst + Most significant bit transmitted out first. + 0 + + + LsbFirst + Least significant bit transmitted out first. + 1 + + + + + CPHA + Serial clock (SCK) phase. + 1 1 + + + Leading + Sample on leading edge of the clock. Shift serial data on trailing edge. + 0 + + + Trailing + Sample on trailing edge of the clock. Shift serial data on leading edge. + 1 + + + + + CPOL + Serial clock (SCK) polarity. + 2 2 + + + ActiveHigh + Active high. + 0 + + + ActiveLow + Active low. + 1 + + + + + + + + DEF + Default character. + 0x55C + + + DEF + Default character. + 0 7 + + + + + ORC + Over-read character. + 0x5C0 + + + ORC + Over-read character. + 0 7 + + + + + + POWER + Peripheral power control. + 0xFFC + + + POWER + Peripheral power control. + 0 0 + + + Disabled + Module power disabled. + 0 + + + Enabled + Module power enabled. + 1 + + + + + + + + + + + GPIOTE + 522 + GPIO tasks and events. + 0x40006000 + GPIOTE + 32 + read-write + + + 0 + 0x1000 + registers + + + + GPIOTE + 6 + + + + + 4 + 0x04 + TASKS_OUT[%s] + Tasks asssociated with GPIOTE channels. + 0x000 + write-only + + + + 4 + 0x04 + EVENTS_IN[%s] + Tasks asssociated with GPIOTE channels. + 0x100 + + + EVENTS_PORT + Event generated from multiple pins. + 0x17C + + + + INTENSET + Interrupt enable set register. + 0x304 + + + IN0 + Enable interrupt on IN[0] event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + IN1 + Enable interrupt on IN[1] event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + IN2 + Enable interrupt on IN[2] event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + IN3 + Enable interrupt on IN[3] event. + 3 3 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + PORT + Enable interrupt on PORT event. + 31 31 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + + + INTENCLR + Interrupt enable clear register. + 0x308 + + + IN0 + Disable interrupt on IN[0] event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + IN1 + Disable interrupt on IN[1] event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + IN2 + Disable interrupt on IN[2] event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + IN3 + Disable interrupt on IN[3] event. + 3 3 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + PORT + Disable interrupt on PORT event. + 31 31 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + + + + 4 + 0x04 + CONFIG[%s] + Channel configuration registers. + 0x510 + + + MODE + Mode + 0 1 + + + Disabled + Disabled. + 0x00 + + + Event + Channel configure in event mode. + 0x01 + + + Task + Channel configure in task mode. + 0x03 + + + + + PSEL + Pin select. + 8 12 + + + POLARITY + Effects on output when in Task mode, or events on input that generates an event. + 16 17 + + + None + No task or event. + 0x00 + + + LoToHi + Low to high. + 0x01 + + + HiToLo + High to low. + 0x02 + + + Toggle + Toggle. + 0x03 + + + + + OUTINIT + Initial value of the output when the GPIOTE channel is configured as a Task. + 20 20 + + + Low + Initial low output when in task mode. + 0 + + + High + Initial high output when in task mode. + 1 + + + + + + + + POWER + Peripheral power control. + 0xFFC + + + POWER + Peripheral power control. + 0 0 + + + Disabled + Module power disabled. + 0 + + + Enabled + Module power enabled. + 1 + + + + + + + + + + + ADC + 522 + Analog to digital converter. + 0x40007000 + ADC + 32 + read-write + + + 0 + 0x1000 + registers + + + + ADC + 7 + + + + + TASKS_START + Start an ADC conversion. + 0x000 + write-only + + + TASKS_STOP + Stop ADC. + 0x004 + write-only + + + + EVENTS_END + ADC conversion complete. + 0x100 + + + + INTENSET + Interrupt enable set register. + 0x304 + + + END + Enable interrupt on END event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + + + INTENCLR + Interrupt enable clear register. + 0x308 + + + END + Disable interrupt on END event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + + + + BUSY + ADC busy register. + 0x400 + read-only + + + BUSY + ADC busy register. + 0 0 + + + Ready + No ongoing ADC conversion is taking place. ADC is ready. + 0 + + + Busy + An ADC conversion is taking place. ADC is busy. + 1 + + + + + + + + ENABLE + ADC enable. + 0x500 + + + ENABLE + ADC enable. + 0 1 + + + Disabled + ADC is disabled. + 0x00 + + + Enabled + ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. + 0x01 + + + + + + + + CONFIG + ADC configuration register. + 0x504 + 0x00000018 + + + RES + ADC resolution. + 0 1 + + + 8bit + 8bit ADC resolution. + 0x00 + + + 9bit + 9bit ADC resolution. + 0x01 + + + 10bit + 10bit ADC resolution. + 0x02 + + + + + INPSEL + ADC input selection. + 2 4 + + + AnalogInputNoPrescaling + Analog input specified by PSEL with no prescaling used as input for the conversion. + 0x00 + + + AnalogInputTwoThirdsPrescaling + Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. + 0x01 + + + AnalogInputOneThirdPrescaling + Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. + 0x02 + + + SupplyTwoThirdsPrescaling + Supply voltage with 2/3 prescaling used as input for the conversion. + 0x05 + + + SupplyOneThirdPrescaling + Supply voltage with 1/3 prescaling used as input for the conversion. + 0x06 + + + + + REFSEL + ADC reference selection. + 5 6 + + + VBG + Use internal 1.2V bandgap voltage as reference for conversion. + 0x00 + + + External + Use external source configured by EXTREFSEL as reference for conversion. + 0x01 + + + SupplyOneHalfPrescaling + Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. + 0x02 + + + SupplyOneThirdPrescaling + Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. + 0x03 + + + + + PSEL + ADC analog pin selection. + 8 15 + + + Disabled + Analog input pins disabled. + 0 + + + AnalogInput0 + Use analog input 0 as analog input. + 1 + + + AnalogInput1 + Use analog input 1 as analog input. + 2 + + + AnalogInput2 + Use analog input 2 as analog input. + 4 + + + AnalogInput3 + Use analog input 3 as analog input. + 8 + + AnalogInput4 + Use analog input 4 as analog input. + 16 + + + AnalogInput5 + Use analog input 5 as analog input. + 32 + + + AnalogInput6 + Use analog input 6 as analog input. + 64 + + + AnalogInput7 + Use analog input 7 as analog input. + 128 + + + + + EXTREFSEL + ADC external reference pin selection. + 16 17 + + + None + Analog external reference inputs disabled. + 0 + + + AnalogReference0 + Use analog reference 0 as reference. + 1 + + + AnalogReference1 + Use analog reference 1 as reference. + 2 + + + + + + + + RESULT + Result of ADC conversion. + 0x508 + read-only + + + RESULT + Result of ADC conversion. + 0 9 + + + + + + POWER + Peripheral power control. + 0xFFC + + + POWER + Peripheral power control. + 0 0 + + + Disabled + Module power disabled. + 0 + + + Enabled + Module power enabled. + 1 + + + + + + + + + + + TIMER0 + 522 + Timer 0. + 0x40008000 + TIMER + 32 + read-write + TIMER + + + + 0 + 0x1000 + registers + + + + TIMER0 + 8 + + + + + TASKS_START + Start Timer. + 0x000 + write-only + + + TASKS_STOP + Stop Timer. + 0x004 + write-only + + + TASKS_COUNT + Increment Timer (In counter mode). + 0x008 + write-only + + + TASKS_CLEAR + Clear timer. + 0x00C + write-only + + + TASKS_SHUTDOWN + Shutdown timer. + 0x010 + write-only + + + 4 + 0x04 + TASKS_CAPTURE[%s] + Capture Timer value to CC[n] registers. + 0x040 + write-only + + + + 4 + 0x04 + EVENTS_COMPARE[%s] + Compare event on CC[n] match. + 0x140 + + + + SHORTS + Shortcuts for Timer. + 0x200 + + + COMPARE0_CLEAR + Shortcut between CC[0] event and the CLEAR task. + 0 0 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + COMPARE1_CLEAR + Shortcut between CC[1] event and the CLEAR task. + 1 1 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + COMPARE2_CLEAR + Shortcut between CC[2] event and the CLEAR task. + 2 2 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + COMPARE3_CLEAR + Shortcut between CC[3] event and the CLEAR task. + 3 3 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + COMPARE0_STOP + Shortcut between CC[0] event and the STOP task. + 8 8 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + COMPARE1_STOP + Shortcut between CC[1] event and the STOP task. + 9 9 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + COMPARE2_STOP + Shortcut between CC[2] event and the STOP task. + 10 10 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + COMPARE3_STOP + Shortcut between CC[3] event and the STOP task. + 11 11 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + + + + INTENSET + Interrupt enable set register. + 0x304 + + + COMPARE0 + Enable interrupt on COMPARE[0] + 16 16 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + COMPARE1 + Enable interrupt on COMPARE[1] + 17 17 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + COMPARE2 + Enable interrupt on COMPARE[2] + 18 18 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + COMPARE3 + Enable interrupt on COMPARE[3] + 19 19 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + + + INTENCLR + Interrupt enable clear register. + 0x308 + + + COMPARE0 + Disable interrupt on COMPARE[0] + 16 16 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + COMPARE1 + Disable interrupt on COMPARE[1] + 17 17 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + COMPARE2 + Disable interrupt on COMPARE[2] + 18 18 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + COMPARE3 + Disable interrupt on COMPARE[3] + 19 19 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + + + + MODE + Timer Mode selection. + 0x504 + + + MODE + Select Normal or Counter mode. + 0 0 + + + Counter + Timer in Counter mode. + 1 + + + Timer + Timer in Normal mode. + 0 + + + + + + + + BITMODE + Sets timer behaviour. + 0x508 + + + BITMODE + Sets timer behaviour ro be like the implementation of a timer with width as indicated. + 0 1 + + + 16Bit + 16-bit timer behaviour. + 0x00 + + + 08Bit + 8-bit timer behaviour. + 0x01 + + + 24Bit + 24-bit timer behaviour. + 0x02 + + + 32Bit + 32-bit timer behaviour. + 0x03 + + + + + + + PRESCALER + 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. + 0x510 + 0x00000004 + + + PRESCALER + Timer PRESCALER value. Max value is 9. + 0 3 + + + + + + 4 + 0x04 + CC[%s] + Capture/compare registers. + 0x540 + + + + POWER + Peripheral power control. + 0xFFC + + + POWER + Peripheral power control. + 0 0 + + + Disabled + Module power disabled. + 0 + + + Enabled + Module power enabled. + 1 + + + + + + + + + + + TIMER1 + 522 + Timer 1. + 0x40009000 + TIMER + 32 + read-write + + TIMER1 + 9 + + + + + TIMER2 + 522 + Timer 2. + 0x4000A000 + TIMER + 32 + read-write + + TIMER2 + 10 + + + + + RTC0 + 522 + Real time counter 0. + 0x4000B000 + RTC + 32 + read-write + RTC + + + 0 + 0x1000 + registers + + + + RTC0 + 11 + + + + + TASKS_START + Start RTC Counter. + 0x000 + write-only + + + TASKS_STOP + Stop RTC Counter. + 0x004 + write-only + + + TASKS_CLEAR + Clear RTC Counter. + 0x008 + write-only + + + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFFFF0. + 0x00C + write-only + + + + EVENTS_TICK + Event on COUNTER increment. + 0x100 + + + EVENTS_OVRFLW + Event on COUNTER overflow. + 0x104 + + + 4 + 0x04 + EVENTS_COMPARE[%s] + Compare event on CC[n] match. + 0x140 + + + + INTENSET + Interrupt enable set register. + 0x304 + + + TICK + Enable interrupt on TICK event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + OVRFLW + Enable interrupt on OVRFLW event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + COMPARE0 + Enable interrupt on COMPARE[0] event. + 16 16 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + COMPARE1 + Enable interrupt on COMPARE[1] event. + 17 17 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + COMPARE2 + Enable interrupt on COMPARE[2] event. + 18 18 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + COMPARE3 + Enable interrupt on COMPARE[3] event. + 19 19 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + + + INTENCLR + Interrupt enable clear register. + 0x308 + + + TICK + Disable interrupt on TICK event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + OVRFLW + Disable interrupt on OVRFLW event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + COMPARE0 + Disable interrupt on COMPARE[0] event. + 16 16 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + COMPARE1 + Disable interrupt on COMPARE[1] event. + 17 17 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + COMPARE2 + Disable interrupt on COMPARE[2] event. + 18 18 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + COMPARE3 + Disable interrupt on COMPARE[3] event. + 19 19 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + + + + EVTEN + Configures event enable routing to PPI for each RTC event. + 0x340 + + + TICK + TICK event enable. + 0 0 + + + Disabled + Event disabled. + 0 + + + Enabled + Event enabled. + 1 + + + + + OVRFLW + OVRFLW event enable. + 1 1 + + + Disabled + Event disabled. + 0 + + + Enabled + Event enabled. + 1 + + + + + COMPARE0 + COMPARE[0] event enable. + 16 16 + + + Disabled + Event disabled. + 0 + + + Enabled + Event enabled. + 1 + + + + + COMPARE1 + COMPARE[1] event enable. + 17 17 + + + Disabled + Event disabled. + 0 + + + Enabled + Event enabled. + 1 + + + + + COMPARE2 + COMPARE[2] event enable. + 18 18 + + + Disabled + Event disabled. + 0 + + + Enabled + Event enabled. + 1 + + + + + COMPARE3 + COMPARE[3] event enable. + 19 19 + + + Disabled + Event disabled. + 0 + + + Enabled + Event enabled. + 1 + + + + + + + EVTENSET + Enable events routing to PPI. The reading of this register gives the value of EVTEN. + 0x344 + + + TICK + Enable routing to PPI of TICK event. + 0 0 + + read + + Disabled + Event disabled. + 0 + + + Enabled + Event enabled. + 1 + + + + write + + Set + Enable event on write. + 1 + + + + + OVRFLW + Enable routing to PPI of OVRFLW event. + 1 1 + + read + + Disabled + Event disabled. + 0 + + + Enabled + Event enabled. + 1 + + + + write + + Set + Enable event on write. + 1 + + + + + COMPARE0 + Enable routing to PPI of COMPARE[0] event. + 16 16 + + read + + Disabled + Event disabled. + 0 + + + Enabled + Event enabled. + 1 + + + + write + + Set + Enable event on write. + 1 + + + + + COMPARE1 + Enable routing to PPI of COMPARE[1] event. + 17 17 + + read + + Disabled + Event disabled. + 0 + + + Enabled + Event enabled. + 1 + + + + write + + Set + Enable event on write. + 1 + + + + + COMPARE2 + Enable routing to PPI of COMPARE[2] event. + 18 18 + + read + + Disabled + Event disabled. + 0 + + + Enabled + Event enabled. + 1 + + + + write + + Set + Enable event on write. + 1 + + + + + COMPARE3 + Enable routing to PPI of COMPARE[3] event. + 19 19 + + read + + Disabled + Event disabled. + 0 + + + Enabled + Event enabled. + 1 + + + + write + + Set + Enable event on write. + 1 + + + + + + + EVTENCLR + Disable events routing to PPI. The reading of this register gives the value of EVTEN. + 0x348 + + + TICK + Disable routing to PPI of TICK event. + 0 0 + + read + + Disabled + Event disabled. + 0 + + + Enabled + Event enabled. + 1 + + + + write + + Clear + Disable event on write. + 1 + + + + + OVRFLW + Disable routing to PPI of OVRFLW event. + 1 1 + + read + + Disabled + Event disabled. + 0 + + + Enabled + Event enabled. + 1 + + + + write + + Clear + Disable event on write. + 1 + + + + + COMPARE0 + Disable routing to PPI of COMPARE[0] event. + 16 16 + + read + + Disabled + Event disabled. + 0 + + + Enabled + Event enabled. + 1 + + + + write + + Clear + Disable event on write. + 1 + + + + + COMPARE1 + Disable routing to PPI of COMPARE[1] event. + 17 17 + + read + + Disabled + Event disabled. + 0 + + + Enabled + Event enabled. + 1 + + + + write + + Clear + Disable event on write. + 1 + + + + + COMPARE2 + Disable routing to PPI of COMPARE[2] event. + 18 18 + + read + + Disabled + Event disabled. + 0 + + + Enabled + Event enabled. + 1 + + + + write + + Clear + Disable event on write. + 1 + + + + + COMPARE3 + Disable routing to PPI of COMPARE[3] event. + 19 19 + + read + + Disabled + Event disabled. + 0 + + + Enabled + Event enabled. + 1 + + + + write + + Clear + Disable event on write. + 1 + + + + + + + + COUNTER + Current COUNTER value. + 0x504 + read-only + + + COUNTER + Counter value. + 0 23 + + + + + + PRESCALER + 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. + 0x508 + + + PRESCALER + RTC PRESCALER value. + 0 11 + + + + + + 4 + 0x04 + CC[%s] + Capture/compare registers. + 0x540 + + + COMPARE + Compare value. + 0 23 + + + + + + POWER + Peripheral power control. + 0xFFC + + + POWER + Peripheral power control. + 0 0 + + + Disabled + Module power disabled. + 0 + + + Enabled + Module power enabled. + 1 + + + + + + + + + + + TEMP + 522 + Temperature Sensor. + TEMP + 0x4000C000 + 32 + read-write + + + 0 + 0x1000 + registers + + + + TEMP + 12 + + + + + TASKS_START + Start temperature measurement. + 0x000 + write-only + + + TASKS_STOP + Stop temperature measurement. + 0x004 + write-only + + + + EVENTS_DATARDY + Temperature measurement complete, data ready event. + 0x100 + + + + INTENSET + Interrupt enable set register. + 0x304 + + + DATARDY + Enable interrupt on DATARDY event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + + + INTENCLR + Interrupt enable clear register. + 0x308 + + + DATARDY + Disable interrupt on DATARDY event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + + + + TEMP + Die temperature in degC, 2's complement format, 0.25 degC pecision. + 0x508 + read-only + int32_t + + + + POWER + Peripheral power control. + 0xFFC + + + POWER + Peripheral power control. + 0 0 + + + Disabled + Module power disabled. + 0 + + + Enabled + Module power enabled. + 1 + + + + + + + + + + + RNG + 522 + Random Number Generator. + 0x4000D000 + RNG + 32 + read-write + + + 0 + 0x1000 + registers + + + + RNG + 13 + + + + + TASKS_START + Start the random number generator. + 0x000 + write-only + + + TASKS_STOP + Stop the random number generator. + 0x004 + write-only + + + + EVENTS_VALRDY + New random number generated and written to VALUE register. + 0x100 + + + + SHORTS + Shortcuts for the RNG. + 0x200 + + + VALRDY_STOP + Shortcut between VALRDY event and STOP task. + 0 0 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + + + + INTENSET + Interrupt enable set register + 0x304 + + + VALRDY + Enable interrupt on VALRDY event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + + + INTENCLR + Interrupt enable clear register + 0x308 + + + VALRDY + Disable interrupt on VALRDY event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + + + + CONFIG + Configuration register. + 0x504 + + + DERCEN + Digital error correction enable. + 0 0 + + + Disabled + Digital error correction disabled. + 0 + + + Enabled + Digital error correction enabled. + 1 + + + + + + + + VALUE + RNG random number. + 0x508 + read-only + + + VALUE + Generated random number. + 0 7 + + + + + + POWER + Peripheral power control. + 0xFFC + + + POWER + Peripheral power control. + 0 0 + + + Disabled + Module power disabled. + 0 + + + Enabled + Module power enabled. + 1 + + + + + + + + + + + ECB + 522 + AES ECB Mode Encryption. + 0x4000E000 + ECB + 32 + read-write + + + 0 + 0x1000 + registers + + + + ECB + 14 + + + + + TASKS_STARTECB + Start ECB block encrypt. If a crypto operation is running, this will not initiate a new encryption and the ERRORECB event will be triggered. + 0x000 + write-only + + + TASKS_STOPECB + Stop current ECB encryption. If a crypto operation is running, this will will trigger the ERRORECB event. + 0x004 + write-only + + + + EVENTS_ENDECB + ECB block encrypt complete. + 0x100 + + + EVENTS_ERRORECB + ECB block encrypt aborted due to a STOPECB task or due to an error. + 0x104 + + + + INTENSET + Interrupt enable set register. + 0x304 + + + ENDECB + Enable interrupt on ENDECB event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + ERRORECB + Enable interrupt on ERRORECB event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + + + INTENCLR + Interrupt enable clear register. + 0x308 + + + ENDECB + Disable interrupt on ENDECB event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + ERRORECB + Disable interrupt on ERRORECB event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + + + + ECBDATAPTR + ECB block encrypt memory pointer. + 0x504 + + + + POWER + Peripheral power control. + 0xFFC + + + POWER + Peripheral power control. + 0 0 + + + Disabled + Module power disabled. + 0 + + + Enabled + Module power enabled. + 1 + + + + + + + + + + + AAR + 522 + Accelerated Address Resolver. + 0x4000F000 + AAR + 32 + read-write + + + 0 + 0x1000 + registers + + + + CCM_AAR + 15 + + + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure. + 0x000 + write-only + + + TASKS_STOP + Stop resolving addresses. + 0x008 + write-only + + + + EVENTS_END + Address resolution procedure completed. + 0x100 + + + EVENTS_RESOLVED + Address resolved. + 0x104 + + + EVENTS_NOTRESOLVED + Address not resolved. + 0x108 + + + + + INTENSET + Interrupt enable set register. + 0x304 + + + END + Enable interrupt on END event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + RESOLVED + Enable interrupt on RESOLVED event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + NOTRESOLVED + Enable interrupt on NOTRESOLVED event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + + + INTENCLR + Interrupt enable clear register. + 0x308 + + + END + Disable interrupt on ENDKSGEN event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + RESOLVED + Disable interrupt on RESOLVED event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + NOTRESOLVED + Disable interrupt on NOTRESOLVED event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + + + + STATUS + Resolution status. + 0x400 + read-only + + + STATUS + The IRK used last time an address was resolved. + 0 3 + + + + + + ENABLE + Enable AAR. + 0x500 + + + ENABLE + Enable AAR. + 0 1 + + + Disabled + Disabled AAR. + 0x00 + + + Enabled + Enable AAR. + 0x03 + + + + + + + + NIRK + Number of Identity root Keys in the IRK data structure. + 0x504 + 0x00000001 + + + NIRK + Number of Identity root Keys in the IRK data structure. + 0 4 + + + + + + IRKPTR + Pointer to the IRK data structure. + 0x508 + + + ADDRPTR + Pointer to the resolvable address (6 bytes). + 0x510 + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during resolution. A minimum of 3 bytes must be reserved. + 0x514 + + + + POWER + Peripheral power control. + 0xFFC + + + POWER + Peripheral power control. + 0 0 + + + Disabled + Module power disabled. + 0 + + + Enabled + Module power enabled. + 1 + + + + + + + + + + + CCM + 522 + AES CCM Mode Encryption. + 0x4000F000 + CCM + 32 + read-write + AAR + + + 0 + 0x1000 + registers + + + + CCM_AAR + 15 + + + + + TASKS_KSGEN + Start generation of key-stream. This operation will stop by itself when completed. + 0x000 + write-only + + + TASKS_CRYPT + Start encrypt/decrypt. This operation will stop by itself when completed. + 0x004 + write-only + + + TASKS_STOP + Stop encrypt/decrypt. + 0x008 + write-only + + + + EVENTS_ENDKSGEN + Keystream generation completed. + 0x100 + + + EVENTS_ENDCRYPT + Encrypt/decrypt completed. + 0x104 + + + EVENTS_ERROR + Error happened. + 0x108 + + + + SHORTS + Shortcuts for the CCM. + 0x200 + + + ENDKSGEN_CRYPT + Shortcut between ENDKSGEN event and CRYPT task. + 0 0 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + + + + INTENSET + Interrupt enable set register. + 0x304 + + + ENDKSGEN + Enable interrupt on ENDKSGEN event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + ENDCRYPT + Enable interrupt on ENDCRYPT event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + ERROR + Enable interrupt on ERROR event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + + + INTENCLR + Interrupt enable clear register. + 0x308 + + + ENDKSGEN + Disable interrupt on ENDKSGEN event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + ENDCRYPT + Disable interrupt on ENDCRYPT event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + ERROR + Disable interrupt on ERROR event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + + + + MICSTATUS + CCM RX MIC check result. + 0x400 + read-only + + + MICSTATUS + Result of the MIC check performed during the previous CCM RX STARTCRYPT + 0 0 + + + CheckFailed + MIC check failed. + 0 + + + CheckPassed + MIC check passed. + 1 + + + + + + + + ENABLE + CCM enable. + 0x500 + + + ENABLE + CCM enable. + 0 1 + + + Disabled + CCM is disabled. + 0x00 + + + Enabled + CCM is enabled. + 0x02 + + + + + + + + MODE + Operation mode. + 0x504 + 0x00000001 + + + MODE + CCM mode operation. + 0 0 + + + Encryption + CCM mode TX + 0 + + + Decryption + CCM mode TX + 1 + + + + + + + + CNFPTR + Pointer to a data structure holding AES key and NONCE vector. + 0x508 + + + INPTR + Pointer to the input packet. + 0x50C + + + OUTPTR + Pointer to the output packet. + 0x510 + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during resolution. A minimum of 43 bytes must be reserved. + 0x514 + + + + POWER + Peripheral power control. + 0xFFC + + + POWER + Peripheral power control. + 0 0 + + + Disabled + Module power disabled. + 0 + + + Enabled + Module power enabled. + 1 + + + + + + + + + + + WDT + 522 + Watchdog Timer. + WDT + 0x40010000 + 32 + read-write + + + 0 + 0x1000 + registers + + + + WDT + 16 + + + + + TASKS_START + Start the watchdog. + 0x000 + write-only + + + + EVENTS_TIMEOUT + Watchdog timeout. + 0x100 + + + + INTENSET + Interrupt enable set register. + 0x304 + + + TIMEOUT + Enable interrupt on TIMEOUT event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + + + INTENCLR + Interrupt enable clear register. + 0x308 + + + TIMEOUT + Disable interrupt on TIMEOUT event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + + + + RUNSTATUS + Watchdog running status. + 0x400 + read-only + + + RUNSTATUS + Watchdog running status. + 0 0 + + + NotRunning + Watchdog timer is not running. + 0 + + + Running + Watchdog timer is running. + 1 + + + + + + + + REQSTATUS + Request status. + 0x404 + 0x00000001 + read-only + + + RR0 + Request status for RR[0]. + 0 0 + + + DisabledOrRequested + RR[0] register is not enabled or has already requested reload. + 0 + + + EnabledAndUnrequested + RR[0] register is enabled and has not jet requested. + 1 + + + + + RR1 + Request status for RR[1]. + 1 1 + + + DisabledOrRequested + RR[1] register is not enabled or has already requested reload. + 0 + + + EnabledAndUnrequested + RR[1] register is enabled and has not jet requested. + 1 + + + + + RR2 + Request status for RR[2]. + 2 2 + + + DisabledOrRequested + RR[2] register is not enabled or has already requested reload. + 0 + + + EnabledAndUnrequested + RR[2] register is enabled and has not jet requested. + 1 + + + + + RR3 + Request status for RR[3]. + 3 3 + + + DisabledOrRequested + RR[3] register is not enabled or has already requested reload. + 0 + + + EnabledAndUnrequested + RR[3] register is enabled and has not jet requested. + 1 + + + + + RR4 + Request status for RR[4]. + 4 4 + + + DisabledOrRequested + RR[4] register is not enabled or has already requested reload. + 0 + + + EnabledAndUnrequested + RR[4] register is enabled and has not jet requested. + 1 + + + + + RR5 + Request status for RR[5]. + 5 5 + + + DisabledOrRequested + RR[5] register is not enabled or has already requested reload. + 0 + + + EnabledAndUnrequested + RR[5] register is enabled and has not jet requested. + 1 + + + + + RR6 + Request status for RR[6]. + 6 6 + + + DisabledOrRequested + RR[6] register is not enabled or has already requested reload. + 0 + + + EnabledAndUnrequested + RR[6] register is enabled and has not jet requested. + 1 + + + + + RR7 + Request status for RR[7]. + 7 7 + + + DisabledOrRequested + RR[7] register is not enabled or has already requested reload. + 0 + + + EnabledAndUnrequested + RR[7] register is enabled and has not jet requested. + 1 + + + + + + + + CRV + Counter reload value in number of 32kiHz clock cycles. + 0x504 + 0xFFFFFFFF + + + + RREN + Reload request enable. + 0x508 + 0x00000001 + + + RR0 + Enable or disable RR[0] register. + 0 0 + + + Disabled + RR[0] register is disabled. + 0 + + + Enabled + RR[0] register is enabled. + 1 + + + + + RR1 + Enable or disable RR[1] register. + 1 1 + + + Disabled + RR[1] register is disabled. + 0 + + + Enabled + RR[1] register is enabled. + 1 + + + + + RR2 + Enable or disable RR[2] register. + 2 2 + + + Disabled + RR[2] register is disabled. + 0 + + + Enabled + RR[2] register is enabled. + 1 + + + + + RR3 + Enable or disable RR[3] register. + 3 3 + + + Disabled + RR[3] register is disabled. + 0 + + + Enabled + RR[3] register is enabled. + 1 + + + + + RR4 + Enable or disable RR[4] register. + 4 4 + + + Disabled + RR[4] register is disabled. + 0 + + + Enabled + RR[4] register is enabled. + 1 + + + + + RR5 + Enable or disable RR[5] register. + 5 5 + + + Disabled + RR[5] register is disabled. + 0 + + + Enabled + RR[5] register is enabled. + 1 + + + + + RR6 + Enable or disable RR[6] register. + 6 6 + + + Disabled + RR[6] register is disabled. + 0 + + + Enabled + RR[6] register is enabled. + 1 + + + + + RR7 + Enable or disable RR[7] register. + 7 7 + + + Disabled + RR[7] register is disabled. + 0 + + + Enabled + RR[7] register is enabled. + 1 + + + + + + + + CONFIG + Configuration register. + 0x50C + 0x00000001 + + + SLEEP + Configure the watchdog to pause or not while the CPU is sleeping. + 0 0 + + + Pause + Pause watchdog while the CPU is asleep. + 0 + + + Run + Do not pause watchdog while the CPU is asleep. + 1 + + + + + HALT + Configure the watchdog to pause or not while the CPU is halted by the debugger. + 3 3 + + + Pause + Pause watchdog while the CPU is halted by the debugger. + 0 + + + Run + Do not pause watchdog while the CPU is halted by the debugger. + 1 + + + + + + + + 8 + 0x04 + RR[%s] + Reload requests registers. + 0x600 + write-only + + + RR + Reload register. + 0 31 + + + Reload + Value to request a reload of the watchdog timer. + 0x6E524635 + + + + + + + + POWER + Peripheral power control. + 0xFFC + + + POWER + Peripheral power control. + 0 0 + + + Disabled + Module power disabled. + 0 + + + Enabled + Module power enabled. + 1 + + + + + + + + + + + RTC1 + 522 + Real time counter 1. + 0x40011000 + RTC + 32 + read-write + + RTC1 + 17 + + + + + QDEC + 522 + Rotary decoder. + QDEC + 0x40012000 + 32 + read-write + + + 0 + 0x1000 + registers + + + + QDEC + 18 + + + + + TASKS_START + Start the quadrature decoder. + 0x000 + write-only + + + TASKS_STOP + Stop the quadrature decoder. + 0x004 + write-only + + + TASKS_READCLRACC + Transfers the content from ACC registers to ACCREAD registers, and clears the ACC registers. + 0x008 + write-only + + + + EVENTS_SAMPLERDY + A new sample is written to the sample register. + 0x100 + + + EVENTS_REPORTRDY + REPORTPER number of samples accumulated in ACC register, and ACC register different than zero. + 0x104 + + + EVENTS_ACCOF + ACC or ACCDBL register overflow. + 0x108 + + + + SHORTS + Shortcuts for the QDEC. + 0x200 + + + REPORTRDY_READCLRACC + Shortcut between REPORTRDY event and READCLRACC task. + 0 0 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + SAMPLERDY_STOP + Shortcut between SAMPLERDY event and STOP task. + 1 1 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + + + + INTENSET + Interrupt enable set register. + 0x304 + + + SAMPLERDY + Enable interrupt on SAMPLERDY event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + REPORTRDY + Enable interrupt on REPORTRDY event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + ACCOF + Enable interrupt on ACCOF event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + + + INTENCLR + Interrupt enable clear register. + 0x308 + + + SAMPLERDY + Disable interrupt on SAMPLERDY event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + REPORTRDY + Disable interrupt on REPORTRDY event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + ACCOF + Disable interrupt on ACCOF event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + + + + ENABLE + Enable the QDEC. + 0x500 + + + ENABLE + Enable or disable QDEC. + 0 0 + + + Disabled + Disabled QDEC. + 0 + + + Enabled + Enable QDEC. + 1 + + + + + + + + LEDPOL + LED output pin polarity. + 0x504 + + + LEDPOL + LED output pin polarity. + 0 0 + + + ActiveLow + LED output is active low. + 0 + + + ActiveHigh + LED output is active high. + 1 + + + + + + + + SAMPLEPER + Sample period. + 0x508 + + + SAMPLEPER + Sample period. + 0 2 + + + 128us + 128us sample period. + 0x00 + + + 256us + 256us sample period. + 0x01 + + + 512us + 512us sample period. + 0x02 + + + 1024us + 1024us sample period. + 0x03 + + + 2048us + 2048us sample period. + 0x04 + + + 4096us + 4096us sample period. + 0x05 + + + 8192us + 8192us sample period. + 0x06 + + + 16384us + 16384us sample period. + 0x07 + + + + + + + + SAMPLE + Motion sample value. + 0x50C + read-only + int32_t + + + SAMPLE + Last sample taken in compliment to 2. + 0 31 + + + + + + REPORTPER + Number of samples to generate an EVENT_REPORTRDY. + 0x510 + + + REPORTPER + Number of samples to generate an EVENT_REPORTRDY. + 0 2 + + + 10Smpl + 10 samples per report. + 0x00 + + + 40Smpl + 40 samples per report. + 0x01 + + + 80Smpl + 80 samples per report. + 0x02 + + + 120Smpl + 120 samples per report. + 0x03 + + + 160Smpl + 160 samples per report. + 0x04 + + + 200Smpl + 200 samples per report. + 0x05 + + + 240Smpl + 240 samples per report. + 0x06 + + + 280Smpl + 280 samples per report. + 0x07 + + + + + + + + ACC + Accumulated valid transitions register. + 0x514 + read-only + int32_t + + + + ACCREAD + Snapshot of ACC register. Value generated by the TASKS_READCLEACC task. + 0x518 + read-only + int32_t + + + + PSELLED + Pin select for LED output. + 0x51C + 0xFFFFFFFF + + + PSELA + Pin select for phase A input. + 0x520 + 0xFFFFFFFF + + + PSELB + Pin select for phase B input. + 0x524 + 0xFFFFFFFF + + + + DBFEN + Enable debouncer input filters. + 0x528 + + + DBFEN + Enable debounce input filters. + 0 0 + + + Disabled + Debounce input filters disabled. + 0 + + + Enabled + Debounce input filters enabled. + 1 + + + + + + + + LEDPRE + Time LED is switched ON before the sample. + 0x540 + 0x00000010 + + + LEDPRE + Period in us the LED in switched on prior to sampling. + 0 8 + + + + + + ACCDBL + Accumulated double (error) transitions register. + 0x544 + read-only + + + ACCDBL + Accumulated double (error) transitions. + 0 3 + + + + + + ACCDBLREAD + Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. + 0x548 + read-only + + + ACCDBLREAD + Snapshot of accumulated double (error) transitions. + 0 3 + + + + + + POWER + Peripheral power control. + 0xFFC + + + POWER + Peripheral power control. + 0 0 + + + Disabled + Module power disabled. + 0 + + + Enabled + Module power enabled. + 1 + + + + + + + + + + + LPCOMP + 522 + Low power comparator. + LPCOMP + 0x40013000 + 32 + read-write + + + 0 + 0x1000 + registers + + + + LPCOMP + 19 + + + + + TASKS_START + Start the comparator. + 0x000 + write-only + + + TASKS_STOP + Stop the comparator. + 0x004 + write-only + + + TASKS_SAMPLE + Sample comparator value. + 0x008 + write-only + + + + EVENTS_READY + LPCOMP is ready and output is valid. + 0x100 + + + EVENTS_DOWN + Input voltage crossed the threshold going down. + 0x104 + + + EVENTS_UP + Input voltage crossed the threshold going up. + 0x108 + + + EVENTS_CROSS + Input voltage crossed the threshold in any direction. + 0x10C + + + + SHORTS + Shortcuts for the LPCOMP. + 0x200 + + + READY_SAMPLE + Shortcut between READY event and SAMPLE task. + 0 0 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + READY_STOP + Shortcut between RADY event and STOP task. + 1 1 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + DOWN_STOP + Shortcut between DOWN event and STOP task. + 2 2 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + UP_STOP + Shortcut between UP event and STOP task. + 3 3 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + CROSS_STOP + Shortcut between CROSS event and STOP task. + 4 4 + + + Disabled + Shortcut disabled. + 0 + + + Enabled + Shortcut enabled. + 1 + + + + + + + + INTENSET + Interrupt enable set register. + 0x304 + + + READY + Enable interrupt on READY event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + DOWN + Enable interrupt on DOWN event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + UP + Enable interrupt on UP event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + CROSS + Enable interrupt on CROSS event. + 3 3 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Set + Enable interrupt on write. + 1 + + + + + + + INTENCLR + Interrupt enable clear register. + 0x308 + + + READY + Disable interrupt on READY event. + 0 0 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + DOWN + Disable interrupt on DOWN event. + 1 1 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + UP + Disable interrupt on UP event. + 2 2 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + CROSS + Disable interrupt on CROSS event. + 3 3 + + read + + Disabled + Interrupt disabled. + 0 + + + Enabled + Interrupt enabled. + 1 + + + + write + + Clear + Disable interrupt on write. + 1 + + + + + + + + RESULT + Result of last compare. + 0x400 + read-only + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 0 + + + Below + Input voltage is bellow the reference threshold. + 0 + + + Above + Input voltage is above the reference threshold. + 1 + + + + + + + + ENABLE + Enable the LPCOMP. + 0x500 + + + ENABLE + Enable or disable LPCOMP. + 0 1 + + + Disabled + Disabled LPCOMP. + 0x00 + + + Enabled + Enable LPCOMP. + 0x01 + + + + + + + + PSEL + Input pin select. + 0x504 + + + PSEL + Analog input pin select. + 0 2 + + + AnalogInput0 + Use analog input 0 as analog input. + 0 + + + AnalogInput1 + Use analog input 1 as analog input. + 1 + + + AnalogInput2 + Use analog input 2 as analog input. + 2 + + AnalogInput3 + Use analog input 3 as analog input. + 3 + + + AnalogInput4 + Use analog input 4 as analog input. + 4 + + + AnalogInput5 + Use analog input 5 as analog input. + 5 + + + AnalogInput6 + Use analog input 6 as analog input. + 6 + + + AnalogInput7 + Use analog input 7 as analog input. + 7 + + + + + + + + REFSEL + Reference select. + 0x508 + + + REFSEL + Reference select. + 0 2 + + + SupplyOneEighthPrescaling + Use supply with a 1/8 prescaler as reference. + 0 + + + SupplyTwoEighthsPrescaling + Use supply with a 2/8 prescaler as reference. + 1 + + + SupplyThreeEighthsPrescaling + Use supply with a 3/8 prescaler as reference. + 2 + + + SupplyFourEighthsPrescaling + Use supply with a 4/8 prescaler as reference. + 3 + + + SupplyFiveEighthsPrescaling + Use supply with a 5/8 prescaler as reference. + 4 + + + SupplySixEighthsPrescaling + Use supply with a 6/8 prescaler as reference. + 5 + + + SupplySevenEighthsPrescaling + Use supply with a 7/8 prescaler as reference. + 6 + + + ARef + Use external analog reference as reference. + 7 + + + + + + + + EXTREFSEL + External reference select. + 0x50C + + + EXTREFSEL + External analog reference pin selection. + 0 0 + + + AnalogReference0 + Use analog reference 0 as reference. + 0 + + + AnalogReference1 + Use analog reference 1 as reference. + 1 + + + + + + + + ANADETECT + Analog detect configuration. + 0x520 + + + ANADETECT + Analog detect configuration. + 0 1 + + + Cross + Generate ANADETEC on crossing, both upwards and downwards crossing. + 0 + + + Up + Generate ANADETEC on upwards crossing only. + 1 + + + Down + Generate ANADETEC on downwards crossing only. + 2 + + + + + + + + POWER + Peripheral power control. + 0xFFC + + + POWER + Peripheral power control. + 0 0 + + + Disabled + Module power disabled. + 0 + + + Enabled + Module power enabled. + 1 + + + + + + + + + + + SWI + 522 + SW Interrupts. + SWI + 0x40014000 + 32 + + + 0 + 0x6000 + registers + + + + SWI0 + 20 + + + SWI1 + 21 + + + SWI2 + 22 + + + SWI3 + 23 + + + SWI4 + 24 + + + SWI5 + 25 + + + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + + NVMC + 522 + Non Volatile Memory Controller. + NVMC + 0x4001E000 + 32 + read-write + + + 0 + 0x1000 + registers + + + + + READY + Ready flag. + 0x400 + read-only + + + READY + NVMC ready. + 0 0 + + + Busy + NVMC is busy (on-going write or erase operation). + 0 + + + Ready + NVMC is ready. + 1 + + + + + + + + CONFIG + Configuration register. + 0x504 + + + WEN + Program write enable. + 0 1 + + + Ren + Read only access. + 0x00 + + + Wen + Write enabled. + 0x01 + + + Een + Erase enabled. + 0x02 + + + + + + + + ERASEPAGE + Register for erasing a non-protected non-volatile memory page. + 0x508 + + + ERASEPCR1 + Register for erasing a non-protected non-volatile memory page. + 0x508 + ERASEPAGE + + + + ERASEALL + Register for erasing all non-volatile user memory. + 0x50C + + + ERASEALL + Starts the erasing of all user NVM (code region 0/1 and UICR registers). + 0 0 + + + NoOperation + No operation. + 0 + + + Erase + Start chip erase. + 1 + + + + + + + + ERASEPCR0 + Register for erasing a protected non-volatile memory page. + 0x510 + + + + ERASEUICR + Register for start erasing User Information Congfiguration Registers. + 0x514 + + + ERASEUICR + It can only be used when all contents of code region 1 are erased. + 0 0 + + + NoOperation + No operation. + 0 + + + Erase + Start UICR erase. + 1 + + + + + + + + + + PPI + 522 + PPI controller. + 0x4001F000 + PPI + 32 + read-write + + + 0 + 0x1000 + registers + + + + + 4 + 0x08 + TASKS_CHG[%s] + Channel group tasks. + 0x000 + + EN + Enable channel group. + 0x000 + write-only + + + DIS + Disable channel group. + 0x004 + write-only + + + + + CHEN + Channel enable. + 0x500 + + + CH0 + Enable PPI channel 0. + 0 0 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH1 + Enable PPI channel 1. + 1 1 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH2 + Enable PPI channel 2. + 2 2 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH3 + Enable PPI channel 3. + 3 3 + + + Disabled + Channel disabled + 0 + + + Enabled + Channel enabled + 1 + + + + + CH4 + Enable PPI channel 4. + 4 4 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH5 + Enable PPI channel 5. + 5 5 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH6 + Enable PPI channel 6. + 6 6 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH7 + Enable PPI channel 7. + 7 7 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH8 + Enable PPI channel 8. + 8 8 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH9 + Enable PPI channel 9. + 9 9 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH10 + Enable PPI channel 10. + 10 10 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH11 + Enable PPI channel 11. + 11 11 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH12 + Enable PPI channel 12. + 12 12 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH13 + Enable PPI channel 13. + 13 13 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH14 + Enable PPI channel 14. + 14 14 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH15 + Enable PPI channel 15. + 15 15 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH20 + Enable PPI channel 20. + 20 20 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH21 + Enable PPI channel 21. + 21 21 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH22 + Enable PPI channel 22. + 22 22 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH23 + Enable PPI channel 23. + 23 23 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH24 + Enable PPI channel 24. + 24 24 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH25 + Enable PPI channel 25. + 25 25 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH26 + Enable PPI channel 26. + 26 26 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH27 + Enable PPI channel 27. + 27 27 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH28 + Enable PPI channel 28. + 28 28 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH29 + Enable PPI channel 29. + 29 29 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH30 + Enable PPI channel 30. + 30 30 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + CH31 + Enable PPI channel 31. + 31 31 + + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + + + + CHENSET + Channel enable set. + 0x504 + + + CH0 + Enable PPI channel 0. + 0 0 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH1 + Enable PPI channel 1. + 1 1 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH2 + Enable PPI channel 2. + 2 2 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH3 + Enable PPI channel 3. + 3 3 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH4 + Enable PPI channel 4. + 4 4 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH5 + Enable PPI channel 5. + 5 5 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH6 + Enable PPI channel 6. + 6 6 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH7 + Enable PPI channel 7. + 7 7 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH8 + Enable PPI channel 8. + 8 8 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH9 + Enable PPI channel 9. + 9 9 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH10 + Enable PPI channel 10. + 10 10 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH11 + Enable PPI channel 11. + 11 11 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH12 + Enable PPI channel 12. + 12 12 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH13 + Enable PPI channel 13. + 13 13 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH14 + Enable PPI channel 14. + 14 14 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH15 + Enable PPI channel 15. + 15 15 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH20 + Enable PPI channel 20. + 20 20 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH21 + Enable PPI channel 21. + 21 21 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH22 + Enable PPI channel 22. + 22 22 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH23 + Enable PPI channel 23. + 23 23 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH24 + Enable PPI channel 24. + 24 24 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH25 + Enable PPI channel 25. + 25 25 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH26 + Enable PPI channel 26. + 26 26 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH27 + Enable PPI channel 27. + 27 27 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH28 + Enable PPI channel 28. + 28 28 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH29 + Enable PPI channel 29. + 29 29 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH30 + Enable PPI channel 30. + 30 30 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + CH31 + Enable PPI channel 31. + 31 31 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Set + Enable channel on write. + 1 + + + + + + + CHENCLR + Channel enable clear. + 0x508 + + + CH0 + Disable PPI channel 0. + 0 0 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH1 + Disable PPI channel 1. + 1 1 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH2 + Disable PPI channel 2. + 2 2 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH3 + Disable PPI channel 3. + 3 3 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH4 + Disable PPI channel 4. + 4 4 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH5 + Disable PPI channel 5. + 5 5 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH6 + Disable PPI channel 6. + 6 6 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH7 + Disable PPI channel 7. + 7 7 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH8 + Disable PPI channel 8. + 8 8 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH9 + Disable PPI channel 9. + 9 9 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH10 + Disable PPI channel 10. + 10 10 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH11 + Disable PPI channel 11. + 11 11 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH12 + Disable PPI channel 12. + 12 12 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH13 + Disable PPI channel 13. + 13 13 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH14 + Disable PPI channel 14. + 14 14 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH15 + Disable PPI channel 15. + 15 15 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH20 + Disable PPI channel 20. + 20 20 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH21 + Disable PPI channel 21. + 21 21 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH22 + Disable PPI channel 22. + 22 22 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH23 + Disable PPI channel 23. + 23 23 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH24 + Disable PPI channel 24. + 24 24 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH25 + Disable PPI channel 25. + 25 25 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH26 + Disable PPI channel 26. + 26 26 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH27 + Disable PPI channel 27. + 27 27 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH28 + Disable PPI channel 28. + 28 28 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH29 + Disable PPI channel 29. + 29 29 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH30 + Disable PPI channel 30. + 30 30 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + CH31 + Disable PPI channel 31. + 31 31 + + read + + Disabled + Channel disabled. + 0 + + + Enabled + Channel enabled. + 1 + + + + write + + Clear + Disable channel on write. + 1 + + + + + + + + 16 + 0x08 + CH[%s] + PPI Channel. + 0x510 + + EEP + Channel event end-point. + 0x000 + + + TEP + Channel task end-point. + 0x004 + + + + + 4 + 0x04 + CHG[%s] + Channel group configuration. + 0x800 + + + CH0 + Include CH0 in channel group. + 0 0 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH1 + Include CH1 in channel group. + 1 1 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH2 + Include CH2 in channel group. + 2 2 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH3 + Include CH3 in channel group. + 3 3 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH4 + Include CH4 in channel group. + 4 4 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH5 + Include CH5 in channel group. + 5 5 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH6 + Include CH6 in channel group. + 6 6 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH7 + Include CH7 in channel group. + 7 7 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH8 + Include CH8 in channel group. + 8 8 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH9 + Include CH9 in channel group. + 9 9 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH10 + Include CH10 in channel group. + 10 10 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH11 + Include CH11 in channel group. + 11 11 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH12 + Include CH12 in channel group. + 12 12 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH13 + Include CH13 in channel group. + 13 13 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH14 + Include CH14 in channel group. + 14 14 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH15 + Include CH15 in channel group. + 15 15 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH20 + Include CH20 in channel group. + 20 20 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH21 + Include CH21 in channel group. + 21 21 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH22 + Include CH22 in channel group. + 22 22 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH23 + Include CH23 in channel group. + 23 23 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH24 + Include CH24 in channel group. + 24 24 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH25 + Include CH25 in channel group. + 25 25 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH26 + Include CH26 in channel group. + 26 26 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH27 + Include CH27 in channel group. + 27 27 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH28 + Include CH28 in channel group. + 28 28 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH29 + Include CH29 in channel group. + 29 29 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH30 + Include CH30 in channel group. + 30 30 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + CH31 + Include CH31 in channel group. + 31 31 + + + Excluded + Channel excluded. + 0 + + + Included + Channel included. + 1 + + + + + + + + + + + FICR + 522 + Factory Information Configuration. + FICR + 0x10000000 + 32 + read-only + 0xFFFFFFFF + + + 0 + 0x1000 + registers + + + + + CODEPAGESIZE + Code memory page size in bytes. + 0x010 + + + CODESIZE + Code memory size in pages. + 0x014 + + + + CLENR0 + Length of code region 0 in bytes. + 0x028 + + + PPFC + Pre-programmed factory code present. + 0x02C + + + PPFC + Pre-programmed factory code present. + 0 7 + + + NotPresent + Not present. + 0xFF + + + Present + Present. + 0x00 + + + + + + + + NUMRAMBLOCK + Number of individualy controllable RAM blocks. + 0x034 + + + SIZERAMBLOCKS + Size of RAM blocks in bytes. + 0x038 + + + 4 + 0x04 + SIZERAMBLOCK[%s] + Deprecated array of size of RAM block in bytes. This name is kept for backward compatinility purposes. Use SIZERAMBLOCKS instead. + 0x038 + SIZERAMBLOCKS + + + + CONFIGID + Configuration identifier. + 0x05C + + + HWID + Hardware Identification Number. + 0 15 + + + FWID + Firmware Identification Number pre-loaded into the flash. + 16 31 + + + + + + 2 + 0x04 + DEVICEID[%s] + Device identifier. + 0x060 + + + + 4 + 0x04 + ER[%s] + Encryption root. + 0x080 + + + + 4 + 0x04 + IR[%s] + Identity root. + 0x090 + + + + DEVICEADDRTYPE + Device address type. + 0x0A0 + + + DEVICEADDRTYPE + Device address type. + 0 0 + + + Public + Public address. + 0 + + + Random + Random address. + 1 + + + + + + + + 2 + 0x04 + DEVICEADDR[%s] + Device address. + 0x0A4 + + + + OVERRIDEEN + Radio calibration override enable. + 0x0AC + + + NRF_1MBIT + Override default values for NRF_1Mbit mode. + 0 0 + + + Override + Override the default values for NRF_1Mbit mode. + 0 + + + NotOverride + Do not override the default values for NRF_1Mbit mode. + 1 + + + + + BLE_1MBIT + Override default values for BLE_1Mbit mode. + 3 3 + + + Override + Override the default values for BLE_1Mbit mode. + 0 + + + NotOverride + Do not override the default values for BLE_1Mbit mode. + 1 + + + + + + + + 5 + 0x04 + NRF_1MBIT[%s] + Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit mode. + 0x0B0 + + + 5 + 0x04 + BLE_1MBIT[%s] + Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit mode. + 0x0EC + + + + + + + UICR + 522 + User Information Configuration. + UICR + 0x10001000 + 32 + read-write + 0xFFFFFFFF + + + 0 + 0x1000 + registers + + + + + CLENR0 + Length of code region 0. + 0x000 + + + + RBPCONF + Readback protection configuration. + 0x004 + + + PR0 + Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. + 0 7 + + + Disabled + Disabled. + 0xFF + + + Enabled + Enabled. + 0x00 + + + + + PALL + Readback protect all code in the device. + 8 15 + + + Disabled + Disabled. + 0xFF + + + Enabled + Enabled. + 0x00 + + + + + + + + XTALFREQ + Reset value for CLOCK XTALFREQ register. + 0x008 + + + XTALFREQ + Reset value for CLOCK XTALFREQ register. + 0 7 + + + 16MHz + 16MHz Xtal is used. + 0xFF + + + 32MHz + 32MHz Xtal is used. + 0x00 + + + + + + + + FWID + Firmware ID. + 0x010 + read-only + + + FWID + Identification number for the firmware loaded into the chip. + 0 15 + + + + + + BOOTLOADERADDR + Bootloader start address. + 0x014 + + + + 15 + 0x04 + NRFFW[%s] + Reserved for Nordic firmware design. + 0x014 + BOOTLOADERADDR + + + 12 + 0x04 + NRFHW[%s] + Reserved for Nordic hardware design. + 0x050 + + + 32 + 0x04 + CUSTOMER[%s] + Reserved for customer. + 0x080 + + + + + + + GPIO + 522 + General purpose input and output. + 0x50000000 + GPIO + 32 + read-write + + + 0 + 0x1000 + registers + + + + + OUT + Write GPIO port. + 0x504 + + + PIN0 + Pin 0. + 0 0 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN1 + Pin 1. + 1 1 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN2 + Pin 2. + 2 2 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN3 + Pin 3. + 3 3 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN4 + Pin 4. + 4 4 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN5 + Pin 5. + 5 5 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN6 + Pin 6. + 6 6 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN7 + Pin 7. + 7 7 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN8 + Pin 8. + 8 8 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN9 + Pin 9. + 9 9 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN10 + Pin 10. + 10 10 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN11 + Pin 11. + 11 11 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN12 + Pin 12. + 12 12 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN13 + Pin 13. + 13 13 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN14 + Pin 14. + 14 14 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN15 + Pin 15. + 15 15 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN16 + Pin 16. + 16 16 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN17 + Pin 17. + 17 17 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN18 + Pin 18. + 18 18 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN19 + Pin 19. + 19 19 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN20 + Pin 20. + 20 20 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN21 + Pin 21. + 21 21 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN22 + Pin 22. + 22 22 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN23 + Pin 23. + 23 23 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN24 + Pin 24. + 24 24 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN25 + Pin 25. + 25 25 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN26 + Pin 26. + 26 26 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN27 + Pin 27. + 27 27 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN28 + Pin 28. + 28 28 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN29 + Pin 29. + 29 29 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN30 + Pin 30. + 30 30 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + PIN31 + Pin 31. + 31 31 + + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + + + + OUTSET + Set individual bits in GPIO port. + 0x508 + + + PIN0 + Pin 0. + 0 0 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN1 + Pin 1. + 1 1 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN2 + Pin 2. + 2 2 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN3 + Pin 3. + 3 3 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN4 + Pin 4. + 4 4 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN5 + Pin 5. + 5 5 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN6 + Pin 6. + 6 6 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN7 + Pin 7. + 7 7 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN8 + Pin 8. + 8 8 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN9 + Pin 9. + 9 9 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN10 + Pin 10. + 10 10 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN11 + Pin 11. + 11 11 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN12 + Pin 12. + 12 12 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN13 + Pin 13. + 13 13 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN14 + Pin 14. + 14 14 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN15 + Pin 15. + 15 15 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN16 + Pin 16. + 16 16 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN17 + Pin 17. + 17 17 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN18 + Pin 18. + 18 18 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN19 + Pin 19. + 19 19 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN20 + Pin 20. + 20 20 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN21 + Pin 21. + 21 21 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN22 + Pin 22. + 22 22 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN23 + Pin 23. + 23 23 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN24 + Pin 24. + 24 24 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN25 + Pin 25. + 25 25 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN26 + Pin 26. + 26 26 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN27 + Pin 27. + 27 27 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN28 + Pin 28. + 28 28 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN29 + Pin 29. + 29 29 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN30 + Pin 30. + 30 30 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + PIN31 + Pin 31. + 31 31 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Set + Set pin driver high. + 1 + + + + + + + OUTCLR + Clear individual bits in GPIO port. + 0x50C + + + PIN0 + Pin 0. + 0 0 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN1 + Pin 1. + 1 1 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN2 + Pin 2. + 2 2 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN3 + Pin 3. + 3 3 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN4 + Pin 4. + 4 4 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN5 + Pin 5. + 5 5 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN6 + Pin 6. + 6 6 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN7 + Pin 7. + 7 7 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN8 + Pin 8. + 8 8 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN9 + Pin 9. + 9 9 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN10 + Pin 10. + 10 10 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN11 + Pin 11. + 11 11 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN12 + Pin 12. + 12 12 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN13 + Pin 13. + 13 13 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN14 + Pin 14. + 14 14 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN15 + Pin 15. + 15 15 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN16 + Pin 16. + 16 16 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN17 + Pin 17. + 17 17 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN18 + Pin 18. + 18 18 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN19 + Pin 19. + 19 19 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN20 + Pin 20. + 20 20 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN21 + Pin 21. + 21 21 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN22 + Pin 22. + 22 22 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN23 + Pin 23. + 23 23 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN24 + Pin 24. + 24 24 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN25 + Pin 25. + 25 25 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN26 + Pin 26. + 26 26 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN27 + Pin 27. + 27 27 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN28 + Pin 28. + 28 28 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN29 + Pin 29. + 29 29 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN30 + Pin 30. + 30 30 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + PIN31 + Pin 31. + 31 31 + + read + + Low + Pin driver is low. + 0 + + + High + Pin driver is high. + 1 + + + + write + + Clear + Set pin driver low. + 1 + + + + + + + + IN + Read GPIO port. + 0x510 + read-only + + + PIN0 + Pin 0. + 0 0 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN1 + Pin 1. + 1 1 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN2 + Pin 2. + 2 2 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN3 + Pin 3. + 3 3 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN4 + Pin 4. + 4 4 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN5 + Pin 5. + 5 5 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN6 + Pin 6. + 6 6 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN7 + Pin 7. + 7 7 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN8 + Pin 8. + 8 8 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN9 + Pin 9. + 9 9 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN10 + Pin 10. + 10 10 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN11 + Pin 11. + 11 11 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN12 + Pin 12. + 12 12 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN13 + Pin 13. + 13 13 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN14 + Pin 14. + 14 14 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN15 + Pin 15. + 15 15 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN16 + Pin 16. + 16 16 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN17 + Pin 17. + 17 17 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN18 + Pin 18. + 18 18 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN19 + Pin 19. + 19 19 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN20 + Pin 20. + 20 20 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN21 + Pin 21. + 21 21 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN22 + Pin 22. + 22 22 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN23 + Pin 23. + 23 23 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN24 + Pin 24. + 24 24 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN25 + Pin 25. + 25 25 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN26 + Pin 26. + 26 26 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN27 + Pin 27. + 27 27 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN28 + Pin 28. + 28 28 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN29 + Pin 29. + 29 29 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN30 + Pin 30. + 30 30 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + PIN31 + Pin 31. + 31 31 + + + Low + Pin input is low. + 0 + + + High + Pin input is high. + 1 + + + + + + + + DIR + Direction of GPIO pins. + 0x514 + + + PIN0 + Pin 0. + 0 0 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN1 + Pin 1. + 1 1 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN2 + Pin 2. + 2 2 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN3 + Pin 3. + 3 3 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN4 + Pin 4. + 4 4 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN5 + Pin 5. + 5 5 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN6 + Pin 6. + 6 6 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN7 + Pin 7. + 7 7 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN8 + Pin 8. + 8 8 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN9 + Pin 9. + 9 9 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN10 + Pin 10. + 10 10 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN11 + Pin 11. + 11 11 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN12 + Pin 12. + 12 12 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN13 + Pin 13. + 13 13 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN14 + Pin 14. + 14 14 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN15 + Pin 15. + 15 15 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN16 + Pin 16. + 16 16 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN17 + Pin 17. + 17 17 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN18 + Pin 18. + 18 18 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN19 + Pin 19. + 19 19 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN20 + Pin 20. + 20 20 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN21 + Pin 21. + 21 21 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN22 + Pin 22. + 22 22 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN23 + Pin 23. + 23 23 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN24 + Pin 24. + 24 24 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN25 + Pin 25. + 25 25 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN26 + Pin 26. + 26 26 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN27 + Pin 27. + 27 27 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN28 + Pin 28. + 28 28 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN29 + Pin 29. + 29 29 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN30 + Pin 30. + 30 30 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + PIN31 + Pin 31. + 31 31 + + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + + + + DIRSET + DIR set register. + 0x518 + + + PIN0 + Set as output pin 0. + 0 0 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN1 + Set as output pin 1. + 1 1 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN2 + Set as output pin 2. + 2 2 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN3 + Set as output pin 3. + 3 3 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN4 + Set as output pin 4. + 4 4 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN5 + Set as output pin 5. + 5 5 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN6 + Set as output pin 6. + 6 6 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN7 + Set as output pin 7. + 7 7 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN8 + Set as output pin 8. + 8 8 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN9 + Set as output pin 9. + 9 9 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN10 + Set as output pin 10. + 10 10 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN11 + Set as output pin 11. + 11 11 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN12 + Set as output pin 12. + 12 12 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN13 + Set as output pin 13. + 13 13 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN14 + Set as output pin 14. + 14 14 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN15 + Set as output pin 15. + 15 15 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN16 + Set as output pin 16. + 16 16 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN17 + Set as output pin 17. + 17 17 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN18 + Set as output pin 18. + 18 18 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN19 + Set as output pin 19. + 19 19 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN20 + Set as output pin 20. + 20 20 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN21 + Set as output pin 21. + 21 21 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN22 + Set as output pin 22. + 22 22 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN23 + Set as output pin 23. + 23 23 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN24 + Set as output pin 24. + 24 24 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN25 + Set as output pin 25. + 25 25 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN26 + Set as output pin 26. + 26 26 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN27 + Set as output pin 27. + 27 27 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN28 + Set as output pin 28. + 28 28 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN29 + Set as output pin 29. + 29 29 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN30 + Set as output pin 30. + 30 30 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + PIN31 + Set as output pin 31. + 31 31 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Set + Set pin as output. + 1 + + + + + + + DIRCLR + DIR clear register. + 0x51C + + + PIN0 + Set as input pin 0. + 0 0 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN1 + Set as input pin 1. + 1 1 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN2 + Set as input pin 2. + 2 2 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN3 + Set as input pin 3. + 3 3 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN4 + Set as input pin 4. + 4 4 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN5 + Set as input pin 5. + 5 5 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN6 + Set as input pin 6. + 6 6 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN7 + Set as input pin 7. + 7 7 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN8 + Set as input pin 8. + 8 8 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN9 + Set as input pin 9. + 9 9 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN10 + Set as input pin 10. + 10 10 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN11 + Set as input pin 11. + 11 11 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN12 + Set as input pin 12. + 12 12 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN13 + Set as input pin 13. + 13 13 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN14 + Set as input pin 14. + 14 14 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN15 + Set as input pin 15. + 15 15 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN16 + Set as input pin 16. + 16 16 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN17 + Set as input pin 17. + 17 17 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN18 + Set as input pin 18. + 18 18 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN19 + Set as input pin 19. + 19 19 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN20 + Set as input pin 20. + 20 20 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN21 + Set as input pin 21. + 21 21 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN22 + Set as input pin 22. + 22 22 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN23 + Set as input pin 23. + 23 23 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN24 + Set as input pin 24. + 24 24 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN25 + Set as input pin 25. + 25 25 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN26 + Set as input pin 26. + 26 26 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN27 + Set as input pin 27. + 27 27 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN28 + Set as input pin 28. + 28 28 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN29 + Set as input pin 29. + 29 29 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN30 + Set as input pin 30. + 30 30 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + PIN31 + Set as input pin 31. + 31 31 + + read + + Input + Pin set as input. + 0 + + + Output + Pin set as output. + 1 + + + + write + + Clear + Set pin as input. + 1 + + + + + + + + + 32 + 0x04 + PIN_CNF[%s] + Configuration of GPIO pins. + 0x700 + 0x00000002 + + + DIR + Pin direction. + 0 0 + + + Input + Configure pin as an input pin. + 0 + + + Output + Configure pin as an output pin. + 1 + + + + + INPUT + Connect or disconnect input path. + 1 1 + + + Connect + Connect input pin. + 0 + + + Disconnect + Disconnect input pin. + 1 + + + + + PULL + Pull-up or -down configuration. + 2 3 + + + Disabled + No pull. + 0x00 + + + Pulldown + Pulldown on pin. + 0x01 + + + Pullup + Pullup on pin. + 0x03 + + + + + DRIVE + Drive configuration. + 8 10 + + + S0S1 + Standard '0', Standard '1'. + 0x00 + + + H0S1 + High '0', Standard '1'. + 0x01 + + + S0H1 + Standard '0', High '1'. + 0x02 + + + H0H1 + High '0', High '1'. + 0x03 + + + D0S1 + Disconnected '0', Standard '1'. + 0x04 + + + D0H1 + Disconnected '0', High '1'. + 0x05 + + + S0D1 + Standard '0', Disconnected '1'. + 0x06 + + + H0D1 + High '0', Disconnected '1'. + 0x07 + + + + + SENSE + Pin sensing mechanism. + 16 17 + + + Disabled + Disabled. + 0x00 + + + High + Wakeup on high level. + 0x02 + + + Low + Wakeup on low level. + 0x03 + + + + + + + + + + diff --git a/openocd.cfg b/openocd.cfg new file mode 100644 index 0000000..91ea439 --- /dev/null +++ b/openocd.cfg @@ -0,0 +1,2 @@ +source [find interface/cmsis-dap.cfg] +source [find target/nrf51.cfg] diff --git a/openocd.gdb b/openocd.gdb new file mode 100644 index 0000000..7795319 --- /dev/null +++ b/openocd.gdb @@ -0,0 +1,40 @@ +target extended-remote :3333 + +# print demangled symbols +set print asm-demangle on + +# set backtrace limit to not have infinite backtrace loops +set backtrace limit 32 + +# detect unhandled exceptions, hard faults and panics +break DefaultHandler +break HardFault +break rust_begin_unwind +# # run the next few lines so the panic message is printed immediately +# # the number needs to be adjusted for your panic handler +# commands $bpnum +# next 4 +# end + +# *try* to stop at the user entry point (it might be gone due to inlining) +break main + +monitor arm semihosting enable + +# # send captured ITM to the file itm.fifo +# # (the microcontroller SWO pin must be connected to the programmer SWO pin) +# # 8000000 must match the core clock frequency +# monitor tpiu config internal itm.txt uart off 8000000 + +# # OR: make the microcontroller SWO pin output compatible with UART (8N1) +# # 8000000 must match the core clock frequency +# # 2000000 is the frequency of the SWO pin +# monitor tpiu config external uart off 8000000 2000000 + +# # enable ITM port 0 +# monitor itm port 0 on + +load + +# start the process but immediately halt the processor +stepi diff --git a/rust-toolchain.toml b/rust-toolchain.toml new file mode 100644 index 0000000..c8455e2 --- /dev/null +++ b/rust-toolchain.toml @@ -0,0 +1,3 @@ +[toolchain] +channel = "1.82.0" +components = ["rustfmt", "llvm-tools-preview"] diff --git a/src/bit_string/mod.rs b/src/bit_string/mod.rs new file mode 100644 index 0000000..9f494cf --- /dev/null +++ b/src/bit_string/mod.rs @@ -0,0 +1,7 @@ +mod thumbv6m; + +pub trait Sender { + fn send(&self, value: u32); +} + +pub use thumbv6m::Msb2LsbSender; diff --git a/src/bit_string/thumbv6m.rs b/src/bit_string/thumbv6m.rs new file mode 100644 index 0000000..83e24bf --- /dev/null +++ b/src/bit_string/thumbv6m.rs @@ -0,0 +1,161 @@ +use super::Sender; +use core::arch::asm; + +pub struct Msb2LsbSender< + const BITS: u32, + const SHIFT: u32, + const PIN_MASK: u32, + const PIN_LEVEL_A_ADDRESS: u32, + const PIN_LEVEL_B_ADDRESS: u32, + const T0A: u32, + const T0B: u32, + const T1A: u32, + const T1B: u32, +> {} + +impl< + const BITS: u32, + const SHIFT: u32, + const PIN_MASK: u32, + const PIN_LEVEL_A_ADDRESS: u32, + const PIN_LEVEL_B_ADDRESS: u32, + const T0A: u32, + const T0B: u32, + const T1A: u32, + const T1B: u32, + > + Msb2LsbSender< + BITS, + SHIFT, + PIN_MASK, + PIN_LEVEL_A_ADDRESS, + PIN_LEVEL_B_ADDRESS, + T0A, + T0B, + T1A, + T1B, + > +{ + pub fn new() -> Self { + Msb2LsbSender {} + } +} + +impl< + const BITS: u32, + const SHIFT: u32, + const PIN_MASK: u32, + const PIN_LEVEL_A_ADDRESS: u32, + const PIN_LEVEL_B_ADDRESS: u32, + const T0A: u32, + const T0B: u32, + const T1A: u32, + const T1B: u32, + > Sender + for Msb2LsbSender< + BITS, + SHIFT, + PIN_MASK, + PIN_LEVEL_A_ADDRESS, + PIN_LEVEL_B_ADDRESS, + T0A, + T0B, + T1A, + T1B, + > +{ + // To send + // Send a string of bit, stored in an u32. first shift by SHIFT to place the first bit in the MSB + // position, then transmit BITS bits, from the most to the least significant one. + // PIN_MASK is the mask to use to write in PIN_START_ADDRESS, and PIN_STOP_ADDRESS to toggle the pin. + // T0A, T0B, T1A, T1B are the number of cycles to wait after writing to A START, and B STOP address. + // At a minimum there is always a 3cycle-delay, and due to rounding there might be a +/- 1 cycle + // difference for non-multiple of 3. + fn send(&self, value: u32) { + unsafe { + let mut primask: u32; + asm!( + // Save interrupt mask and disable interrupts for each bit + // We do this outside of the bit sending loop as it allows callers of the function to tune + // how long the interrupts are disabled by setting the BITS type constant. + " mrs {primask}, PRIMASK", + " movs {tmp}, #1", + " orrs {tmp}, {primask}", + " msr PRIMASK, {tmp}", + primask = out(reg) primask, + tmp = out(reg) _, + ); + + asm!( + "3:", + // reload pin mask + " movs {tmp}, #{pin_mask}", + // shift left and update carry flag + " lsls {value}, {value}, #1", + // send a 0 or a 1 based on the carry flag value + " bcs 1f", + " nop", + " movs {delay1}, #{t0a}", + " movs {delay2}, #{t0b}", + " b 2f", + "1: ", + " movs {delay1}, #{t1a}", + " movs {delay2}, #{t1b}", + " b 2f", + "2: ", + + // set or clear pin + " str {tmp}, [{pin_start_address}]", + // wait first delay + "1:", + " subs {delay1}, #1", + " bgt 1b", + // toggle pin + " str {tmp}, [{pin_stop_address}]", + // wait second delay + "1:", + " subs {delay2}, #1", + " bgt 1b", + + // loop back to send next bit + " subs {bit}, #1", + " bgt 3b", + + // A loop is 3 cycles, and the index is predecremented, so make sure it is at least 1. + // We also add 1 so that the integer division is at most off by one. + t0a = const match T0A { + 0..3 => 1, + _ => (T0A + 1) / 3, + }, + t0b = const match T0B { + 0..3 => 1, + _ => (T0A + 1) / 3, + }, + t1a = const match T1A { + 0..3 => 1, + _ => (T1A + 1) / 3, + }, + t1b = const match T1B { + 0..3 => 1, + _ => (T1B + 1) / 3, + }, + pin_mask = const PIN_MASK, + pin_start_address = in(reg) PIN_LEVEL_A_ADDRESS, + pin_stop_address = in(reg) PIN_LEVEL_B_ADDRESS, + // Number of bits to transmit + bit = inout(reg) BITS => _, + // Place the value in the most significant bits of the register + value = inout(reg) value << SHIFT => _, + delay1 = out(reg) _, + delay2 = out(reg) _, + tmp = out(reg) _, + ); + + asm!( + // Restore primask to previous state. + " msr PRIMASK, {primask}", + primask = in(reg) primask, + ); + } + } +} diff --git a/src/led_display/mod.rs b/src/led_display/mod.rs new file mode 100644 index 0000000..098caeb --- /dev/null +++ b/src/led_display/mod.rs @@ -0,0 +1,22 @@ +pub trait PixelDisplay { + fn show(&self); + + fn clear(&mut self); + + fn fill(&mut self, value: u32); + + fn point(&mut self, position: Position, value: u32); + + fn fill_rectangle(&mut self, a: Position, b: Position, value: u32); + + fn fill_circle(&mut self, origin: Position, radius: usize, value: u32); + + fn rectangle(&mut self, bottom_left: Position, upper_right: Position, value: u32); + + fn circle(&mut self, origin: Position, radius: usize, value: u32); + + // fn segment(&mut self, origin: Position, end: Position, value: u32); + // + // fn copy(&mut self, origin: Position, data: &[[u32]]); + +} diff --git a/src/lib.rs b/src/lib.rs new file mode 100644 index 0000000..b1f1eab --- /dev/null +++ b/src/lib.rs @@ -0,0 +1,52 @@ +// #![no_main] +#![no_std] +// +// use cortex_m_semihosting::debug; +// +// use defmt_rtt as _; // global logger +// +// // use some_hal as _; // memory layout +// use microbit as _; +// +// use panic_probe as _; +// +// // same panicking *behavior* as `panic-probe` but doesn't print a panic message +// // this prevents the panic message being printed *twice* when `defmt::panic` is invoked +// #[defmt::panic_handler] +// fn panic() -> ! { +// cortex_m::asm::udf() +// } +// +// /// Terminates the application and makes a semihosting-capable debug tool exit +// /// with status code 0. +// pub fn exit() -> ! { +// loop { +// debug::exit(debug::EXIT_SUCCESS); +// } +// } +// +// /// Hardfault handler. +// /// +// /// Terminates the application and makes a semihosting-capable debug tool exit +// /// with an error. This seems better than the default, which is to spin in a +// /// loop. +// #[cortex_m_rt::exception] +// unsafe fn HardFault(_frame: &cortex_m_rt::ExceptionFrame) -> ! { +// loop { +// debug::exit(debug::EXIT_FAILURE); +// } +// } +// +// // defmt-test 0.3.0 has the limitation that this `#[tests]` attribute can only be used +// // once within a crate. the module can be in any file but there can only be at most +// // one `#[tests]` module in this library crate +// #[cfg(test)] +// #[defmt_test::tests] +// mod unit_tests { +// use defmt::assert; +// +// #[test] +// fn it_works() { +// assert!(true) +// } +// } diff --git a/src/main.rs b/src/main.rs new file mode 100644 index 0000000..cf5ea63 --- /dev/null +++ b/src/main.rs @@ -0,0 +1,93 @@ +#![no_main] +#![no_std] + +use crate::neo_pixel::CompositeNeoPixelDisplay; +use cortex_m::asm; +use cortex_m::asm::delay; +use defmt_rtt as _; +use led_display::PixelDisplay; +use microbit::hal::gpio::Level::Low; +use microbit::Board; +use panic_probe as _; + +mod bit_string; +mod led_display; +mod neo_pixel; + +// Bit delay, starting always from set HIGH, wait, go to LOW, wait, repeat +const T0H_NS: u32 = 250; // 350+/-150 [ns] +const T1H_NS: u32 = 900; // 700+/-150 [ns] + +// Latch reset delay +const TLL_NS: u32 = 250_000; // 6_000 [ns] min, newer pixels require ~250_000 [ns] + +const T0L_NS: u32 = 900; // 800+/-150 [ns] +const T1L_NS: u32 = 600; // 600+/-150 [ns] + +// Rounded down, from 20.8333 +const NS_PER_CYCLE: u32 = 114; // empirically measured to be about 114ns + +const T0H: u32 = T0H_NS / NS_PER_CYCLE; +const T0L: u32 = T0L_NS / NS_PER_CYCLE; +const T1H: u32 = T1H_NS / NS_PER_CYCLE; +const T1L: u32 = T1L_NS / NS_PER_CYCLE; +const TLL: u32 = TLL_NS / NS_PER_CYCLE; + +// TODO RETRIEVE THIS FROM PAC +const EDGE_PAD0_MASK: u32 = 1 << 3; +const EDGE_PAD0_SET_ADDRESS: u32 = 0x5000_0508; // Address of the SET register +const EDGE_PAD0_CLEAR_ADDRESS: u32 = 0x5000_050c; // Address of the toggle register + +fn setup() -> CompositeNeoPixelDisplay<8, 8, 4, 1, 2192, 8, 1342178568, 1342178572, 2, 7, 7, 5> { + let board = Board::take().unwrap(); + let _pin = board.edge.e00.into_push_pull_output(Low); + delay(TLL * 2); + + CompositeNeoPixelDisplay::< + 8, + 8, + 4, /*NX*/ + 1, /*NY*/ + TLL, + EDGE_PAD0_MASK, + EDGE_PAD0_SET_ADDRESS, + EDGE_PAD0_CLEAR_ADDRESS, + T0H, + T0L, + T1H, + T1L, + >::new() +} + +#[cortex_m_rt::entry] +fn main() -> ! { + const SPACING: usize = 32; + let mut display = setup(); + let mut frame = 0; + + loop { + display.clear(); + + display.vbar_shift_left(0x020000, frame, SPACING); + display.vbar_shift_left(0x020000, frame + 1, SPACING); + display.vbar_shift_left(0x020000, frame + 2, SPACING); + display.vbar_shift_left(0x000200, frame + 3, SPACING); + display.vbar_shift_left(0x000200, frame + 4, SPACING); + display.vbar_shift_left(0x000002, frame + 5, SPACING); + display.fill_circle( + display.position((frame + 32 - 4) % { 4 * 8 }, 3), + 2, + 0x020000, + ); + display.circle( + display.position((frame + 32 - 4) % { 4 * 8 }, 3), + 3, + 0x040000, + ); + + display.show(); + frame += 1; + + asm::delay(200_000); // TODO: REPLACE WITH TIMER DELAY + } +} diff --git a/src/neo_pixel/mod.rs b/src/neo_pixel/mod.rs new file mode 100644 index 0000000..7d929c8 --- /dev/null +++ b/src/neo_pixel/mod.rs @@ -0,0 +1,358 @@ +use crate::bit_string; +use crate::bit_string::Sender; +use crate::led_display::PixelDisplay; +use cortex_m::asm; +use defmt::{warn, Format}; + +#[derive(Eq, Format, Ord, PartialEq, PartialOrd)] +pub struct Position { + x: usize, + y: usize, +} + +impl Position { + fn new(x: usize, y: usize) -> Self { + Self { x, y } + } +} + +pub type NeoPixelSender< + const PIN_MASK: u32, + const PIN_LEVEL_HIGH_ADDRESS: u32, + const PIN_LEVEL_LOW_ADDRESS: u32, + const DELAY_ZERO_HIGH: u32, + const DELAY_ZERO_LOW: u32, + const DELAY_ONE_HIGH: u32, + const DELAY_ONE_LOW: u32, +> = bit_string::Msb2LsbSender< + 24, + 8, + PIN_MASK, + PIN_LEVEL_HIGH_ADDRESS, + PIN_LEVEL_LOW_ADDRESS, + DELAY_ZERO_HIGH, + DELAY_ZERO_LOW, + DELAY_ONE_HIGH, + DELAY_ONE_LOW, +>; + +struct BufferPosition { + row: usize, + col: usize, + y: usize, + x: usize, +} + +impl TryFrom> + for BufferPosition +{ + type Error = (); + + fn try_from(position: Option) -> Result { + if let Some(position) = position { + position.try_into() + } else { + Err(()) + } + } +} + +impl TryFrom + for BufferPosition +{ + type Error = (); + + fn try_from(position: Position) -> Result { + let col = position.x / X; + let row = position.y / Y; + + if col > NX && row > NY { + return Err(()); + } + if col > NX { + return Err(()); + } + if row > NY { + return Err(()); + } + + let x = position.x % X; + let y = position.y % Y; + Ok(BufferPosition { row, col, y, x }) + } +} + +pub struct CompositeNeoPixelDisplay< + const X: usize, + const Y: usize, + const NX: usize, + const NY: usize, + const DELAY_RESET: u32, + const PIN_MASK: u32, + const PIN_LEVEL_HIGH_ADDRESS: u32, + const PIN_LEVEL_LOW_ADDRESS: u32, + const DELAY_ZERO_HIGH: u32, + const DELAY_ZERO_LOW: u32, + const DELAY_ONE_HIGH: u32, + const DELAY_ONE_LOW: u32, +> { + buffer: [[[[u32; X]; Y]; NX]; NY], + sender: NeoPixelSender< + PIN_MASK, + PIN_LEVEL_HIGH_ADDRESS, + PIN_LEVEL_LOW_ADDRESS, + DELAY_ZERO_HIGH, + DELAY_ZERO_LOW, + DELAY_ONE_HIGH, + DELAY_ONE_LOW, + >, +} + +impl< + const X: usize, + const Y: usize, + const NX: usize, + const NY: usize, + const DELAY_RESET: u32, + const PIN_MASK: u32, + const PIN_LEVEL_HIGH_ADDRESS: u32, + const PIN_LEVEL_LOW_ADDRESS: u32, + const DELAY_ZERO_HIGH: u32, + const DELAY_ZERO_LOW: u32, + const DELAY_ONE_HIGH: u32, + const DELAY_ONE_LOW: u32, + > + CompositeNeoPixelDisplay< + X, + Y, + NX, + NY, + DELAY_RESET, + PIN_MASK, + PIN_LEVEL_HIGH_ADDRESS, + PIN_LEVEL_LOW_ADDRESS, + DELAY_ZERO_HIGH, + DELAY_ZERO_LOW, + DELAY_ONE_HIGH, + DELAY_ONE_LOW, + > +{ + pub fn new() -> Self { + let display = Self { + buffer: [[[[0x0; X]; Y]; NX]; NY], + sender: NeoPixelSender::new(), + }; + + display.show(); + display + } + + pub fn position(&self, x: usize, y: usize) -> Option { + if (x < { X * NX }) && (y < { Y * NY }) { + Some(Position::new(x, y)) + } else { + warn!( + "Position({},{}) is outside the display range [(0,0);({},{})[.", + x, + y, + { X * NX }, + { Y * NY }, + ); + None + } + } + + // funzies + pub fn vbar_shift_left(&mut self, color: u32, offset: usize, spacing: usize) { + for i in 0..(X * Y * NX * NY) { + if (i % spacing) == 0 { + self.point(self.position((i + offset) % (X * NX), i / (X * NX)), color); + } + } + } +} + +impl< + const X: usize, + const Y: usize, + const NX: usize, + const NY: usize, + const DELAY_RESET: u32, + const PIN_MASK: u32, + const PIN_LEVEL_HIGH_ADDRESS: u32, + const PIN_LEVEL_LOW_ADDRESS: u32, + const DELAY_ZERO_HIGH: u32, + const DELAY_ZERO_LOW: u32, + const DELAY_ONE_HIGH: u32, + const DELAY_ONE_LOW: u32, + > PixelDisplay> + for CompositeNeoPixelDisplay< + X, + Y, + NX, + NY, + DELAY_RESET, + PIN_MASK, + PIN_LEVEL_HIGH_ADDRESS, + PIN_LEVEL_LOW_ADDRESS, + DELAY_ZERO_HIGH, + DELAY_ZERO_LOW, + DELAY_ONE_HIGH, + DELAY_ONE_LOW, + > +{ + fn show(&self) { + for r in 0..NY { + for c in 0..NX { + for y in 0..Y { + for x in 0..X { + self.sender.send(self.buffer[r][c][y][x]); + } + } + } + } + asm::delay(DELAY_RESET); + } + + fn clear(&mut self) { + self.fill(0x0); + } + + fn fill(&mut self, value: u32) { + self.fill_rectangle( + self.position(0, 0), + self.position(X * NX - 1, Y * NY - 1), + value, + ); + } + + fn point(&mut self, position: Option, value: u32) { + if let Ok(BufferPosition:: { row, col, y, x }) = position.try_into() { + self.buffer[row][col][y][x] = value; + } + } + + fn fill_rectangle(&mut self, a: Option, b: Option, value: u32) { + if let Some(a) = a { + if let Some(b) = b { + let bottom_left; + let upper_right; + if a < b { + bottom_left = a; + upper_right = b; + } else { + bottom_left = b; + upper_right = a; + } + let Position { x: x0, y: y0 } = bottom_left; + let Position { x: x1, y: y1 } = upper_right; + + for y in y0..=y1 { + for x in x0..=x1 { + self.point(self.position(x, y), value) + } + } + } + } + } + + fn fill_circle(&mut self, origin: Option, radius: usize, value: u32) { + if let Some(origin) = origin { + let Position { x: cx, y: cy } = origin; + let y0 = if cy < radius { 0 } else { cy - radius }; + let x0 = if cx < radius { 0 } else { cx - radius }; + + for y in y0..=(cy + radius) { + for x in x0..=(cx + radius) { + let dx = if x < cx { cx - x } else { x - cx }; + let dy = if y < cy { cy - y } else { y - cy }; + let h = dx * dx + dy * dy; + let epsilon = (radius * 2) + 1 / radius + 1; // todo simplify or tune some more + if h <= radius + epsilon { + self.point(self.position(x, y), value); + } + } + } + } + } + // fn segment(&mut self, a: Option, b: Option, value: u32) { + // if let Some(a) = &a { + // if let Some(b) = &b { + // let start = if a < b { a } else { b }; + // let end = if a < b { b } else { a }; + // let dx = end.x - start.x; + // let dy = end.y - start.y; + // for x in start.x..=end.x {} + // } + // } + // } + // + // fn copy(&mut self, origin: Option, data: &[[u32]]) { + // if let Some(origin) = origin { + // let Position { x: x0, y: y0 } = origin; + // let mut iy = 0; + // let mut ix = 0; + // for y in data.iter() { + // ix = 0; + // for x in y.iter() { + // self.point(self.position(ix, iy), *x); + // ix += 1; + // } + // iy += 1; + // } + // } + // } + + fn rectangle(&mut self, a: Option, b: Option, value: u32) { + if let Some(a) = a { + if let Some(b) = b { + let bottom_left; + let upper_right; + if a < b { + bottom_left = a; + upper_right = b; + } else { + bottom_left = b; + upper_right = a; + } + let Position { x: x0, y: y0 } = bottom_left; + let Position { x: x1, y: y1 } = upper_right; + + for y in y0..=y1 { + if (y != y0) && (y != y1) { + continue; + } + for x in x0..=x1 { + if (x != x0) && (x != x1) { + continue; + } + self.point(self.position(x, y), value); + } + } + } + } + } + + fn circle(&mut self, origin: Option, radius: usize, value: u32) { + if let Some(origin) = origin { + let Position { x: cx, y: cy } = origin; + let y0 = if cy < radius { 0 } else { cy - radius }; + let x0 = if cx < radius { 0 } else { cx - radius }; + + for y in y0..=(cy + radius) { + for x in x0..=(cx + radius) { + let dx = if x < cx { cx - x } else { x - cx }; + let dy = if y < cy { cy - y } else { y - cy }; + let r2 = radius * radius; + let h = dx * dx + dy * dy; + let d = if r2 < h { h - r2 } else { r2 - h }; + let epsilon = (radius * 2 + 1) / radius + 1; + if d < epsilon { + // we use a larger epsilon to have a full line + self.point(self.position(x, y), value); + } + } + } + } + } +} diff --git a/tests/integration.rs b/tests/integration.rs new file mode 100644 index 0000000..1816b06 --- /dev/null +++ b/tests/integration.rs @@ -0,0 +1,16 @@ +#![no_std] +#![no_main] + +use template_microbit as _; // memory layout + panic handler + +// See https://crates.io/crates/defmt-test/0.3.0 for more documentation (e.g. about the 'state' +// feature) +#[defmt_test::tests] +mod tests { + use defmt::assert; + + #[test] + fn it_works() { + assert!(true) + } +}