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Replace u32_t by uint32_t

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This commit is contained in:
Lionel Sambuc
2018-01-02 18:57:25 +01:00
parent 662d40e304
commit 7b6f6eb8b6
297 changed files with 2110 additions and 2110 deletions
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4
minix/commands/autopart/autopart.c
View File

@@ -1523,7 +1523,7 @@ void m_read(int ev, int *biosdrive)
{
int i, n, v;
struct part_entry *pe;
u32_t system_hz;
uint32_t system_hz;
if (ev != 'r' || device >= 0) return;
@@ -1536,7 +1536,7 @@ void m_read(int ev, int *biosdrive)
return;
}
system_hz = (u32_t) sysconf(_SC_CLK_TCK);
system_hz = (uint32_t) sysconf(_SC_CLK_TCK);
v = 2*system_hz;
ioctl(device, DIOCTIMEOUT, &v);

8
minix/commands/minix-service/minix-service.c
View File

@@ -289,7 +289,7 @@ static int parse_ipc_filter(char* str, int type_flag)
/* Parse and verify correctness of arguments. Report problem and exit if an
* error is found. Store needed parameters in global variables.
*/
static int parse_arguments(int argc, char **argv, u32_t *rss_flags)
static int parse_arguments(int argc, char **argv, uint32_t *rss_flags)
{
struct stat stat_buf;
char *hz, *buff;
@@ -415,7 +415,7 @@ static int parse_arguments(int argc, char **argv, u32_t *rss_flags)
*rss_flags = 0;
if (req_nr == RS_UP || req_nr == RS_UPDATE || req_nr == RS_EDIT) {
u32_t system_hz;
uint32_t system_hz;
if (c_flag)
*rss_flags |= RSS_COPY;
@@ -511,7 +511,7 @@ static int parse_arguments(int argc, char **argv, u32_t *rss_flags)
}
/* Get HZ. */
system_hz = (u32_t) sysconf(_SC_CLK_TCK);
system_hz = (uint32_t) sysconf(_SC_CLK_TCK);
/* Check optional arguments that come in pairs like "-args arglist". */
for (i=optind+MIN_ARG_COUNT+1; i<argc; i=i+2) {
@@ -717,7 +717,7 @@ int main(int argc, char **argv)
char *progname = NULL;
/* Arguments for RS to start a new service */
struct rs_config config;
u32_t rss_flags = 0;
uint32_t rss_flags = 0;
/* Verify and parse the command line arguments. All arguments are checked
* here. If an error occurs, the problem is reported and exit(2) is called.

2
minix/commands/minix-service/parse.c
View File

@@ -575,7 +575,7 @@ static void do_pci_device(config_t *cpe, struct rs_start *rs_start)
static void do_pci_class(config_t *cpe, struct rs_start *rs_start)
{
uint8_t baseclass, subclass, interface;
u32_t class_id, mask;
uint32_t class_id, mask;
char *check;
/* Process a list of PCI device class IDs */

156
minix/drivers/audio/als4000/als4000.c
View File

@@ -10,46 +10,46 @@ drv_t drv;
/* internal function */
static int dev_probe(void);
static int set_sample_rate(u32_t rate, int num);
static int set_stereo(u32_t stereo, int num);
static int set_bits(u32_t bits, int sub_dev);
static int set_frag_size(u32_t frag_size, int num);
static int set_sign(u32_t val, int num);
static int get_frag_size(u32_t *val, int *len, int num);
static int free_buf(u32_t *val, int *len, int num);
static int set_sample_rate(uint32_t rate, int num);
static int set_stereo(uint32_t stereo, int num);
static int set_bits(uint32_t bits, int sub_dev);
static int set_frag_size(uint32_t frag_size, int num);
static int set_sign(uint32_t val, int num);
static int get_frag_size(uint32_t *val, int *len, int num);
static int free_buf(uint32_t *val, int *len, int num);
/* developer interface */
static int dev_reset(u32_t *base);
static void dev_configure(u32_t *base);
static void dev_init_mixer(u32_t *base);
static void dev_set_sample_rate(u32_t *base, uint16_t sample_rate);
static void dev_set_format(u32_t *base, u32_t bits, u32_t sign,
u32_t stereo, u32_t sample_count);
static void dev_start_channel(u32_t *base, int sub_dev);
static void dev_stop_channel(u32_t *base, int sub_dev);
static void dev_set_dma(u32_t *base, u32_t dma, u32_t len, int sub_dev);
static u32_t dev_read_dma_current(u32_t *base, int sub_dev);
static void dev_pause_dma(u32_t *base, int sub_dev);
static void dev_resume_dma(u32_t *base, int sub_dev);
static void dev_intr_other(u32_t *base, u32_t status);
static u32_t dev_read_clear_intr_status(u32_t *base);
static void dev_intr_enable(u32_t *base, int flag);
static int dev_reset(uint32_t *base);
static void dev_configure(uint32_t *base);
static void dev_init_mixer(uint32_t *base);
static void dev_set_sample_rate(uint32_t *base, uint16_t sample_rate);
static void dev_set_format(uint32_t *base, uint32_t bits, uint32_t sign,
uint32_t stereo, uint32_t sample_count);
static void dev_start_channel(uint32_t *base, int sub_dev);
static void dev_stop_channel(uint32_t *base, int sub_dev);
static void dev_set_dma(uint32_t *base, uint32_t dma, uint32_t len, int sub_dev);
static uint32_t dev_read_dma_current(uint32_t *base, int sub_dev);
static void dev_pause_dma(uint32_t *base, int sub_dev);
static void dev_resume_dma(uint32_t *base, int sub_dev);
static void dev_intr_other(uint32_t *base, uint32_t status);
static uint32_t dev_read_clear_intr_status(uint32_t *base);
static void dev_intr_enable(uint32_t *base, int flag);
/* ======= Developer implemented function ======= */
/* ====== Self-defined function ====== */
static u32_t dev_gcr_read(u32_t base, u32_t reg) {
u32_t res;
static uint32_t dev_gcr_read(uint32_t base, uint32_t reg) {
uint32_t res;
sdr_out8(base, REG_GCR_INDEX, reg);
res = sdr_in32(base, REG_GCR_DATA);
return res;
}
static void dev_gcr_write(u32_t base, u32_t reg, u32_t val) {
static void dev_gcr_write(uint32_t base, uint32_t reg, uint32_t val) {
sdr_out8(base, REG_GCR_INDEX, reg);
sdr_out32(base, REG_GCR_DATA, val);
}
static void dev_command(u32_t base, u32_t cmd) {
static void dev_command(uint32_t base, uint32_t cmd) {
int i;
for (i = 0; i < 1000; i++) {
if ((sdr_in8(base + REG_SB_BASE, REG_SB_CMD) & 0x80) == 0) {
@@ -62,7 +62,7 @@ static void dev_command(u32_t base, u32_t cmd) {
/* ====== Mixer handling interface ====== */
/* Write the data to mixer register (### WRITE_MIXER_REG ###) */
void dev_mixer_write(u32_t *base, u32_t reg, u32_t val) {
void dev_mixer_write(uint32_t *base, uint32_t reg, uint32_t val) {
sdr_out8(base[0] + REG_SB_BASE, REG_MIXER_ADDR, reg);
micro_delay(100);
sdr_out8(base[0] + REG_SB_BASE, REG_MIXER_DATA, val);
@@ -70,8 +70,8 @@ void dev_mixer_write(u32_t *base, u32_t reg, u32_t val) {
}
/* Read the data from mixer register (### READ_MIXER_REG ###) */
u32_t dev_mixer_read(u32_t *base, u32_t reg) {
u32_t res;
uint32_t dev_mixer_read(uint32_t *base, uint32_t reg) {
uint32_t res;
sdr_out8(base[0] + REG_SB_BASE, REG_MIXER_ADDR, reg);
micro_delay(100);
res = sdr_in8(base[0] + REG_SB_BASE, REG_MIXER_DATA);
@@ -83,8 +83,8 @@ u32_t dev_mixer_read(u32_t *base, u32_t reg) {
/* ====== Developer interface ======*/
/* Reset the device (### RESET_HARDWARE_CAN_FAIL ###)
* -- Return OK means success, Others means failure */
static int dev_reset(u32_t *base) {
u32_t i, base0 = base[0];
static int dev_reset(uint32_t *base) {
uint32_t i, base0 = base[0];
sdr_out8(base0, REG_SB_RESET, 1);
micro_delay(10);
sdr_out8(base0, REG_SB_RESET, 0);
@@ -101,8 +101,8 @@ static int dev_reset(u32_t *base) {
}
/* Configure hardware registers (### CONF_HARDWARE ###) */
static void dev_configure(u32_t *base) {
u32_t i, data, base0 = base[0];
static void dev_configure(uint32_t *base) {
uint32_t i, data, base0 = base[0];
data = dev_mixer_read(base, REG_SB_CONFIG);
dev_mixer_write(base, REG_SB_CONFIG | REG_SB_CTRL,
data | CMD_MIXER_WRITE_ENABLE);
@@ -117,23 +117,23 @@ static void dev_configure(u32_t *base) {
}
/* Initialize the mixer (### INIT_MIXER ###) */
static void dev_init_mixer(u32_t *base) {
static void dev_init_mixer(uint32_t *base) {
// dev_mixer_write(base, 0, 0);
}
/* Set DAC and ADC sample rate (### SET_SAMPLE_RATE ###) */
static void dev_set_sample_rate(u32_t *base, uint16_t sample_rate) {
u32_t base0 = base[0];
static void dev_set_sample_rate(uint32_t *base, uint16_t sample_rate) {
uint32_t base0 = base[0];
dev_command(base0, CMD_SAMPLE_RATE_OUT);
dev_command(base0, sample_rate >> 8);
dev_command(base0, sample_rate & 0xff);
}
static u32_t rec_format = 0;
static uint32_t rec_format = 0;
/* Set DAC and ADC format (### SET_FORMAT ###)*/
static void dev_set_format(u32_t *base, u32_t bits, u32_t sign,
u32_t stereo, u32_t sample_count) {
u32_t format = 0, base0 = base[0];
static void dev_set_format(uint32_t *base, uint32_t bits, uint32_t sign,
uint32_t stereo, uint32_t sample_count) {
uint32_t format = 0, base0 = base[0];
if (bits == 16) {
format = CMD_BIT16_AI;
rec_format = 0;
@@ -171,8 +171,8 @@ static void dev_set_format(u32_t *base, u32_t bits, u32_t sign,
}
/* Start the channel (### START_CHANNEL ###) */
static void dev_start_channel(u32_t *base, int sub_dev) {
u32_t base0 = base[0];
static void dev_start_channel(uint32_t *base, int sub_dev) {
uint32_t base0 = base[0];
dev_command(base0, CMD_SOUND_ON);
if (sub_dev == DAC) {
dev_command(base0, CMD_BIT16_DMA_ON);
@@ -183,8 +183,8 @@ static void dev_start_channel(u32_t *base, int sub_dev) {
}
/* Stop the channel (### STOP_CHANNEL ###) */
static void dev_stop_channel(u32_t *base, int sub_dev) {
u32_t base0 = base[0];
static void dev_stop_channel(uint32_t *base, int sub_dev) {
uint32_t base0 = base[0];
if (sub_dev == DAC) {
dev_command(base0, CMD_BIT16_DMA_OFF);
dev_command(base0, CMD_BIT8_DMA_OFF);
@@ -194,8 +194,8 @@ static void dev_stop_channel(u32_t *base, int sub_dev) {
}
/* Set DMA address and length (### SET_DMA ###) */
static void dev_set_dma(u32_t *base, u32_t dma, u32_t len, int sub_dev) {
u32_t base0 = base[0];
static void dev_set_dma(uint32_t *base, uint32_t dma, uint32_t len, int sub_dev) {
uint32_t base0 = base[0];
if (sub_dev == DAC) {
dev_gcr_write(base0, REG_DAC_DMA_ADDR, dma);
dev_gcr_write(base0, REG_DAC_DMA_LEN, (len - 1) | 0x180000);
@@ -207,8 +207,8 @@ static void dev_set_dma(u32_t *base, u32_t dma, u32_t len, int sub_dev) {
}
/* Read current address (### READ_DMA_CURRENT_ADDR ###) */
static u32_t dev_read_dma_current(u32_t *base, int sub_dev) {
u32_t data, base0 = base[0];
static uint32_t dev_read_dma_current(uint32_t *base, int sub_dev) {
uint32_t data, base0 = base[0];
if (sub_dev == DAC)
data = dev_gcr_read(base0, REG_DAC_CUR_ADDR);
else if (sub_dev == ADC)
@@ -217,8 +217,8 @@ static u32_t dev_read_dma_current(u32_t *base, int sub_dev) {
}
/* Pause the DMA (### PAUSE_DMA ###) */
static void dev_pause_dma(u32_t *base, int sub_dev) {
u32_t base0 = base[0];
static void dev_pause_dma(uint32_t *base, int sub_dev) {
uint32_t base0 = base[0];
if (sub_dev == DAC) {
dev_command(base0, CMD_BIT16_DMA_OFF);
dev_command(base0, CMD_BIT8_DMA_OFF);
@@ -228,8 +228,8 @@ static void dev_pause_dma(u32_t *base, int sub_dev) {
}
/* Resume the DMA (### RESUME_DMA ###) */
static void dev_resume_dma(u32_t *base, int sub_dev) {
u32_t base0 = base[0];
static void dev_resume_dma(uint32_t *base, int sub_dev) {
uint32_t base0 = base[0];
if (sub_dev == DAC) {
dev_command(base0, CMD_BIT16_DMA_ON);
dev_command(base0, CMD_BIT8_DMA_ON);
@@ -240,8 +240,8 @@ static void dev_resume_dma(u32_t *base, int sub_dev) {
/* Read and clear interrupt status (### READ_CLEAR_INTR_STS ###)
* -- Return interrupt status */
static u32_t dev_read_clear_intr_status(u32_t *base) {
u32_t data, status, base0 = base[0];
static uint32_t dev_read_clear_intr_status(uint32_t *base) {
uint32_t data, status, base0 = base[0];
status = sdr_in8(base0, REG_INTR_STS);
sdr_out8(base0, REG_INTR_STS, status);
data = dev_mixer_read(base, REG_SB_IRQ_STATUS);
@@ -255,8 +255,8 @@ static u32_t dev_read_clear_intr_status(u32_t *base) {
}
/* Enable or disable interrupt (### INTR_ENABLE_DISABLE ###) */
static void dev_intr_enable(u32_t *base, int flag) {
u32_t data, base0 = base[0];
static void dev_intr_enable(uint32_t *base, int flag) {
uint32_t data, base0 = base[0];
data = dev_gcr_read(base0, REG_INTR_CTRL);
if (flag == INTR_ENABLE)
dev_gcr_write(base0, REG_INTR_CTRL, data | CMD_INTR_ENABLE);
@@ -268,7 +268,7 @@ static void dev_intr_enable(u32_t *base, int flag) {
/* Probe the device */
static int dev_probe(void) {
int devind, i, ioflag;
u32_t device, bar, size, base;
uint32_t device, bar, size, base;
uint16_t vid, did, temp;
uint8_t *reg;
@@ -299,7 +299,7 @@ static int dev_probe(void) {
printf("SDR: Fail to map hardware registers from PCI\n");
return -EIO;
}
dev.base[i] = (u32_t)reg;
dev.base[i] = (uint32_t)reg;
}
#else
/* Get PCI BAR0-5 */
@@ -325,25 +325,25 @@ static int dev_probe(void) {
}
/* Set sample rate in configuration */
static int set_sample_rate(u32_t rate, int num) {
static int set_sample_rate(uint32_t rate, int num) {
aud_conf[num].sample_rate = rate;
return OK;
}
/* Set stereo in configuration */
static int set_stereo(u32_t stereo, int num) {
static int set_stereo(uint32_t stereo, int num) {
aud_conf[num].stereo = stereo;
return OK;
}
/* Set sample bits in configuration */
static int set_bits(u32_t bits, int num) {
static int set_bits(uint32_t bits, int num) {
aud_conf[num].nr_of_bits = bits;
return OK;
}
/* Set fragment size in configuration */
static int set_frag_size(u32_t frag_size, int num) {
static int set_frag_size(uint32_t frag_size, int num) {
if (frag_size > (sub_dev[num].DmaSize / sub_dev[num].NrOfDmaFragments) ||
frag_size < sub_dev[num].MinFragmentSize) {
return EINVAL;
@@ -353,20 +353,20 @@ static int set_frag_size(u32_t frag_size, int num) {
}
/* Set frame sign in configuration */
static int set_sign(u32_t val, int num) {
static int set_sign(uint32_t val, int num) {
aud_conf[num].sign = val;
return OK;
}
/* Get maximum fragment size */
static int get_max_frag_size(u32_t *val, int *len, int num) {
static int get_max_frag_size(uint32_t *val, int *len, int num) {
*len = sizeof(*val);
*val = (sub_dev[num].DmaSize / sub_dev[num].NrOfDmaFragments);
return OK;
}
/* Return 1 if there are free buffers */
static int free_buf(u32_t *val, int *len, int num) {
static int free_buf(uint32_t *val, int *len, int num) {
*len = sizeof(*val);
if (sub_dev[num].BufLength == sub_dev[num].NrOfExtraBuffers)
*val = 0;
@@ -376,11 +376,11 @@ static int free_buf(u32_t *val, int *len, int num) {
}
/* Get the current sample counter */
static int get_samples_in_buf(u32_t *result, int *len, int chan) {
u32_t res;
static int get_samples_in_buf(uint32_t *result, int *len, int chan) {
uint32_t res;
/* READ_DMA_CURRENT_ADDR */
res = dev_read_dma_current(dev.base, chan);
*result = (u32_t)(sub_dev[chan].BufLength * 8192) + res;
*result = (uint32_t)(sub_dev[chan].BufLength * 8192) + res;
return OK;
}
@@ -503,7 +503,7 @@ int drv_start(int sub_dev, int DmaMode) {
/* ======= [Audio interface] Driver start ======= */
int drv_stop(int sub_dev) {
u32_t data;
uint32_t data;
/* INTR_ENABLE_DISABLE */
dev_intr_enable(dev.base, INTR_DISABLE);
@@ -527,19 +527,19 @@ int drv_io_ctl(unsigned long request, void *val, int *len, int sub_dev) {
int status;
switch (request) {
case DSPIORATE:
status = set_sample_rate(*((u32_t *)val), sub_dev);
status = set_sample_rate(*((uint32_t *)val), sub_dev);
break;
case DSPIOSTEREO:
status = set_stereo(*((u32_t *)val), sub_dev);
status = set_stereo(*((uint32_t *)val), sub_dev);
break;
case DSPIOBITS:
status = set_bits(*((u32_t *)val), sub_dev);
status = set_bits(*((uint32_t *)val), sub_dev);
break;
case DSPIOSIZE:
status = set_frag_size(*((u32_t *)val), sub_dev);
status = set_frag_size(*((uint32_t *)val), sub_dev);
break;
case DSPIOSIGN:
status = set_sign(*((u32_t *)val), sub_dev);
status = set_sign(*((uint32_t *)val), sub_dev);
break;
case DSPIOMAX:
status = get_max_frag_size(val, len, sub_dev);
@@ -581,13 +581,13 @@ int drv_get_irq(char *irq) {
}
/* ======= [Audio interface] Get fragment size ======= */
int drv_get_frag_size(u32_t *frag_size, int sub_dev) {
int drv_get_frag_size(uint32_t *frag_size, int sub_dev) {
*frag_size = aud_conf[sub_dev].fragment_size;
return OK;
}
/* ======= [Audio interface] Set DMA channel ======= */
int drv_set_dma(u32_t dma, u32_t length, int chan) {
int drv_set_dma(uint32_t dma, uint32_t length, int chan) {
#ifdef DMA_LENGTH_BY_FRAME
length = length / (aud_conf[chan].nr_of_bits * (aud_conf[chan].stereo + 1) / 8);
#endif
@@ -598,7 +598,7 @@ int drv_set_dma(u32_t dma, u32_t length, int chan) {
/* ======= [Audio interface] Get interrupt summary status ======= */
int drv_int_sum(void) {
u32_t status;
uint32_t status;
/* ### READ_CLEAR_INTR_STS ### */
status = dev_read_clear_intr_status(dev.base);
dev.intr_status = status;
@@ -610,7 +610,7 @@ int drv_int_sum(void) {
/* ======= [Audio interface] Handle interrupt status ======= */
int drv_int(int sub_dev) {
u32_t mask;
uint32_t mask;
/* ### CHECK_INTR_DAC ### */
if (sub_dev == DAC)

22
minix/drivers/audio/als4000/als4000.h
View File

@@ -82,18 +82,18 @@
#define CMD_REC_STEREO 0x20
#define CMD_REC_SIGN 0x10
static u32_t g_sample_rate[] = {
static uint32_t g_sample_rate[] = {
5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000
};
/* Driver Data Structure */
typedef struct aud_sub_dev_conf_t {
u32_t stereo;
uint32_t stereo;
uint16_t sample_rate;
u32_t nr_of_bits;
u32_t sign;
u32_t busy;
u32_t fragment_size;
uint32_t nr_of_bits;
uint32_t sign;
uint32_t busy;
uint32_t fragment_size;
uint8_t format;
} aud_sub_dev_conf_t;
@@ -101,14 +101,14 @@ typedef struct DEV_STRUCT {
char *name;
uint16_t vid;
uint16_t did;
u32_t devind;
u32_t base[6];
uint32_t devind;
uint32_t base[6];
char irq;
char revision;
u32_t intr_status;
uint32_t intr_status;
} DEV_STRUCT;
void dev_mixer_write(u32_t *base, u32_t reg, u32_t val);
u32_t dev_mixer_read(u32_t *base, u32_t reg);
void dev_mixer_write(uint32_t *base, uint32_t reg, uint32_t val);
uint32_t dev_mixer_read(uint32_t *base, uint32_t reg);
#endif

22
minix/drivers/audio/als4000/io.h
View File

@@ -6,8 +6,8 @@
#include "als4000.h"
/* I/O function */
static uint8_t my_inb(u32_t port) {
u32_t value;
static uint8_t my_inb(uint32_t port) {
uint32_t value;
int r;
#ifdef DMA_BASE_IOMAP
value = *(volatile uint8_t *)(port);
@@ -19,8 +19,8 @@ static uint8_t my_inb(u32_t port) {
}
#define sdr_in8(port, offset) (my_inb((port) + (offset)))
static uint16_t my_inw(u32_t port) {
u32_t value;
static uint16_t my_inw(uint32_t port) {
uint32_t value;
int r;
#ifdef DMA_BASE_IOMAP
value = *(volatile uint16_t *)(port);
@@ -32,11 +32,11 @@ static uint16_t my_inw(u32_t port) {
}
#define sdr_in16(port, offset) (my_inw((port) + (offset)))
static u32_t my_inl(u32_t port) {
u32_t value;
static uint32_t my_inl(uint32_t port) {
uint32_t value;
int r;
#ifdef DMA_BASE_IOMAP
value = *(volatile u32_t *)(port);
value = *(volatile uint32_t *)(port);
#else
if ((r = sys_inl(port, &value)) != OK)
printf("SDR: sys_inl failed: %d\n", r);
@@ -45,7 +45,7 @@ static u32_t my_inl(u32_t port) {
}
#define sdr_in32(port, offset) (my_inl((port) + (offset)))
static void my_outb(u32_t port, u32_t value) {
static void my_outb(uint32_t port, uint32_t value) {
int r;
#ifdef DMA_BASE_IOMAP
*(volatile uint8_t *)(port) = value;
@@ -57,7 +57,7 @@ static void my_outb(u32_t port, u32_t value) {
#define sdr_out8(port, offset, value) \
(my_outb(((port) + (offset)), (value)))
static void my_outw(u32_t port, u32_t value) {
static void my_outw(uint32_t port, uint32_t value) {
int r;
#ifdef DMA_BASE_IOMAP
*(volatile uint16_t *)(port) = value;
@@ -69,10 +69,10 @@ static void my_outw(u32_t port, u32_t value) {
#define sdr_out16(port, offset, value) \
(my_outw(((port) + (offset)), (value)))
static void my_outl(u32_t port, u32_t value) {
static void my_outl(uint32_t port, uint32_t value) {
int r;
#ifdef DMA_BASE_IOMAP
*(volatile u32_t *)(port) = value;
*(volatile uint32_t *)(port) = value;
#else
if ((r = sys_outl(port, value)) != OK)
printf("SDR: sys_outl failed: %d\n", r);

8
minix/drivers/audio/als4000/mixer.c
View File

@@ -7,7 +7,7 @@ uint8_t mixer_value[] = {
0x7e, 0x3d, 0x01, 0x01, 0x00, 0x00, 0x03, 0x00,
0x00, 0x01
};
int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
int get_set_volume(uint32_t *base, struct volume_level *level, int flag) {
int max_level, cmd_left, cmd_right;
max_level = 0x1f;
@@ -76,7 +76,7 @@ int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
#endif
#ifdef MIXER_SB16
int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
int get_set_volume(uint32_t *base, struct volume_level *level, int flag) {
int max_level, shift, cmd_left, cmd_right;
max_level = 0x0f;
@@ -155,7 +155,7 @@ int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
#endif
#ifdef MIXER_AC97
int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
int get_set_volume(uint32_t *base, struct volume_level *level, int flag) {
int max_level, cmd, data;
max_level = 0x1f;
@@ -223,7 +223,7 @@ int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
#endif
/* Set default mixer volume */
void dev_set_default_volume(u32_t *base) {
void dev_set_default_volume(uint32_t *base) {
int i;
#ifdef MIXER_AK4531
for (i = 0; i <= 0x19; i++)

4
minix/drivers/audio/als4000/mixer.h
View File

@@ -56,7 +56,7 @@
#define AC97_RESET 0x00
#endif
int get_set_volume(u32_t *pbase, struct volume_level *level, int flag);
void dev_set_default_volume(u32_t *pbase);
int get_set_volume(uint32_t *pbase, struct volume_level *level, int flag);
void dev_set_default_volume(uint32_t *pbase);
#endif

152
minix/drivers/audio/cmi8738/cmi8738.c
View File

@@ -10,35 +10,35 @@ drv_t drv;
/* internal function */
static int dev_probe(void);
static int set_sample_rate(u32_t rate, int num);
static int set_stereo(u32_t stereo, int num);
static int set_bits(u32_t bits, int sub_dev);
static int set_frag_size(u32_t frag_size, int num);
static int set_sign(u32_t val, int num);
static int get_frag_size(u32_t *val, int *len, int num);
static int free_buf(u32_t *val, int *len, int num);
static int set_sample_rate(uint32_t rate, int num);
static int set_stereo(uint32_t stereo, int num);
static int set_bits(uint32_t bits, int sub_dev);
static int set_frag_size(uint32_t frag_size, int num);
static int set_sign(uint32_t val, int num);
static int get_frag_size(uint32_t *val, int *len, int num);
static int free_buf(uint32_t *val, int *len, int num);
/* developer interface */
static int dev_reset(u32_t *base);
static void dev_configure(u32_t *base);
static void dev_init_mixer(u32_t *base);
static void dev_set_sample_rate(u32_t *base, uint16_t sample_rate);
static void dev_set_format(u32_t *base, u32_t bits, u32_t sign,
u32_t stereo, u32_t sample_count);
static void dev_start_channel(u32_t *base, int sub_dev);
static void dev_stop_channel(u32_t *base, int sub_dev);
static void dev_set_dma(u32_t *base, u32_t dma, u32_t len, int sub_dev);
static u32_t dev_read_dma_current(u32_t *base, int sub_dev);
static void dev_pause_dma(u32_t *base, int sub_dev);
static void dev_resume_dma(u32_t *base, int sub_dev);
static void dev_intr_other(u32_t *base, u32_t status);
static u32_t dev_read_clear_intr_status(u32_t *base);
static void dev_intr_enable(u32_t *base, int flag);
static int dev_reset(uint32_t *base);
static void dev_configure(uint32_t *base);
static void dev_init_mixer(uint32_t *base);
static void dev_set_sample_rate(uint32_t *base, uint16_t sample_rate);
static void dev_set_format(uint32_t *base, uint32_t bits, uint32_t sign,
uint32_t stereo, uint32_t sample_count);
static void dev_start_channel(uint32_t *base, int sub_dev);
static void dev_stop_channel(uint32_t *base, int sub_dev);
static void dev_set_dma(uint32_t *base, uint32_t dma, uint32_t len, int sub_dev);
static uint32_t dev_read_dma_current(uint32_t *base, int sub_dev);
static void dev_pause_dma(uint32_t *base, int sub_dev);
static void dev_resume_dma(uint32_t *base, int sub_dev);
static void dev_intr_other(uint32_t *base, uint32_t status);
static uint32_t dev_read_clear_intr_status(uint32_t *base);
static void dev_intr_enable(uint32_t *base, int flag);
/* ======= Developer implemented function ======= */
/* ====== Self-defined function ====== */
void dev_io_set_clear(u32_t base, u32_t reg, u32_t val, int flag) {
u32_t data;
void dev_io_set_clear(uint32_t base, uint32_t reg, uint32_t val, int flag) {
uint32_t data;
data = sdr_in32(base, reg);
if (flag == 0)
data &= ~val;
@@ -49,15 +49,15 @@ void dev_io_set_clear(u32_t base, u32_t reg, u32_t val, int flag) {
/* ====== Mixer handling interface ======*/
/* Write the data to mixer register (### WRITE_MIXER_REG ###) */
void dev_mixer_write(u32_t *base, u32_t reg, u32_t val) {
u32_t base0 = base[0];
void dev_mixer_write(uint32_t *base, uint32_t reg, uint32_t val) {
uint32_t base0 = base[0];
sdr_out8(base0, REG_SB_ADDR, reg);
sdr_out8(base0, REG_SB_DATA, val);
}
/* Read the data from mixer register (### READ_MIXER_REG ###) */
u32_t dev_mixer_read(u32_t *base, u32_t reg) {
u32_t base0 = base[0];
uint32_t dev_mixer_read(uint32_t *base, uint32_t reg) {
uint32_t base0 = base[0];
sdr_out8(base0, REG_SB_ADDR, reg);
return sdr_in8(base0, REG_SB_DATA);
}
@@ -66,8 +66,8 @@ u32_t dev_mixer_read(u32_t *base, u32_t reg) {
/* Reset the device (### RESET_HARDWARE_CAN_FAIL ###)
* -- Return OK means success, Others means failure */
static int dev_reset(u32_t *base) {
u32_t data, base0 = base[0];
static int dev_reset(uint32_t *base) {
uint32_t data, base0 = base[0];
dev_io_set_clear(base0, REG_MISC_CTRL, CMD_POWER_DOWN, 0);
dev_io_set_clear(base0, REG_MISC_CTRL, CMD_RESET, 1);
micro_delay(100);
@@ -76,8 +76,8 @@ static int dev_reset(u32_t *base) {
}
/* Configure hardware registers (### CONF_HARDWARE ###) */
static void dev_configure(u32_t *base) {
u32_t data, base0 = base[0];
static void dev_configure(uint32_t *base) {
uint32_t data, base0 = base[0];
dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_ADC_C0, 0);
dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_ADC_C1, 1);
dev_io_set_clear(base0, REG_MISC_CTRL, CMD_N4SPK3D, 1);
@@ -88,7 +88,7 @@ static void dev_configure(u32_t *base) {
}
/* Initialize the mixer (### INIT_MIXER ###) */
static void dev_init_mixer(u32_t *base) {
static void dev_init_mixer(uint32_t *base) {
dev_mixer_write(base, 0, 0);
dev_mixer_write(base, MIXER_ADCL, 0x1f);
dev_mixer_write(base, MIXER_ADCR, 0x7f);
@@ -96,9 +96,9 @@ static void dev_init_mixer(u32_t *base) {
}
/* Set DAC and ADC sample rate (### SET_SAMPLE_RATE ###) */
static void dev_set_sample_rate(u32_t *base, uint16_t sample_rate) {
static void dev_set_sample_rate(uint32_t *base, uint16_t sample_rate) {
int i;
u32_t data, rate = 0, base0 = base[0];
uint32_t data, rate = 0, base0 = base[0];
for (i = 0; i < 8; i++) {
if (sample_rate == g_sample_rate[i]) {
rate = i;
@@ -113,9 +113,9 @@ static void dev_set_sample_rate(u32_t *base, uint16_t sample_rate) {
}
/* Set DAC and ADC format (### SET_FORMAT ###)*/
static void dev_set_format(u32_t *base, u32_t bits, u32_t sign,
u32_t stereo, u32_t sample_count) {
u32_t format = 0, data, base0 = base[0];
static void dev_set_format(uint32_t *base, uint32_t bits, uint32_t sign,
uint32_t stereo, uint32_t sample_count) {
uint32_t format = 0, data, base0 = base[0];
if (stereo == 1)
format |= FMT_STEREO;
if (bits == 16)
@@ -132,8 +132,8 @@ static void dev_set_format(u32_t *base, u32_t bits, u32_t sign,
}
/* Start the channel (### START_CHANNEL ###) */
static void dev_start_channel(u32_t *base, int sub_dev) {
u32_t data, base0 = base[0];
static void dev_start_channel(uint32_t *base, int sub_dev) {
uint32_t data, base0 = base[0];
if (sub_dev == DAC) {
dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_ENA_C0, 1);
}
@@ -143,8 +143,8 @@ static void dev_start_channel(u32_t *base, int sub_dev) {
}
/* Stop the channel (### STOP_CHANNEL ###) */
static void dev_stop_channel(u32_t *base, int sub_dev) {
u32_t data, base0 = base[0];
static void dev_stop_channel(uint32_t *base, int sub_dev) {
uint32_t data, base0 = base[0];
if (sub_dev == DAC) {
dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_ENA_C0, 0);
dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_RESET_C0, 1);
@@ -160,8 +160,8 @@ static void dev_stop_channel(u32_t *base, int sub_dev) {
}
/* Set DMA address and length (### SET_DMA ###) */
static void dev_set_dma(u32_t *base, u32_t dma, u32_t len, int sub_dev) {
u32_t base0 = base[0];
static void dev_set_dma(uint32_t *base, uint32_t dma, uint32_t len, int sub_dev) {
uint32_t base0 = base[0];
if (sub_dev == DAC) {
sdr_out32(base0, REG_DAC_DMA_ADDR, dma);
sdr_out16(base0, REG_DAC_DMA_LEN, len - 1);
@@ -173,8 +173,8 @@ static void dev_set_dma(u32_t *base, u32_t dma, u32_t len, int sub_dev) {
}
/* Read current address (### READ_DMA_CURRENT_ADDR ###) */
static u32_t dev_read_dma_current(u32_t *base, int sub_dev) {
u32_t data, base0 = base[0];
static uint32_t dev_read_dma_current(uint32_t *base, int sub_dev) {
uint32_t data, base0 = base[0];
if (sub_dev == DAC)
data = sdr_in16(base0, REG_DAC_CUR_ADDR);
else if (sub_dev == ADC)
@@ -183,8 +183,8 @@ static u32_t dev_read_dma_current(u32_t *base, int sub_dev) {
}
/* Pause the DMA (### PAUSE_DMA ###) */
static void dev_pause_dma(u32_t *base, int sub_dev) {
u32_t base0 = base[0];
static void dev_pause_dma(uint32_t *base, int sub_dev) {
uint32_t base0 = base[0];
if (sub_dev == DAC)
dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_PAUSE_C0, 1);
else if (sub_dev == ADC)
@@ -192,8 +192,8 @@ static void dev_pause_dma(u32_t *base, int sub_dev) {
}
/* Resume the DMA (### RESUME_DMA ###) */
static void dev_resume_dma(u32_t *base, int sub_dev) {
u32_t base0 = base[0];
static void dev_resume_dma(uint32_t *base, int sub_dev) {
uint32_t base0 = base[0];
if (sub_dev == DAC)
dev_io_set_clear(base0, REG_FUNC_CTRL, CMD_PAUSE_C0, 0);
else if (sub_dev == ADC)
@@ -202,8 +202,8 @@ static void dev_resume_dma(u32_t *base, int sub_dev) {
/* Read and clear interrupt status (### READ_CLEAR_INTR_STS ###)
* -- Return interrupt status */
static u32_t dev_read_clear_intr_status(u32_t *base) {
u32_t data, base0 = base[0];
static uint32_t dev_read_clear_intr_status(uint32_t *base) {
uint32_t data, base0 = base[0];
data = sdr_in32(base0, REG_INTR_STS);
dev_intr_enable(base, INTR_DISABLE);
dev_intr_enable(base, INTR_ENABLE);
@@ -211,8 +211,8 @@ static u32_t dev_read_clear_intr_status(u32_t *base) {
}
/* Enable or disable interrupt (### INTR_ENBALE_DISABLE ###) */
static void dev_intr_enable(u32_t *base, int flag) {
u32_t data, base0 = base[0];
static void dev_intr_enable(uint32_t *base, int flag) {
uint32_t data, base0 = base[0];
data = sdr_in32(base0, REG_INTR_STS);
if (flag == INTR_ENABLE)
sdr_out32(base0, REG_INTR_CTRL, data | CMD_INTR_ENABLE);
@@ -224,7 +224,7 @@ static void dev_intr_enable(u32_t *base, int flag) {
/* Probe the device */
static int dev_probe(void) {
int devind, i, ioflag;
u32_t device, bar, size, base;
uint32_t device, bar, size, base;
uint16_t vid, did, temp;
uint8_t *reg;
@@ -255,7 +255,7 @@ static int dev_probe(void) {
printf("SDR: Fail to map hardware registers from PCI\n");
return -EIO;
}
dev.base[i] = (u32_t)reg;
dev.base[i] = (uint32_t)reg;
}
#else
/* Get PCI BAR0-5 */
@@ -281,25 +281,25 @@ static int dev_probe(void) {
}
/* Set sample rate in configuration */
static int set_sample_rate(u32_t rate, int num) {
static int set_sample_rate(uint32_t rate, int num) {
aud_conf[num].sample_rate = rate;
return OK;
}
/* Set stereo in configuration */
static int set_stereo(u32_t stereo, int num) {
static int set_stereo(uint32_t stereo, int num) {
aud_conf[num].stereo = stereo;
return OK;
}
/* Set sample bits in configuration */
static int set_bits(u32_t bits, int num) {
static int set_bits(uint32_t bits, int num) {
aud_conf[num].nr_of_bits = bits;
return OK;
}
/* Set fragment size in configuration */
static int set_frag_size(u32_t frag_size, int num) {
static int set_frag_size(uint32_t frag_size, int num) {
if (frag_size > (sub_dev[num].DmaSize / sub_dev[num].NrOfDmaFragments) ||
frag_size < sub_dev[num].MinFragmentSize) {
return EINVAL;
@@ -309,20 +309,20 @@ static int set_frag_size(u32_t frag_size, int num) {
}
/* Set frame sign in configuration */
static int set_sign(u32_t val, int num) {
static int set_sign(uint32_t val, int num) {
aud_conf[num].sign = val;
return OK;
}
/* Get maximum fragment size */
static int get_max_frag_size(u32_t *val, int *len, int num) {
static int get_max_frag_size(uint32_t *val, int *len, int num) {
*len = sizeof(*val);
*val = (sub_dev[num].DmaSize / sub_dev[num].NrOfDmaFragments);
return OK;
}
/* Return 1 if there are free buffers */
static int free_buf(u32_t *val, int *len, int num) {
static int free_buf(uint32_t *val, int *len, int num) {
*len = sizeof(*val);
if (sub_dev[num].BufLength == sub_dev[num].NrOfExtraBuffers)
*val = 0;
@@ -332,11 +332,11 @@ static int free_buf(u32_t *val, int *len, int num) {
}
/* Get the current sample counter */
static int get_samples_in_buf(u32_t *result, int *len, int chan) {
u32_t res;
static int get_samples_in_buf(uint32_t *result, int *len, int chan) {
uint32_t res;
/* READ_DMA_CURRENT_ADDR */
res = dev_read_dma_current(dev.base, chan);
*result = (u32_t)(sub_dev[chan].BufLength * 8192) + res;
*result = (uint32_t)(sub_dev[chan].BufLength * 8192) + res;
return OK;
}
@@ -459,7 +459,7 @@ int drv_start(int sub_dev, int DmaMode) {
/* ======= [Audio interface] Driver start ======= */
int drv_stop(int sub_dev) {
u32_t data;
uint32_t data;
/* INTR_ENABLE_DISABLE */
dev_intr_enable(dev.base, INTR_DISABLE);
@@ -483,19 +483,19 @@ int drv_io_ctl(unsigned long request, void *val, int *len, int sub_dev) {
int status;
switch (request) {
case DSPIORATE:
status = set_sample_rate(*((u32_t *)val), sub_dev);
status = set_sample_rate(*((uint32_t *)val), sub_dev);
break;
case DSPIOSTEREO:
status = set_stereo(*((u32_t *)val), sub_dev);
status = set_stereo(*((uint32_t *)val), sub_dev);
break;
case DSPIOBITS:
status = set_bits(*((u32_t *)val), sub_dev);
status = set_bits(*((uint32_t *)val), sub_dev);
break;
case DSPIOSIZE:
status = set_frag_size(*((u32_t *)val), sub_dev);
status = set_frag_size(*((uint32_t *)val), sub_dev);
break;
case DSPIOSIGN:
status = set_sign(*((u32_t *)val), sub_dev);
status = set_sign(*((uint32_t *)val), sub_dev);
break;
case DSPIOMAX:
status = get_max_frag_size(val, len, sub_dev);
@@ -537,13 +537,13 @@ int drv_get_irq(char *irq) {
}
/* ======= [Audio interface] Get fragment size ======= */
int drv_get_frag_size(u32_t *frag_size, int sub_dev) {
int drv_get_frag_size(uint32_t *frag_size, int sub_dev) {
*frag_size = aud_conf[sub_dev].fragment_size;
return OK;
}
/* ======= [Audio interface] Set DMA channel ======= */
int drv_set_dma(u32_t dma, u32_t length, int chan) {
int drv_set_dma(uint32_t dma, uint32_t length, int chan) {
#ifdef DMA_LENGTH_BY_FRAME
length = length / (aud_conf[chan].nr_of_bits * (aud_conf[chan].stereo + 1) / 8);
#endif
@@ -554,7 +554,7 @@ int drv_set_dma(u32_t dma, u32_t length, int chan) {
/* ======= [Audio interface] Get interrupt summary status ======= */
int drv_int_sum(void) {
u32_t status;
uint32_t status;
/* ### READ_CLEAR_INTR_STS ### */
status = dev_read_clear_intr_status(dev.base);
dev.intr_status = status;
@@ -566,7 +566,7 @@ int drv_int_sum(void) {
/* ======= [Audio interface] Handle interrupt status ======= */
int drv_int(int sub_dev) {
u32_t mask;
uint32_t mask;
/* ### CHECK_INTR_DAC ### */
if (sub_dev == DAC)

22
minix/drivers/audio/cmi8738/cmi8738.h
View File

@@ -81,18 +81,18 @@
#define CMD_INTR_ENABLE 0x00030000
static u32_t g_sample_rate[] = {
static uint32_t g_sample_rate[] = {
5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000
};
/* Driver Data Structure */
typedef struct aud_sub_dev_conf_t {
u32_t stereo;
uint32_t stereo;
uint16_t sample_rate;
u32_t nr_of_bits;
u32_t sign;
u32_t busy;
u32_t fragment_size;
uint32_t nr_of_bits;
uint32_t sign;
uint32_t busy;
uint32_t fragment_size;
uint8_t format;
} aud_sub_dev_conf_t;
@@ -100,14 +100,14 @@ typedef struct DEV_STRUCT {
char *name;
uint16_t vid;
uint16_t did;
u32_t devind;
u32_t base[6];
uint32_t devind;
uint32_t base[6];
char irq;
char revision;
u32_t intr_status;
uint32_t intr_status;
} DEV_STRUCT;
void dev_mixer_write(u32_t *base, u32_t reg, u32_t val);
u32_t dev_mixer_read(u32_t *base, u32_t reg);
void dev_mixer_write(uint32_t *base, uint32_t reg, uint32_t val);
uint32_t dev_mixer_read(uint32_t *base, uint32_t reg);
#endif

22
minix/drivers/audio/cmi8738/io.h
View File

@@ -6,8 +6,8 @@
#include "cmi8738.h"
/* I/O function */
static uint8_t my_inb(u32_t port) {
u32_t value;
static uint8_t my_inb(uint32_t port) {
uint32_t value;
int r;
#ifdef DMA_BASE_IOMAP
value = *(volatile uint8_t *)(port);
@@ -19,8 +19,8 @@ static uint8_t my_inb(u32_t port) {
}
#define sdr_in8(port, offset) (my_inb((port) + (offset)))
static uint16_t my_inw(u32_t port) {
u32_t value;
static uint16_t my_inw(uint32_t port) {
uint32_t value;
int r;
#ifdef DMA_BASE_IOMAP
value = *(volatile uint16_t *)(port);
@@ -32,11 +32,11 @@ static uint16_t my_inw(u32_t port) {
}
#define sdr_in16(port, offset) (my_inw((port) + (offset)))
static u32_t my_inl(u32_t port) {
u32_t value;
static uint32_t my_inl(uint32_t port) {
uint32_t value;
int r;
#ifdef DMA_BASE_IOMAP
value = *(volatile u32_t *)(port);
value = *(volatile uint32_t *)(port);
#else
if ((r = sys_inl(port, &value)) != OK)
printf("SDR: sys_inl failed: %d\n", r);
@@ -45,7 +45,7 @@ static u32_t my_inl(u32_t port) {
}
#define sdr_in32(port, offset) (my_inl((port) + (offset)))
static void my_outb(u32_t port, u32_t value) {
static void my_outb(uint32_t port, uint32_t value) {
int r;
#ifdef DMA_BASE_IOMAP
*(volatile uint8_t *)(port) = value;
@@ -57,7 +57,7 @@ static void my_outb(u32_t port, u32_t value) {
#define sdr_out8(port, offset, value) \
(my_outb(((port) + (offset)), (value)))
static void my_outw(u32_t port, u32_t value) {
static void my_outw(uint32_t port, uint32_t value) {
int r;
#ifdef DMA_BASE_IOMAP
*(volatile uint16_t *)(port) = value;
@@ -69,10 +69,10 @@ static void my_outw(u32_t port, u32_t value) {
#define sdr_out16(port, offset, value) \
(my_outw(((port) + (offset)), (value)))
static void my_outl(u32_t port, u32_t value) {
static void my_outl(uint32_t port, uint32_t value) {
int r;
#ifdef DMA_BASE_IOMAP
*(volatile u32_t *)(port) = value;
*(volatile uint32_t *)(port) = value;
#else
if ((r = sys_outl(port, value)) != OK)
printf("SDR: sys_outl failed: %d\n", r);

8
minix/drivers/audio/cmi8738/mixer.c
View File

@@ -7,7 +7,7 @@ uint8_t mixer_value[] = {
0x7e, 0x3d, 0x01, 0x01, 0x00, 0x00, 0x03, 0x00,
0x00, 0x01
};
int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
int get_set_volume(uint32_t *base, struct volume_level *level, int flag) {
int max_level, cmd_left, cmd_right;
max_level = 0x1f;
@@ -76,7 +76,7 @@ int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
#endif
#ifdef MIXER_SB16
int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
int get_set_volume(uint32_t *base, struct volume_level *level, int flag) {
int max_level, shift, cmd_left, cmd_right;
max_level = 0x0f;
@@ -155,7 +155,7 @@ int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
#endif
#ifdef MIXER_AC97
int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
int get_set_volume(uint32_t *base, struct volume_level *level, int flag) {
int max_level, cmd, data;
max_level = 0x1f;
@@ -223,7 +223,7 @@ int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
#endif
/* Set default mixer volume */
void dev_set_default_volume(u32_t *base) {
void dev_set_default_volume(uint32_t *base) {
int i;
#ifdef MIXER_AK4531
for (i = 0; i <= 0x19; i++)

4
minix/drivers/audio/cmi8738/mixer.h
View File

@@ -56,7 +56,7 @@
#define AC97_RESET 0x00
#endif
int get_set_volume(u32_t *pbase, struct volume_level *level, int flag);
void dev_set_default_volume(u32_t *pbase);
int get_set_volume(uint32_t *pbase, struct volume_level *level, int flag);
void dev_set_default_volume(uint32_t *pbase);
#endif

148
minix/drivers/audio/cs4281/cs4281.c
View File

@@ -10,38 +10,38 @@ drv_t drv;
/* internal function */
static int dev_probe(void);
static int set_sample_rate(u32_t rate, int num);
static int set_stereo(u32_t stereo, int num);
static int set_bits(u32_t bits, int sub_dev);
static int set_frag_size(u32_t frag_size, int num);
static int set_sign(u32_t val, int num);
static int get_frag_size(u32_t *val, int *len, int num);
static int free_buf(u32_t *val, int *len, int num);
static int set_sample_rate(uint32_t rate, int num);
static int set_stereo(uint32_t stereo, int num);
static int set_bits(uint32_t bits, int sub_dev);
static int set_frag_size(uint32_t frag_size, int num);
static int set_sign(uint32_t val, int num);
static int get_frag_size(uint32_t *val, int *len, int num);
static int free_buf(uint32_t *val, int *len, int num);
/* developer interface */
static int dev_reset(u32_t *base);
static void dev_configure(u32_t *base);
static void dev_init_mixer(u32_t *base);
static void dev_set_sample_rate(u32_t *base, uint16_t sample_rate);
static void dev_set_format(u32_t *base, u32_t bits, u32_t sign,
u32_t stereo, u32_t sample_count);
static void dev_start_channel(u32_t *base, int sub_dev);
static void dev_stop_channel(u32_t *base, int sub_dev);
static void dev_set_dma(u32_t *base, u32_t dma, u32_t len, int sub_dev);
static u32_t dev_read_dma_current(u32_t *base, int sub_dev);
static void dev_pause_dma(u32_t *base, int sub_dev);
static void dev_resume_dma(u32_t *base, int sub_dev);
static void dev_intr_other(u32_t *base, u32_t status);
static u32_t dev_read_clear_intr_status(u32_t *base);
static void dev_intr_enable(u32_t *base, int flag);
static int dev_reset(uint32_t *base);
static void dev_configure(uint32_t *base);
static void dev_init_mixer(uint32_t *base);
static void dev_set_sample_rate(uint32_t *base, uint16_t sample_rate);
static void dev_set_format(uint32_t *base, uint32_t bits, uint32_t sign,
uint32_t stereo, uint32_t sample_count);
static void dev_start_channel(uint32_t *base, int sub_dev);
static void dev_stop_channel(uint32_t *base, int sub_dev);
static void dev_set_dma(uint32_t *base, uint32_t dma, uint32_t len, int sub_dev);
static uint32_t dev_read_dma_current(uint32_t *base, int sub_dev);
static void dev_pause_dma(uint32_t *base, int sub_dev);
static void dev_resume_dma(uint32_t *base, int sub_dev);
static void dev_intr_other(uint32_t *base, uint32_t status);
static uint32_t dev_read_clear_intr_status(uint32_t *base);
static void dev_intr_enable(uint32_t *base, int flag);
/* ======= Developer implemented function ======= */
/* ====== Self-defined function ====== */
/* ====== Mixer handling interface ======*/
/* Write the data to mixer register (### WRITE_MIXER_REG ###) */
void dev_mixer_write(u32_t *base, u32_t reg, u32_t val) {
u32_t i, data, base0 = base[0];
void dev_mixer_write(uint32_t *base, uint32_t reg, uint32_t val) {
uint32_t i, data, base0 = base[0];
sdr_out32(base0, REG_CODEC_ADDR, reg);
sdr_out32(base0, REG_CODEC_DATA, val);
sdr_out32(base0, REG_CODEC_CTRL, 0x0e);
@@ -57,8 +57,8 @@ void dev_mixer_write(u32_t *base, u32_t reg, u32_t val) {
}
/* Read the data from mixer register (### READ_MIXER_REG ###) */
u32_t dev_mixer_read(u32_t *base, u32_t reg) {
u32_t i, data, base0 = base[0];
uint32_t dev_mixer_read(uint32_t *base, uint32_t reg) {
uint32_t i, data, base0 = base[0];
sdr_in32(base0, REG_CODEC_SDA);
sdr_out32(base0, REG_CODEC_ADDR, reg & 0xff);
sdr_out32(base0, REG_CODEC_DATA, 0);
@@ -86,8 +86,8 @@ u32_t dev_mixer_read(u32_t *base, u32_t reg) {
/* Reset the device (### RESET_HARDWARE_CAN_FAIL ###)
* -- Return OK means success, Others means failure */
static int dev_reset(u32_t *base) {
u32_t data, base0 = base[0];
static int dev_reset(uint32_t *base) {
uint32_t data, base0 = base[0];
data = sdr_in32(base0, REG_POWER_EXT);
if (data & CMD_POWER_DOWN)
sdr_out32(base0, REG_POWER_EXT, data & ~CMD_POWER_DOWN);
@@ -109,8 +109,8 @@ static int dev_reset(u32_t *base) {
}
/* Configure hardware registers (### CONF_HARDWARE ###) */
static void dev_configure(u32_t *base) {
u32_t i, data, base0 = base[0];
static void dev_configure(uint32_t *base) {
uint32_t i, data, base0 = base[0];
sdr_out32(base0, REG_MASTER_CTRL, CMD_PORT_TIMING | CMD_AC97_MODE |
CMD_MASTER_SERIAL);
sdr_out32(base0, REG_CLK_CTRL, 0x10);
@@ -127,13 +127,13 @@ static void dev_configure(u32_t *base) {
}
/* Initialize the mixer (### INIT_MIXER ###) */
static void dev_init_mixer(u32_t *base) {
static void dev_init_mixer(uint32_t *base) {
dev_mixer_write(base, 0, 0);
}
/* Set DAC and ADC sample rate (### SET_SAMPLE_RATE ###) */
static void dev_set_sample_rate(u32_t *base, uint16_t sample_rate) {
u32_t i, data = 0, base0 = base[0];
static void dev_set_sample_rate(uint32_t *base, uint16_t sample_rate) {
uint32_t i, data = 0, base0 = base[0];
for (i = 0; i < 6; i++) {
if (g_sample_rate[i] == sample_rate) {
data = i;
@@ -145,9 +145,9 @@ static void dev_set_sample_rate(u32_t *base, uint16_t sample_rate) {
}
/* Set DAC and ADC format (### SET_FORMAT ###)*/
static void dev_set_format(u32_t *base, u32_t bits, u32_t sign,
u32_t stereo, u32_t sample_count) {
u32_t base0 = base[0];
static void dev_set_format(uint32_t *base, uint32_t bits, uint32_t sign,
uint32_t stereo, uint32_t sample_count) {
uint32_t base0 = base[0];
dmr_data = CMD_DMR_INIT;
if (stereo == 0)
dmr_data |= CMD_DMR_MONO;
@@ -163,8 +163,8 @@ static void dev_set_format(u32_t *base, u32_t bits, u32_t sign,
}
/* Start the channel (### START_CHANNEL ###) */
static void dev_start_channel(u32_t *base, int sub_dev) {
u32_t temp, base0 = base[0];
static void dev_start_channel(uint32_t *base, int sub_dev) {
uint32_t temp, base0 = base[0];
dcr_data = 0x30001;
if (sub_dev == DAC)
@@ -194,8 +194,8 @@ static void dev_start_channel(u32_t *base, int sub_dev) {
}
/* Stop the channel (### STOP_CHANNEL ###) */
static void dev_stop_channel(u32_t *base, int sub_dev) {
u32_t base0 = base[0];
static void dev_stop_channel(uint32_t *base, int sub_dev) {
uint32_t base0 = base[0];
dmr_data &= ~(CMD_DMR_DMA | CMD_DMR_POLL);
dcr_data |= ~CMD_DCR_MASK;
fcr_data &= ~CMD_FCR_FEN;
@@ -212,8 +212,8 @@ static void dev_stop_channel(u32_t *base, int sub_dev) {
}
/* Set DMA address and length (### SET_DMA ###) */
static void dev_set_dma(u32_t *base, u32_t dma, u32_t len, int sub_dev) {
u32_t base0 = base[0];
static void dev_set_dma(uint32_t *base, uint32_t dma, uint32_t len, int sub_dev) {
uint32_t base0 = base[0];
if (sub_dev == DAC) {
sdr_out32(base0, REG_DAC_DMA_ADDR, dma);
@@ -226,8 +226,8 @@ static void dev_set_dma(u32_t *base, u32_t dma, u32_t len, int sub_dev) {
}
/* Read current address (### READ_DMA_CURRENT_ADDR ###) */
static u32_t dev_read_dma_current(u32_t *base, int sub_dev) {
u32_t data, base0 = base[0];
static uint32_t dev_read_dma_current(uint32_t *base, int sub_dev) {
uint32_t data, base0 = base[0];
if (sub_dev == DAC)
data = sdr_in32(base0, REG_DAC_DCC);
else if (sub_dev == ADC)
@@ -237,8 +237,8 @@ static u32_t dev_read_dma_current(u32_t *base, int sub_dev) {
}
/* Pause the DMA (### PAUSE_DMA ###) */
static void dev_pause_dma(u32_t *base, int sub_dev) {
u32_t base0 = base[0];
static void dev_pause_dma(uint32_t *base, int sub_dev) {
uint32_t base0 = base[0];
dcr_data |= CMD_DCR_MASK;
fcr_data |= CMD_FCR_FEN;
if (sub_dev == DAC) {
@@ -254,8 +254,8 @@ static void dev_pause_dma(u32_t *base, int sub_dev) {
}
/* Resume the DMA (### RESUME_DMA ###) */
static void dev_resume_dma(u32_t *base, int sub_dev) {
u32_t base0 = base[0];
static void dev_resume_dma(uint32_t *base, int sub_dev) {
uint32_t base0 = base[0];
dcr_data &= ~CMD_DCR_MASK;
fcr_data &= ~CMD_FCR_FEN;
if (sub_dev == DAC) {
@@ -272,8 +272,8 @@ static void dev_resume_dma(u32_t *base, int sub_dev) {
/* Read and clear interrupt stats (### READ_CLEAR_INTR_STS ###)
* -- Return interrupt status */
static u32_t dev_read_clear_intr_status(u32_t *base) {
u32_t status, base0 = base[0];
static uint32_t dev_read_clear_intr_status(uint32_t *base) {
uint32_t status, base0 = base[0];
status = sdr_in32(base0, REG_INTR_STS);
sdr_in32(base0, REG_DAC_HDSR);
sdr_in32(base0, REG_ADC_HDSR);
@@ -282,8 +282,8 @@ static u32_t dev_read_clear_intr_status(u32_t *base) {
}
/* Enable or disable interrupt (### INTR_ENABLE_DISABLE ###) */
static void dev_intr_enable(u32_t *base, int flag) {
u32_t data, base0 = base[0];
static void dev_intr_enable(uint32_t *base, int flag) {
uint32_t data, base0 = base[0];
if (flag == INTR_ENABLE) {
sdr_out32(base0, REG_INTR_CTRL, CMD_INTR_ENABLE);
sdr_out32(base0, REG_INTR_MASK, ~(CMD_INTR_DMA | CMD_INTR_DMA0 |
@@ -299,7 +299,7 @@ static void dev_intr_enable(u32_t *base, int flag) {
/* Probe the device */
static int dev_probe(void) {
int devind, i, ioflag;
u32_t device, bar, size, base;
uint32_t device, bar, size, base;
uint16_t vid, did, temp;
uint8_t *reg;
@@ -330,7 +330,7 @@ static int dev_probe(void) {
printf("SDR: Fail to map hardware registers from PCI\n");
return -EIO;
}
dev.base[i] = (u32_t)reg;
dev.base[i] = (uint32_t)reg;
}
#else
/* Get PCI BAR0-5 */
@@ -356,25 +356,25 @@ static int dev_probe(void) {
}
/* Set sample rate in configuration */
static int set_sample_rate(u32_t rate, int num) {
static int set_sample_rate(uint32_t rate, int num) {
aud_conf[num].sample_rate = rate;
return OK;
}
/* Set stereo in configuration */
static int set_stereo(u32_t stereo, int num) {
static int set_stereo(uint32_t stereo, int num) {
aud_conf[num].stereo = stereo;
return OK;
}
/* Set sample bits in configuration */
static int set_bits(u32_t bits, int num) {
static int set_bits(uint32_t bits, int num) {
aud_conf[num].nr_of_bits = bits;
return OK;
}
/* Set fragment size in configuration */
static int set_frag_size(u32_t frag_size, int num) {
static int set_frag_size(uint32_t frag_size, int num) {
if (frag_size > (sub_dev[num].DmaSize / sub_dev[num].NrOfDmaFragments) ||
frag_size < sub_dev[num].MinFragmentSize) {
return EINVAL;
@@ -384,20 +384,20 @@ static int set_frag_size(u32_t frag_size, int num) {
}
/* Set frame sign in configuration */
static int set_sign(u32_t val, int num) {
static int set_sign(uint32_t val, int num) {
aud_conf[num].sign = val;
return OK;
}
/* Get maximum fragment size */
static int get_max_frag_size(u32_t *val, int *len, int num) {
static int get_max_frag_size(uint32_t *val, int *len, int num) {
*len = sizeof(*val);
*val = (sub_dev[num].DmaSize / sub_dev[num].NrOfDmaFragments);
return OK;
}
/* Return 1 if there are free buffers */
static int free_buf(u32_t *val, int *len, int num) {
static int free_buf(uint32_t *val, int *len, int num) {
*len = sizeof(*val);
if (sub_dev[num].BufLength == sub_dev[num].NrOfExtraBuffers)
*val = 0;
@@ -407,11 +407,11 @@ static int free_buf(u32_t *val, int *len, int num) {
}
/* Get the current sample counter */
static int get_samples_in_buf(u32_t *result, int *len, int chan) {
u32_t res;
static int get_samples_in_buf(uint32_t *result, int *len, int chan) {
uint32_t res;
/* READ_DMA_CURRENT_ADDR */
res = dev_read_dma_current(dev.base, chan);
*result = (u32_t)(sub_dev[chan].BufLength * 8192) + res;
*result = (uint32_t)(sub_dev[chan].BufLength * 8192) + res;
return OK;
}
@@ -534,7 +534,7 @@ int drv_start(int sub_dev, int DmaMode) {
/* ======= [Audio interface] Driver start ======= */
int drv_stop(int sub_dev) {
u32_t data;
uint32_t data;
/* INTR_ENABLE_DISABLE */
dev_intr_enable(dev.base, INTR_DISABLE);
@@ -558,19 +558,19 @@ int drv_io_ctl(unsigned long request, void *val, int *len, int sub_dev) {
int status;
switch (request) {
case DSPIORATE:
status = set_sample_rate(*((u32_t *)val), sub_dev);
status = set_sample_rate(*((uint32_t *)val), sub_dev);
break;
case DSPIOSTEREO:
status = set_stereo(*((u32_t *)val), sub_dev);
status = set_stereo(*((uint32_t *)val), sub_dev);
break;
case DSPIOBITS:
status = set_bits(*((u32_t *)val), sub_dev);
status = set_bits(*((uint32_t *)val), sub_dev);
break;
case DSPIOSIZE:
status = set_frag_size(*((u32_t *)val), sub_dev);
status = set_frag_size(*((uint32_t *)val), sub_dev);
break;
case DSPIOSIGN:
status = set_sign(*((u32_t *)val), sub_dev);
status = set_sign(*((uint32_t *)val), sub_dev);
break;
case DSPIOMAX:
status = get_max_frag_size(val, len, sub_dev);
@@ -612,13 +612,13 @@ int drv_get_irq(char *irq) {
}
/* ======= [Audio interface] Get fragment size ======= */
int drv_get_frag_size(u32_t *frag_size, int sub_dev) {
int drv_get_frag_size(uint32_t *frag_size, int sub_dev) {
*frag_size = aud_conf[sub_dev].fragment_size;
return OK;
}
/* ======= [Audio interface] Set DMA channel ======= */
int drv_set_dma(u32_t dma, u32_t length, int chan) {
int drv_set_dma(uint32_t dma, uint32_t length, int chan) {
#ifdef DMA_LENGTH_BY_FRAME
length = length / (aud_conf[chan].nr_of_bits * (aud_conf[chan].stereo + 1) / 8);
#endif
@@ -629,7 +629,7 @@ int drv_set_dma(u32_t dma, u32_t length, int chan) {
/* ======= [Audio interface] Get interrupt summary status ======= */
int drv_int_sum(void) {
u32_t status;
uint32_t status;
/* ### READ_CLEAR_INTR_STS ### */
status = dev_read_clear_intr_status(dev.base);
dev.intr_status = status;
@@ -641,7 +641,7 @@ int drv_int_sum(void) {
/* ======= [Audio interface] Handle interrupt status ======= */
int drv_int(int sub_dev) {
u32_t mask;
uint32_t mask;
/* ### CHECK_INTR_DAC ### */
if (sub_dev == DAC)

24
minix/drivers/audio/cs4281/cs4281.h
View File

@@ -106,19 +106,19 @@
#define CMD_DAC_FCR_INIT 0x01002000
#define CMD_ADC_FCR_INIT 0x0b0a2020
static u32_t dcr_data, dmr_data, fcr_data;
static u32_t g_sample_rate[] = {
static uint32_t dcr_data, dmr_data, fcr_data;
static uint32_t g_sample_rate[] = {
48000, 44100, 22050, 16000, 11025, 8000
};
/* Driver Data Structure */
typedef struct aud_sub_dev_conf_t {
u32_t stereo;
uint32_t stereo;
uint16_t sample_rate;
u32_t nr_of_bits;
u32_t sign;
u32_t busy;
u32_t fragment_size;
uint32_t nr_of_bits;
uint32_t sign;
uint32_t busy;
uint32_t fragment_size;
uint8_t format;
} aud_sub_dev_conf_t;
@@ -126,14 +126,14 @@ typedef struct DEV_STRUCT {
char *name;
uint16_t vid;
uint16_t did;
u32_t devind;
u32_t base[6];
uint32_t devind;
uint32_t base[6];
char irq;
char revision;
u32_t intr_status;
uint32_t intr_status;
} DEV_STRUCT;
void dev_mixer_write(u32_t *base, u32_t reg, u32_t val);
u32_t dev_mixer_read(u32_t *base, u32_t reg);
void dev_mixer_write(uint32_t *base, uint32_t reg, uint32_t val);
uint32_t dev_mixer_read(uint32_t *base, uint32_t reg);
#endif

22
minix/drivers/audio/cs4281/io.h
View File

@@ -6,8 +6,8 @@
#include "cs4281.h"
/* I/O function */
static uint8_t my_inb(u32_t port) {
u32_t value;
static uint8_t my_inb(uint32_t port) {
uint32_t value;
int r;
#ifdef DMA_BASE_IOMAP
value = *(volatile uint8_t *)(port);
@@ -19,8 +19,8 @@ static uint8_t my_inb(u32_t port) {
}
#define sdr_in8(port, offset) (my_inb((port) + (offset)))
static uint16_t my_inw(u32_t port) {
u32_t value;
static uint16_t my_inw(uint32_t port) {
uint32_t value;
int r;
#ifdef DMA_BASE_IOMAP
value = *(volatile uint16_t *)(port);
@@ -32,11 +32,11 @@ static uint16_t my_inw(u32_t port) {
}
#define sdr_in16(port, offset) (my_inw((port) + (offset)))
static u32_t my_inl(u32_t port) {
u32_t value;
static uint32_t my_inl(uint32_t port) {
uint32_t value;
int r;
#ifdef DMA_BASE_IOMAP
value = *(volatile u32_t *)(port);
value = *(volatile uint32_t *)(port);
#else
if ((r = sys_inl(port, &value)) != OK)
printf("SDR: sys_inl failed: %d\n", r);
@@ -45,7 +45,7 @@ static u32_t my_inl(u32_t port) {
}
#define sdr_in32(port, offset) (my_inl((port) + (offset)))
static void my_outb(u32_t port, u32_t value) {
static void my_outb(uint32_t port, uint32_t value) {
int r;
#ifdef DMA_BASE_IOMAP
*(volatile uint8_t *)(port) = value;
@@ -57,7 +57,7 @@ static void my_outb(u32_t port, u32_t value) {
#define sdr_out8(port, offset, value) \
(my_outb(((port) + (offset)), (value)))
static void my_outw(u32_t port, u32_t value) {
static void my_outw(uint32_t port, uint32_t value) {
int r;
#ifdef DMA_BASE_IOMAP
*(volatile uint16_t *)(port) = value;
@@ -69,10 +69,10 @@ static void my_outw(u32_t port, u32_t value) {
#define sdr_out16(port, offset, value) \
(my_outw(((port) + (offset)), (value)))
static void my_outl(u32_t port, u32_t value) {
static void my_outl(uint32_t port, uint32_t value) {
int r;
#ifdef DMA_BASE_IOMAP
*(volatile u32_t *)(port) = value;
*(volatile uint32_t *)(port) = value;
#else
if ((r = sys_outl(port, value)) != OK)
printf("SDR: sys_outl failed: %d\n", r);

8
minix/drivers/audio/cs4281/mixer.c
View File

@@ -7,7 +7,7 @@ uint8_t mixer_value[] = {
0x7e, 0x3d, 0x01, 0x01, 0x00, 0x00, 0x03, 0x00,
0x00, 0x01
};
int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
int get_set_volume(uint32_t *base, struct volume_level *level, int flag) {
int max_level, cmd_left, cmd_right;
max_level = 0x1f;
@@ -76,7 +76,7 @@ int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
#endif
#ifdef MIXER_SB16
int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
int get_set_volume(uint32_t *base, struct volume_level *level, int flag) {
int max_level, shift, cmd_left, cmd_right;
max_level = 0x0f;
@@ -155,7 +155,7 @@ int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
#endif
#ifdef MIXER_AC97
int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
int get_set_volume(uint32_t *base, struct volume_level *level, int flag) {
int max_level, cmd, data;
max_level = 0x1f;
@@ -223,7 +223,7 @@ int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
#endif
/* Set default mixer volume */
void dev_set_default_volume(u32_t *base) {
void dev_set_default_volume(uint32_t *base) {
int i;
#ifdef MIXER_AK4531
for (i = 0; i <= 0x19; i++)

4
minix/drivers/audio/cs4281/mixer.h
View File

@@ -56,7 +56,7 @@
#define AC97_RESET 0x00
#endif
int get_set_volume(u32_t *pbase, struct volume_level *level, int flag);
void dev_set_default_volume(u32_t *pbase);
int get_set_volume(uint32_t *pbase, struct volume_level *level, int flag);
void dev_set_default_volume(uint32_t *pbase);
#endif

68
minix/drivers/audio/es1370/es1370.c
View File

@@ -30,15 +30,15 @@
/* prototypes of private functions */
static int detect_hw(void);
static int disable_int(int sub_dev);
static int set_stereo(u32_t stereo, int sub_dev);
static int set_bits(u32_t nr_of_bits, int sub_dev);
static int set_sample_rate(u32_t rate, int sub_dev);
static int set_sign(u32_t val, int sub_dev);
static int get_max_frag_size(u32_t * val, int *len, int sub_dev);
static int set_frag_size(u32_t fragment_size, int sub_dev);
static int set_stereo(uint32_t stereo, int sub_dev);
static int set_bits(uint32_t nr_of_bits, int sub_dev);
static int set_sample_rate(uint32_t rate, int sub_dev);
static int set_sign(uint32_t val, int sub_dev);
static int get_max_frag_size(uint32_t * val, int *len, int sub_dev);
static int set_frag_size(uint32_t fragment_size, int sub_dev);
static int set_int_cnt(int sub_dev);
static int free_buf(u32_t *val, int *len, int sub_dev);
static int get_samples_in_buf(u32_t *val, int *len, int sub_dev);
static int free_buf(uint32_t *val, int *len, int sub_dev);
static int get_samples_in_buf(uint32_t *val, int *len, int sub_dev);
static int get_set_volume(struct volume_level *level, int *len, int
sub_dev, int flag);
static int reset(int sub_dev);
@@ -168,7 +168,7 @@ int drv_init_hw (void) {
static int detect_hw(void) {
u32_t device;
uint32_t device;
int devind;
uint16_t v_id, d_id;
@@ -224,7 +224,7 @@ int drv_reset() {
int drv_start(int sub_dev, int UNUSED(DmaMode)) {
u32_t enable_bit, result = 0;
uint32_t enable_bit, result = 0;
/* Write default values to device in case user failed to configure.
If user did configure properly, everything is written twice.
@@ -265,7 +265,7 @@ int drv_start(int sub_dev, int UNUSED(DmaMode)) {
int drv_stop(int sub_dev)
{
u32_t enable_bit;
uint32_t enable_bit;
int status;
switch(sub_dev) {
@@ -292,15 +292,15 @@ int drv_io_ctl(unsigned long request, void * val, int * len, int sub_dev) {
switch(request) {
case DSPIORATE:
status = set_sample_rate(*((u32_t *) val), sub_dev); break;
status = set_sample_rate(*((uint32_t *) val), sub_dev); break;
case DSPIOSTEREO:
status = set_stereo(*((u32_t *) val), sub_dev); break;
status = set_stereo(*((uint32_t *) val), sub_dev); break;
case DSPIOBITS:
status = set_bits(*((u32_t *) val), sub_dev); break;
status = set_bits(*((uint32_t *) val), sub_dev); break;
case DSPIOSIZE:
status = set_frag_size(*((u32_t *) val), sub_dev); break;
status = set_frag_size(*((uint32_t *) val), sub_dev); break;
case DSPIOSIGN:
status = set_sign(*((u32_t *) val), sub_dev); break;
status = set_sign(*((uint32_t *) val), sub_dev); break;
case DSPIOMAX:
status = get_max_frag_size(val, len, sub_dev); break;
case DSPIORESET:
@@ -331,16 +331,16 @@ int drv_get_irq(char *irq) {
}
int drv_get_frag_size(u32_t *frag_size, int sub_dev) {
int drv_get_frag_size(uint32_t *frag_size, int sub_dev) {
*frag_size = aud_conf[sub_dev].fragment_size;
return OK;
}
int drv_set_dma(u32_t dma, u32_t length, int chan) {
int drv_set_dma(uint32_t dma, uint32_t length, int chan) {
/* dma length in bytes,
max is 64k long words for es1370 = 256k bytes */
u32_t page, frame_count_reg, dma_add_reg;
uint32_t page, frame_count_reg, dma_add_reg;
switch(chan) {
case ADC1_CHAN: page = ADC_MEM_PAGE;
@@ -368,7 +368,7 @@ int drv_set_dma(u32_t dma, u32_t length, int chan) {
* addressable.
* It expects length -1
*/
pci_outl(reg(frame_count_reg), (u32_t) (length - 1));
pci_outl(reg(frame_count_reg), (uint32_t) (length - 1));
return OK;
}
@@ -381,8 +381,8 @@ int drv_int_sum(void) {
int drv_int(int sub_dev) {
u32_t int_status;
u32_t bit;
uint32_t int_status;
uint32_t bit;
/* return status of interrupt bit of specified channel*/
switch (sub_dev) {
@@ -418,7 +418,7 @@ int drv_reenable_int(int chan) {
int drv_pause(int sub_dev) {
u32_t pause_bit;
uint32_t pause_bit;
disable_int(sub_dev); /* don't send interrupts */
@@ -437,7 +437,7 @@ int drv_pause(int sub_dev) {
int drv_resume(int sub_dev) {
u32_t pause_bit = 0;
uint32_t pause_bit = 0;
drv_reenable_int(sub_dev); /* enable interrupts */
@@ -455,7 +455,7 @@ int drv_resume(int sub_dev) {
}
static int set_bits(u32_t nr_of_bits, int sub_dev) {
static int set_bits(uint32_t nr_of_bits, int sub_dev) {
/* set format bits for specified channel. */
uint16_t size_16_bit, ser_interface;
@@ -479,7 +479,7 @@ static int set_bits(u32_t nr_of_bits, int sub_dev) {
}
static int set_stereo(u32_t stereo, int sub_dev) {
static int set_stereo(uint32_t stereo, int sub_dev) {
/* set format bits for specified channel. */
uint16_t stereo_bit, ser_interface;
@@ -501,12 +501,12 @@ static int set_stereo(u32_t stereo, int sub_dev) {
}
static int set_sign(u32_t UNUSED(val), int UNUSED(sub_dev)) {
static int set_sign(uint32_t UNUSED(val), int UNUSED(sub_dev)) {
return OK;
}
static int set_frag_size(u32_t fragment_size, int sub_dev_nr) {
static int set_frag_size(uint32_t fragment_size, int sub_dev_nr) {
if (fragment_size > (sub_dev[sub_dev_nr].DmaSize /
sub_dev[sub_dev_nr].NrOfDmaFragments) ||
fragment_size < sub_dev[sub_dev_nr].MinFragmentSize) {
@@ -518,9 +518,9 @@ static int set_frag_size(u32_t fragment_size, int sub_dev_nr) {
}
static int set_sample_rate(u32_t rate, int sub_dev) {
static int set_sample_rate(uint32_t rate, int sub_dev) {
/* currently only 44.1kHz */
u32_t controlRegister;
uint32_t controlRegister;
if (rate > MAX_RATE || rate < MIN_RATE) {
return EINVAL;
@@ -573,7 +573,7 @@ static int set_int_cnt(int chan) {
}
static int get_max_frag_size(u32_t * val, int * len, int sub_dev_nr) {
static int get_max_frag_size(uint32_t * val, int * len, int sub_dev_nr) {
*len = sizeof(*val);
*val = (sub_dev[sub_dev_nr].DmaSize /
sub_dev[sub_dev_nr].NrOfDmaFragments);
@@ -597,7 +597,7 @@ static int disable_int(int chan) {
}
static int get_samples_in_buf (u32_t *samples_in_buf, int *len, int chan) {
static int get_samples_in_buf (uint32_t *samples_in_buf, int *len, int chan) {
uint16_t samp_ct_reg;
uint16_t curr_samp_ct_reg;
uint16_t curr_samp_ct; /* counts back from SAMP_CT till 0 */
@@ -621,7 +621,7 @@ static int get_samples_in_buf (u32_t *samples_in_buf, int *len, int chan) {
(void) pci_inw(reg(samp_ct_reg));
curr_samp_ct = pci_inw(reg(curr_samp_ct_reg));
*samples_in_buf = (u32_t) (sub_dev[chan].BufLength * 8192) +
*samples_in_buf = (uint32_t) (sub_dev[chan].BufLength * 8192) +
curr_samp_ct;
return OK;
@@ -629,7 +629,7 @@ static int get_samples_in_buf (u32_t *samples_in_buf, int *len, int chan) {
/* returns 1 if there are free buffers */
static int free_buf (u32_t *val, int *len, int sub_dev_nr) {
static int free_buf (uint32_t *val, int *len, int sub_dev_nr) {
*len = sizeof(*val);
if (sub_dev[sub_dev_nr].BufLength ==
sub_dev[sub_dev_nr].NrOfExtraBuffers) {

14
minix/drivers/audio/es1370/es1370.h
View File

@@ -92,12 +92,12 @@
typedef struct {
u32_t stereo;
uint32_t stereo;
uint16_t sample_rate;
u32_t nr_of_bits;
u32_t sign;
u32_t busy;
u32_t fragment_size;
uint32_t nr_of_bits;
uint32_t sign;
uint32_t busy;
uint32_t fragment_size;
} aud_sub_dev_conf_t;
/* Some defaults for the aud_sub_dev_conf_t*/
@@ -113,9 +113,9 @@ typedef struct DEVSTRUCT {
char* name;
uint16_t v_id; /* vendor id */
uint16_t d_id; /* device id */
u32_t devind; /* minix pci device id, for
uint32_t devind; /* minix pci device id, for
* pci configuration space */
u32_t base; /* changed to 32 bits */
uint32_t base; /* changed to 32 bits */
char irq;
char revision; /* version of the device */
} DEV_STRUCT;

14
minix/drivers/audio/es1370/pci_helper.c
View File

@@ -14,8 +14,8 @@
/*===========================================================================*
* helper functions for I/O *
*===========================================================================*/
u32_t pci_inb(uint16_t port) {
u32_t value;
uint32_t pci_inb(uint16_t port) {
uint32_t value;
int s;
if ((s=sys_inb(port, &value)) !=OK)
printf("%s: warning, sys_inb failed: %d\n", DRIVER_NAME, s);
@@ -23,8 +23,8 @@ u32_t pci_inb(uint16_t port) {
}
u32_t pci_inw(uint16_t port) {
u32_t value;
uint32_t pci_inw(uint16_t port) {
uint32_t value;
int s;
if ((s=sys_inw(port, &value)) !=OK)
printf("%s: warning, sys_inw failed: %d\n", DRIVER_NAME, s);
@@ -32,8 +32,8 @@ u32_t pci_inw(uint16_t port) {
}
u32_t pci_inl(uint16_t port) {
u32_t value;
uint32_t pci_inl(uint16_t port) {
uint32_t value;
int s;
if ((s=sys_inl(port, &value)) !=OK)
printf("%s: warning, sys_inl failed: %d\n", DRIVER_NAME, s);
@@ -55,7 +55,7 @@ void pci_outw(uint16_t port, uint16_t value) {
}
void pci_outl(uint16_t port, u32_t value) {
void pci_outl(uint16_t port, uint32_t value) {
int s;
if ((s=sys_outl(port, value)) !=OK)
printf("%s: warning, sys_outl failed: %d\n", DRIVER_NAME, s);

2
minix/drivers/audio/es1370/pci_helper.h
View File

@@ -7,6 +7,6 @@ unsigned pci_inl(uint16_t port);
void pci_outb(uint16_t port, uint8_t value);
void pci_outw(uint16_t port, uint16_t value);
void pci_outl(uint16_t port, u32_t value);
void pci_outl(uint16_t port, uint32_t value);
#endif

18
minix/drivers/audio/es1371/AC97.c
View File

@@ -51,7 +51,7 @@ static int AC97_set_volume(const struct volume_level *level);
if you change this ! */
#define SRC_UNSYNCED 0xffffffffUL
static u32_t SrcSyncState = 0x00010000UL;
static uint32_t SrcSyncState = 0x00010000UL;
static DEV_STRUCT *dev;
@@ -61,7 +61,7 @@ static void set_src_sync_state (int state)
if (state < 0)
SrcSyncState = SRC_UNSYNCED;
else {
SrcSyncState = (u32_t)state << 16;
SrcSyncState = (uint32_t)state << 16;
SrcSyncState &= 0x00070000Ul;
}
}
@@ -70,7 +70,7 @@ static void set_src_sync_state (int state)
static int AC97_write (const DEV_STRUCT * pCC, uint16_t wAddr, uint16_t wData)
{
u32_t dtemp, i;
uint32_t dtemp, i;
uint16_t wBaseAddr = pCC->base;
/* wait for WIP bit (Write In Progress) to go away */
@@ -106,7 +106,7 @@ uint16_t wBaseAddr = pCC->base;
/* A test for 5880 - prime the PCI data bus */
{
u32_t dat = ((u32_t) wAddr << 16) | wData;
uint32_t dat = ((uint32_t) wAddr << 16) | wData;
char page = pci_inb(wBaseAddr + MEM_PAGE);
pci_outl (wBaseAddr + MEM_PAGE, dat);
@@ -135,7 +135,7 @@ uint16_t wBaseAddr = pCC->base;
#if 0
static int AC97_read (const DEV_STRUCT * pCC, uint16_t wAddr, uint16_t *data)
{
u32_t dtemp, i;
uint32_t dtemp, i;
uint16_t base = pCC->base;
/* wait for WIP to go away */
@@ -169,7 +169,7 @@ uint16_t base = pCC->base;
/* A test for 5880 - prime the PCI data bus */
{
/* set bit 23, this means read in stead of write. */
u32_t dat = ((u32_t) wAddr << 16) | (1UL << 23);
uint32_t dat = ((uint32_t) wAddr << 16) | (1UL << 23);
char page = pci_inb(base + MEM_PAGE);
/* todo: why are we putting data in the mem page register??? */
@@ -215,7 +215,7 @@ static int AC97_write_unsynced (const DEV_STRUCT * pCC, uint16_t wAddr,
return (AC97_ERR_WIP_TIMEOUT);
/* write addr and data */
pci_outl(pCC->base + CODEC_READ, ((u32_t) wAddr << 16) | wData);
pci_outl(pCC->base + CODEC_READ, ((uint32_t) wAddr << 16) | wData);
return 0;
}
@@ -223,14 +223,14 @@ static int AC97_write_unsynced (const DEV_STRUCT * pCC, uint16_t wAddr,
static int AC97_read_unsynced (const DEV_STRUCT * pCC, uint16_t wAddr,
uint16_t *data)
{
u32_t dtemp;
uint32_t dtemp;
/* wait for WIP to go away */
if (WaitBitd (pCC->base + CODEC_READ, 30, 0, WIP_TIMEOUT))
return (AC97_ERR_WIP_TIMEOUT);
/* write addr w/data=0 and assert read request */
pci_outl(pCC->base + CODEC_READ, ((u32_t) wAddr << 16) | (1UL << 23));
pci_outl(pCC->base + CODEC_READ, ((uint32_t) wAddr << 16) | (1UL << 23));
/* now wait for the stinkin' data (RDY) */
if (WaitBitd (pCC->base + CODEC_READ, 31, 1, DRDY_TIMEOUT))

14
minix/drivers/audio/es1371/SRC.c
View File

@@ -6,7 +6,7 @@
int SRCInit ( DEV_STRUCT * DSP )
{
u32_t i;
uint32_t i;
int retVal;
/* Clear all SRC RAM then init - keep SRC disabled until done */
@@ -57,7 +57,7 @@ int SRCInit ( DEV_STRUCT * DSP )
int SRCRegRead(DEV_STRUCT * DSP, uint16_t reg, uint16_t *data)
{
u32_t dtemp;
uint32_t dtemp;
/* wait for ready */
if (WaitBitd (reg(CONC_dSRCIO_OFF), SRC_BUSY_BIT, 0, 1000))
@@ -67,7 +67,7 @@ int SRCRegRead(DEV_STRUCT * DSP, uint16_t reg, uint16_t *data)
/* assert a read request */
pci_outl(reg(CONC_dSRCIO_OFF),
(dtemp & SRC_CTLMASK) | ((u32_t) reg << 25));
(dtemp & SRC_CTLMASK) | ((uint32_t) reg << 25));
/* now wait for the data */
if (WaitBitd (reg(CONC_dSRCIO_OFF), SRC_BUSY_BIT, 0, 1000))
@@ -82,7 +82,7 @@ int SRCRegRead(DEV_STRUCT * DSP, uint16_t reg, uint16_t *data)
int SRCRegWrite(DEV_STRUCT * DSP, uint16_t reg, uint16_t val)
{
u32_t dtemp;
uint32_t dtemp;
/* wait for ready */
@@ -93,7 +93,7 @@ int SRCRegWrite(DEV_STRUCT * DSP, uint16_t reg, uint16_t val)
/* assert the write request */
pci_outl(reg(CONC_dSRCIO_OFF),
(dtemp & SRC_CTLMASK) | SRC_WENABLE | ((u32_t) reg << 25) | val);
(dtemp & SRC_CTLMASK) | SRC_WENABLE | ((uint32_t) reg << 25) | val);
return 0;
}
@@ -101,7 +101,7 @@ int SRCRegWrite(DEV_STRUCT * DSP, uint16_t reg, uint16_t val)
void SRCSetRate(DEV_STRUCT * DSP, char base, uint16_t rate)
{
u32_t freq, dtemp, i;
uint32_t freq, dtemp, i;
uint16_t N, truncM, truncStart, wtemp;
@@ -118,7 +118,7 @@ void SRCSetRate(DEV_STRUCT * DSP, char base, uint16_t rate)
/* calculate new frequency and write it - preserve accum */
/* please don't try to understand. */
freq = ((u32_t) rate << 16) / 3000U;
freq = ((uint32_t) rate << 16) / 3000U;
SRCRegRead(DSP, base + SRC_INT_REGS_OFF, &wtemp);
SRCRegWrite(DSP, base + SRC_INT_REGS_OFF,

18
minix/drivers/audio/es1371/codec.c
View File

@@ -12,7 +12,7 @@
if you change this ! */
#define SRC_UNSYNCED 0xffffffffUL
static u32_t SrcSyncState = 0x00010000UL;
static uint32_t SrcSyncState = 0x00010000UL;
void CodecSetSrcSyncState (int state)
@@ -20,7 +20,7 @@ void CodecSetSrcSyncState (int state)
if (state < 0)
SrcSyncState = SRC_UNSYNCED;
else {
SrcSyncState = (u32_t)state << 16;
SrcSyncState = (uint32_t)state << 16;
SrcSyncState &= 0x00070000Ul;
}
}
@@ -28,7 +28,7 @@ void CodecSetSrcSyncState (int state)
int CodecWrite (DEV_STRUCT * pCC, uint16_t wAddr, uint16_t wData)
{
u32_t dtemp, i;
uint32_t dtemp, i;
uint16_t wBaseAddr = pCC->base;
/* wait for WIP bit (Write In Progress) to go away */
@@ -64,7 +64,7 @@ uint16_t wBaseAddr = pCC->base;
/* A test for 5880 - prime the PCI data bus */
{
u32_t dat = ((u32_t) wAddr << 16) | wData;
uint32_t dat = ((uint32_t) wAddr << 16) | wData;
char page = pci_inb(wBaseAddr + CONC_bMEMPAGE_OFF);
pci_outl (wBaseAddr + CONC_bMEMPAGE_OFF, dat);
@@ -91,7 +91,7 @@ uint16_t wBaseAddr = pCC->base;
int CodecRead (DEV_STRUCT * pCC, uint16_t wAddr, uint16_t *data)
{
u32_t dtemp, i;
uint32_t dtemp, i;
uint16_t base = pCC->base;
/* wait for WIP to go away */
@@ -125,7 +125,7 @@ uint16_t base = pCC->base;
/* A test for 5880 - prime the PCI data bus */
{
/* set bit 23, this means read in stead of write. */
u32_t dat = ((u32_t) wAddr << 16) | (1UL << 23);
uint32_t dat = ((uint32_t) wAddr << 16) | (1UL << 23);
char page = pci_inb(base + CONC_bMEMPAGE_OFF);
/* todo: why are we putting data in the mem page register??? */
@@ -169,21 +169,21 @@ int CodecWriteUnsynced (DEV_STRUCT * pCC, uint16_t wAddr, uint16_t wData)
return (CODEC_ERR_WIP_TIMEOUT);
/* write addr and data */
pci_outl(pCC->base + CONC_dCODECCTL_OFF, ((u32_t) wAddr << 16) | wData);
pci_outl(pCC->base + CONC_dCODECCTL_OFF, ((uint32_t) wAddr << 16) | wData);
return 0;
}
int CodecReadUnsynced (DEV_STRUCT * pCC, uint16_t wAddr, uint16_t *data)
{
u32_t dtemp;
uint32_t dtemp;
/* wait for WIP to go away */
if (WaitBitd (pCC->base + CONC_dCODECCTL_OFF, 30, 0, WIP_TIMEOUT))
return (CODEC_ERR_WIP_TIMEOUT);
/* write addr w/data=0 and assert read request */
pci_outl(pCC->base + CONC_dCODECCTL_OFF, ((u32_t) wAddr << 16) | (1UL << 23));
pci_outl(pCC->base + CONC_dCODECCTL_OFF, ((uint32_t) wAddr << 16) | (1UL << 23));
/* now wait for the stinkin' data (RDY) */
if (WaitBitd (pCC->base + CONC_dCODECCTL_OFF, 31, 1, DRDY_TIMEOUT))

68
minix/drivers/audio/es1371/es1371.c
View File

@@ -36,15 +36,15 @@
/* prototypes of private functions */
static int detect_hw(void);
static int disable_int(int sub_dev);
static int set_stereo(u32_t stereo, int sub_dev);
static int set_bits(u32_t nr_of_bits, int sub_dev);
static int set_sample_rate(u32_t rate, int sub_dev);
static int set_sign(u32_t val, int sub_dev);
static int get_max_frag_size(u32_t * val, int *len, int sub_dev);
static int set_frag_size(u32_t fragment_size, int sub_dev);
static int set_stereo(uint32_t stereo, int sub_dev);
static int set_bits(uint32_t nr_of_bits, int sub_dev);
static int set_sample_rate(uint32_t rate, int sub_dev);
static int set_sign(uint32_t val, int sub_dev);
static int get_max_frag_size(uint32_t * val, int *len, int sub_dev);
static int set_frag_size(uint32_t fragment_size, int sub_dev);
static int set_int_cnt(int sub_dev);
static int free_buf(u32_t *val, int *len, int sub_dev);
static int get_samples_in_buf(u32_t *val, int *len, int sub_dev);
static int free_buf(uint32_t *val, int *len, int sub_dev);
static int get_samples_in_buf(uint32_t *val, int *len, int sub_dev);
static int get_set_volume(struct volume_level *level, int *len, int
sub_dev, int flag);
static int reset(int sub_dev);
@@ -170,7 +170,7 @@ int drv_init_hw (void) {
static int detect_hw(void) {
u32_t device;
uint32_t device;
int devind;
uint16_t v_id, d_id;
@@ -226,7 +226,7 @@ int drv_reset() {
int drv_start(int sub_dev, int UNUSED(DmaMode)) {
u32_t enable_bit, result = 0;
uint32_t enable_bit, result = 0;
/* Write default values to device in case user failed to configure.
If user did configure properly, everything is written twice.
@@ -267,7 +267,7 @@ int drv_start(int sub_dev, int UNUSED(DmaMode)) {
int drv_stop(int sub_dev)
{
u32_t enable_bit;
uint32_t enable_bit;
switch(sub_dev) {
case ADC1_CHAN: enable_bit = ADC1_EN;break;
@@ -293,15 +293,15 @@ int drv_io_ctl(unsigned long request, void * val, int * len, int sub_dev) {
switch(request) {
case DSPIORATE:
status = set_sample_rate(*((u32_t *) val), sub_dev); break;
status = set_sample_rate(*((uint32_t *) val), sub_dev); break;
case DSPIOSTEREO:
status = set_stereo(*((u32_t *) val), sub_dev); break;
status = set_stereo(*((uint32_t *) val), sub_dev); break;
case DSPIOBITS:
status = set_bits(*((u32_t *) val), sub_dev); break;
status = set_bits(*((uint32_t *) val), sub_dev); break;
case DSPIOSIZE:
status = set_frag_size(*((u32_t *) val), sub_dev); break;
status = set_frag_size(*((uint32_t *) val), sub_dev); break;
case DSPIOSIGN:
status = set_sign(*((u32_t *) val), sub_dev); break;
status = set_sign(*((uint32_t *) val), sub_dev); break;
case DSPIOMAX:
status = get_max_frag_size(val, len, sub_dev); break;
case DSPIORESET:
@@ -332,16 +332,16 @@ int drv_get_irq(char *irq) {
}
int drv_get_frag_size(u32_t *frag_size, int sub_dev) {
int drv_get_frag_size(uint32_t *frag_size, int sub_dev) {
*frag_size = aud_conf[sub_dev].fragment_size;
return OK;
}
int drv_set_dma(u32_t dma, u32_t length, int chan) {
int drv_set_dma(uint32_t dma, uint32_t length, int chan) {
/* dma length in bytes,
max is 64k long words for es1371 = 256k bytes */
u32_t page, frame_count_reg, dma_add_reg;
uint32_t page, frame_count_reg, dma_add_reg;
switch(chan) {
case ADC1_CHAN: page = ADC_MEM_PAGE;
@@ -369,7 +369,7 @@ int drv_set_dma(u32_t dma, u32_t length, int chan) {
* addressable.
* It expects length -1
*/
pci_outl(reg(frame_count_reg), (u32_t) (length - 1));
pci_outl(reg(frame_count_reg), (uint32_t) (length - 1));
return OK;
}
@@ -382,8 +382,8 @@ int drv_int_sum(void) {
int drv_int(int sub_dev) {
u32_t int_status;
u32_t bit;
uint32_t int_status;
uint32_t bit;
/* return status of interrupt bit of specified channel*/
switch (sub_dev) {
@@ -419,7 +419,7 @@ int drv_reenable_int(int chan) {
int drv_pause(int sub_dev) {
u32_t pause_bit;
uint32_t pause_bit;
disable_int(sub_dev); /* don't send interrupts */
@@ -438,7 +438,7 @@ int drv_pause(int sub_dev) {
int drv_resume(int sub_dev) {
u32_t pause_bit = 0;
uint32_t pause_bit = 0;
drv_reenable_int(sub_dev); /* enable interrupts */
@@ -456,7 +456,7 @@ int drv_resume(int sub_dev) {
}
static int set_bits(u32_t nr_of_bits, int sub_dev) {
static int set_bits(uint32_t nr_of_bits, int sub_dev) {
/* set format bits for specified channel. */
uint16_t size_16_bit, ser_interface;
@@ -480,7 +480,7 @@ static int set_bits(u32_t nr_of_bits, int sub_dev) {
}
static int set_stereo(u32_t stereo, int sub_dev) {
static int set_stereo(uint32_t stereo, int sub_dev) {
/* set format bits for specified channel. */
uint16_t stereo_bit, ser_interface;
@@ -502,12 +502,12 @@ static int set_stereo(u32_t stereo, int sub_dev) {
}
static int set_sign(u32_t UNUSED(val), int UNUSED(sub_dev)) {
static int set_sign(uint32_t UNUSED(val), int UNUSED(sub_dev)) {
return OK;
}
static int set_frag_size(u32_t fragment_size, int sub_dev_nr) {
static int set_frag_size(uint32_t fragment_size, int sub_dev_nr) {
if (fragment_size > (sub_dev[sub_dev_nr].DmaSize /
sub_dev[sub_dev_nr].NrOfDmaFragments) ||
fragment_size < sub_dev[sub_dev_nr].MinFragmentSize) {
@@ -519,8 +519,8 @@ static int set_frag_size(u32_t fragment_size, int sub_dev_nr) {
}
static int set_sample_rate(u32_t rate, int sub_dev) {
u32_t src_base_reg;
static int set_sample_rate(uint32_t rate, int sub_dev) {
uint32_t src_base_reg;
if (rate > MAX_RATE || rate < MIN_RATE) {
return EINVAL;
@@ -575,7 +575,7 @@ static int set_int_cnt(int chan) {
}
static int get_max_frag_size(u32_t * val, int * len, int sub_dev_nr) {
static int get_max_frag_size(uint32_t * val, int * len, int sub_dev_nr) {
*len = sizeof(*val);
*val = (sub_dev[sub_dev_nr].DmaSize /
sub_dev[sub_dev_nr].NrOfDmaFragments);
@@ -599,7 +599,7 @@ static int disable_int(int chan) {
}
static int get_samples_in_buf (u32_t *samples_in_buf, int *len, int chan) {
static int get_samples_in_buf (uint32_t *samples_in_buf, int *len, int chan) {
uint16_t samp_ct_reg;
uint16_t curr_samp_ct_reg;
uint16_t curr_samp_ct; /* counts back from SAMP_CT till 0 */
@@ -623,7 +623,7 @@ static int get_samples_in_buf (u32_t *samples_in_buf, int *len, int chan) {
(void) pci_inw(reg(samp_ct_reg));
curr_samp_ct = pci_inw(reg(curr_samp_ct_reg));
*samples_in_buf = (u32_t) (sub_dev[chan].BufLength * 8192) +
*samples_in_buf = (uint32_t) (sub_dev[chan].BufLength * 8192) +
curr_samp_ct;
return OK;
@@ -631,7 +631,7 @@ static int get_samples_in_buf (u32_t *samples_in_buf, int *len, int chan) {
/* returns 1 if there are free buffers */
static int free_buf (u32_t *val, int *len, int sub_dev_nr) {
static int free_buf (uint32_t *val, int *len, int sub_dev_nr) {
*len = sizeof(*val);
if (sub_dev[sub_dev_nr].BufLength ==
sub_dev[sub_dev_nr].NrOfExtraBuffers) {

14
minix/drivers/audio/es1371/es1371.h
View File

@@ -94,12 +94,12 @@
typedef struct {
u32_t stereo;
uint32_t stereo;
uint16_t sample_rate;
u32_t nr_of_bits;
u32_t sign;
u32_t busy;
u32_t fragment_size;
uint32_t nr_of_bits;
uint32_t sign;
uint32_t busy;
uint32_t fragment_size;
} aud_sub_dev_conf_t;
/* Some defaults for the aud_sub_dev_conf_t*/
@@ -115,9 +115,9 @@ typedef struct DEVSTRUCT {
char* name;
uint16_t v_id; /* vendor id */
uint16_t d_id; /* device id */
u32_t devind; /* minix pci device id, for
uint32_t devind; /* minix pci device id, for
* pci configuration space */
u32_t base; /* changed to 32 bits */
uint32_t base; /* changed to 32 bits */
char irq;
char revision; /* version of the device */
} DEV_STRUCT;

14
minix/drivers/audio/es1371/pci_helper.c
View File

@@ -14,8 +14,8 @@
/*===========================================================================*
* helper functions for I/O *
*===========================================================================*/
u32_t pci_inb(uint16_t port) {
u32_t value;
uint32_t pci_inb(uint16_t port) {
uint32_t value;
int s;
if ((s=sys_inb(port, &value)) !=OK)
printf("%s: warning, sys_inb failed: %d\n", DRIVER_NAME, s);
@@ -23,8 +23,8 @@ u32_t pci_inb(uint16_t port) {
}
u32_t pci_inw(uint16_t port) {
u32_t value;
uint32_t pci_inw(uint16_t port) {
uint32_t value;
int s;
if ((s=sys_inw(port, &value)) !=OK)
printf("%s: warning, sys_inw failed: %d\n", DRIVER_NAME, s);
@@ -32,8 +32,8 @@ u32_t pci_inw(uint16_t port) {
}
u32_t pci_inl(uint16_t port) {
u32_t value;
uint32_t pci_inl(uint16_t port) {
uint32_t value;
int s;
if ((s=sys_inl(port, &value)) !=OK)
printf("%s: warning, sys_inl failed: %d\n", DRIVER_NAME, s);
@@ -55,7 +55,7 @@ void pci_outw(uint16_t port, uint16_t value) {
}
void pci_outl(uint16_t port, u32_t value) {
void pci_outl(uint16_t port, uint32_t value) {
int s;
if ((s=sys_outl(port, value)) !=OK)
printf("%s: warning, sys_outl failed: %d\n", DRIVER_NAME, s);

2
minix/drivers/audio/es1371/pci_helper.h
View File

@@ -7,6 +7,6 @@ unsigned pci_inl(uint16_t port);
void pci_outb(uint16_t port, uint8_t value);
void pci_outw(uint16_t port, uint16_t value);
void pci_outl(uint16_t port, u32_t value);
void pci_outl(uint16_t port, uint32_t value);
#endif

16
minix/drivers/audio/es1371/sample_rate_converter.c
View File

@@ -40,7 +40,7 @@ static int src_reg_write(const DEV_STRUCT * DSP, uint16_t reg, uint16_t val);
int src_init ( DEV_STRUCT * DSP ) {
u32_t i;
uint32_t i;
int retVal;
/* Clear all SRC RAM then init - keep SRC disabled until done */
@@ -104,7 +104,7 @@ int src_init ( DEV_STRUCT * DSP ) {
static int src_reg_read(const DEV_STRUCT * DSP, uint16_t reg, uint16_t *data) {
u32_t dtemp;
uint32_t dtemp;
/* wait for ready */
if (WaitBitd (reg(SAMPLE_RATE_CONV), SRC_BUSY_BIT, 0, 1000))
@@ -114,9 +114,9 @@ static int src_reg_read(const DEV_STRUCT * DSP, uint16_t reg, uint16_t *data) {
/* assert a read request */
/*pci_outl(reg(SAMPLE_RATE_CONV),
(dtemp & SRC_CTLMASK) | ((u32_t) reg << 25));*/
(dtemp & SRC_CTLMASK) | ((uint32_t) reg << 25));*/
pci_outl(reg(SAMPLE_RATE_CONV), (dtemp &
(DIS_REC|DIS_P2|DIS_P1|SRC_DISABLE)) | ((u32_t) reg << 25));
(DIS_REC|DIS_P2|DIS_P1|SRC_DISABLE)) | ((uint32_t) reg << 25));
/* now wait for the data */
if (WaitBitd (reg(SAMPLE_RATE_CONV), SRC_BUSY_BIT, 0, 1000))
@@ -130,7 +130,7 @@ static int src_reg_read(const DEV_STRUCT * DSP, uint16_t reg, uint16_t *data) {
static int src_reg_write(const DEV_STRUCT * DSP, uint16_t reg, uint16_t val) {
u32_t dtemp;
uint32_t dtemp;
/* wait for ready */
if (WaitBitd (reg(SAMPLE_RATE_CONV), SRC_BUSY_BIT, 0, 1000))
@@ -140,14 +140,14 @@ static int src_reg_write(const DEV_STRUCT * DSP, uint16_t reg, uint16_t val) {
/* assert the write request */
pci_outl(reg(SAMPLE_RATE_CONV),
(dtemp & SRC_CTLMASK) | SRC_RAM_WE | ((u32_t) reg << 25) | val);
(dtemp & SRC_CTLMASK) | SRC_RAM_WE | ((uint32_t) reg << 25) | val);
return 0;
}
void src_set_rate(const DEV_STRUCT * DSP, char base, uint16_t rate) {
u32_t freq, dtemp, i;
uint32_t freq, dtemp, i;
uint16_t N, truncM, truncStart, wtemp;
@@ -164,7 +164,7 @@ void src_set_rate(const DEV_STRUCT * DSP, char base, uint16_t rate) {
/* calculate new frequency and write it - preserve accum */
/* please don't try to understand. */
freq = ((u32_t) rate << 16) / 3000U;
freq = ((uint32_t) rate << 16) / 3000U;
src_reg_read(DSP, base + SRC_INT_REGS_OFF, &wtemp);
src_reg_write(DSP, base + SRC_INT_REGS_OFF,

20
minix/drivers/audio/sb16/sb16.c
View File

@@ -19,7 +19,7 @@ static int dsp_set_speed(unsigned int speed);
static int dsp_set_stereo(unsigned int stereo);
static int dsp_set_bits(unsigned int bits);
static int dsp_set_sign(unsigned int sign);
static int dsp_get_max_frag_size(u32_t *val, int *len);
static int dsp_get_max_frag_size(uint32_t *val, int *len);
static unsigned int DspStereo = DEFAULT_STEREO;
@@ -190,7 +190,7 @@ int drv_stop(int sub_dev) {
int drv_set_dma(u32_t dma, u32_t UNUSED(length), int UNUSED(chan)) {
int drv_set_dma(uint32_t dma, uint32_t UNUSED(length), int UNUSED(chan)) {
Dprint(("drv_set_dma():\n"));
DmaPhys = dma;
return OK;
@@ -255,7 +255,7 @@ int drv_get_irq(char *irq) {
int drv_get_frag_size(u32_t *frag_size, int UNUSED(sub_dev)) {
int drv_get_frag_size(uint32_t *frag_size, int UNUSED(sub_dev)) {
Dprint(("drv_get_frag_size():\n"));
*frag_size = DspFragmentSize;
return OK;
@@ -267,11 +267,11 @@ static int dsp_ioctl(unsigned long request, void *val, int *len) {
int status;
switch(request) {
case DSPIORATE: status = dsp_set_speed(*((u32_t*) val)); break;
case DSPIOSTEREO: status = dsp_set_stereo(*((u32_t*) val)); break;
case DSPIOBITS: status = dsp_set_bits(*((u32_t*) val)); break;
case DSPIOSIZE: status = dsp_set_size(*((u32_t*) val)); break;
case DSPIOSIGN: status = dsp_set_sign(*((u32_t*) val)); break;
case DSPIORATE: status = dsp_set_speed(*((uint32_t*) val)); break;
case DSPIOSTEREO: status = dsp_set_stereo(*((uint32_t*) val)); break;
case DSPIOBITS: status = dsp_set_bits(*((uint32_t*) val)); break;
case DSPIOSIZE: status = dsp_set_size(*((uint32_t*) val)); break;
case DSPIOSIGN: status = dsp_set_sign(*((uint32_t*) val)); break;
case DSPIOMAX: status = dsp_get_max_frag_size(val, len); break;
case DSPIORESET: status = drv_reset(); break;
default: status = ENOTTY; break;
@@ -405,7 +405,7 @@ static int dsp_set_sign(unsigned int sign) {
static int dsp_get_max_frag_size(u32_t *val, int *len) {
static int dsp_get_max_frag_size(uint32_t *val, int *len) {
*len = sizeof(*val);
*val = sub_dev[AUDIO].DmaSize / sub_dev[AUDIO].NrOfDmaFragments;
return OK;
@@ -431,7 +431,7 @@ int dsp_command(int value) {
int sb16_inb(int port) {
int s;
u32_t value;
uint32_t value;
if ((s=sys_inb(port, &value)) != OK)
panic("sys_inb() failed: %d", s);

22
minix/drivers/audio/trident/io.h
View File

@@ -6,8 +6,8 @@
#include "trident.h"
/* I/O function */
static uint8_t my_inb(u32_t port) {
u32_t value;
static uint8_t my_inb(uint32_t port) {
uint32_t value;
int r;
#ifdef DMA_BASE_IOMAP
value = *(volatile uint8_t *)(port);
@@ -19,8 +19,8 @@ static uint8_t my_inb(u32_t port) {
}
#define sdr_in8(port, offset) (my_inb((port) + (offset)))
static uint16_t my_inw(u32_t port) {
u32_t value;
static uint16_t my_inw(uint32_t port) {
uint32_t value;
int r;
#ifdef DMA_BASE_IOMAP
value = *(volatile uint16_t *)(port);
@@ -32,11 +32,11 @@ static uint16_t my_inw(u32_t port) {
}
#define sdr_in16(port, offset) (my_inw((port) + (offset)))
static u32_t my_inl(u32_t port) {
u32_t value;
static uint32_t my_inl(uint32_t port) {
uint32_t value;
int r;
#ifdef DMA_BASE_IOMAP
value = *(volatile u32_t *)(port);
value = *(volatile uint32_t *)(port);
#else
if ((r = sys_inl(port, &value)) != OK)
printf("SDR: sys_inl failed: %d\n", r);
@@ -45,7 +45,7 @@ static u32_t my_inl(u32_t port) {
}
#define sdr_in32(port, offset) (my_inl((port) + (offset)))
static void my_outb(u32_t port, u32_t value) {
static void my_outb(uint32_t port, uint32_t value) {
int r;
#ifdef DMA_BASE_IOMAP
*(volatile uint8_t *)(port) = value;
@@ -57,7 +57,7 @@ static void my_outb(u32_t port, u32_t value) {
#define sdr_out8(port, offset, value) \
(my_outb(((port) + (offset)), (value)))
static void my_outw(u32_t port, u32_t value) {
static void my_outw(uint32_t port, uint32_t value) {
int r;
#ifdef DMA_BASE_IOMAP
*(volatile uint16_t *)(port) = value;
@@ -69,10 +69,10 @@ static void my_outw(u32_t port, u32_t value) {
#define sdr_out16(port, offset, value) \
(my_outw(((port) + (offset)), (value)))
static void my_outl(u32_t port, u32_t value) {
static void my_outl(uint32_t port, uint32_t value) {
int r;
#ifdef DMA_BASE_IOMAP
*(volatile u32_t *)(port) = value;
*(volatile uint32_t *)(port) = value;
#else
if ((r = sys_outl(port, value)) != OK)
printf("SDR: sys_outl failed: %d\n", r);

8
minix/drivers/audio/trident/mixer.c
View File

@@ -7,7 +7,7 @@ uint8_t mixer_value[] = {
0x7e, 0x3d, 0x01, 0x01, 0x00, 0x00, 0x03, 0x00,
0x00, 0x01
};
int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
int get_set_volume(uint32_t *base, struct volume_level *level, int flag) {
int max_level, cmd_left, cmd_right;
max_level = 0x1f;
@@ -76,7 +76,7 @@ int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
#endif
#ifdef MIXER_SB16
int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
int get_set_volume(uint32_t *base, struct volume_level *level, int flag) {
int max_level, shift, cmd_left, cmd_right;
max_level = 0x0f;
@@ -155,7 +155,7 @@ int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
#endif
#ifdef MIXER_AC97
int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
int get_set_volume(uint32_t *base, struct volume_level *level, int flag) {
int max_level, cmd, data;
max_level = 0x1f;
@@ -223,7 +223,7 @@ int get_set_volume(u32_t *base, struct volume_level *level, int flag) {
#endif
/* Set default mixer volume */
void dev_set_default_volume(u32_t *base) {
void dev_set_default_volume(uint32_t *base) {
int i;
#ifdef MIXER_AK4531
for (i = 0; i <= 0x19; i++)

4
minix/drivers/audio/trident/mixer.h
View File

@@ -56,7 +56,7 @@
#define AC97_RESET 0x00
#endif
int get_set_volume(u32_t *pbase, struct volume_level *level, int flag);
void dev_set_default_volume(u32_t *pbase);
int get_set_volume(uint32_t *pbase, struct volume_level *level, int flag);
void dev_set_default_volume(uint32_t *pbase);
#endif

152
minix/drivers/audio/trident/trident.c
View File

@@ -10,35 +10,35 @@ drv_t drv;
/* internal function */
static int dev_probe(void);
static int set_sample_rate(u32_t rate, int num);
static int set_stereo(u32_t stereo, int num);
static int set_bits(u32_t bits, int sub_dev);
static int set_frag_size(u32_t frag_size, int num);
static int set_sign(u32_t val, int num);
static int get_frag_size(u32_t *val, int *len, int num);
static int free_buf(u32_t *val, int *len, int num);
static int set_sample_rate(uint32_t rate, int num);
static int set_stereo(uint32_t stereo, int num);
static int set_bits(uint32_t bits, int sub_dev);
static int set_frag_size(uint32_t frag_size, int num);
static int set_sign(uint32_t val, int num);
static int get_frag_size(uint32_t *val, int *len, int num);
static int free_buf(uint32_t *val, int *len, int num);
/* developer interface */
static int dev_reset(u32_t *base);
static void dev_configure(u32_t *base);
static void dev_init_mixer(u32_t *base);
static void dev_set_sample_rate(u32_t *base, uint16_t sample_rate);
static void dev_set_format(u32_t *base, u32_t bits, u32_t sign,
u32_t stereo, u32_t sample_count);
static void dev_start_channel(u32_t *base, int sub_dev);
static void dev_stop_channel(u32_t *base, int sub_dev);
static void dev_set_dma(u32_t *base, u32_t dma, u32_t len, int sub_dev);
static u32_t dev_read_dma_current(u32_t *base, int sub_dev);
static void dev_pause_dma(u32_t *base, int sub_dev);
static void dev_resume_dma(u32_t *base, int sub_dev);
static void dev_intr_other(u32_t *base, u32_t status);
static u32_t dev_read_clear_intr_status(u32_t *base);
static void dev_intr_enable(u32_t *base, int flag);
static int dev_reset(uint32_t *base);
static void dev_configure(uint32_t *base);
static void dev_init_mixer(uint32_t *base);
static void dev_set_sample_rate(uint32_t *base, uint16_t sample_rate);
static void dev_set_format(uint32_t *base, uint32_t bits, uint32_t sign,
uint32_t stereo, uint32_t sample_count);
static void dev_start_channel(uint32_t *base, int sub_dev);
static void dev_stop_channel(uint32_t *base, int sub_dev);
static void dev_set_dma(uint32_t *base, uint32_t dma, uint32_t len, int sub_dev);
static uint32_t dev_read_dma_current(uint32_t *base, int sub_dev);
static void dev_pause_dma(uint32_t *base, int sub_dev);
static void dev_resume_dma(uint32_t *base, int sub_dev);
static void dev_intr_other(uint32_t *base, uint32_t status);
static uint32_t dev_read_clear_intr_status(uint32_t *base);
static void dev_intr_enable(uint32_t *base, int flag);
/* ======= Developer implemented function ======= */
/* ====== Self-defined function ====== */
static void dev_write_chan_reg(u32_t base) {
u32_t reg[5], i, data;
static void dev_write_chan_reg(uint32_t base) {
uint32_t reg[5], i, data;
reg[0] = (my_chan.cso << 16) | (my_chan.alpha << 4) | my_chan.fms;
reg[1] = my_chan.dma;
reg[2] = (my_chan.eso << 16) | my_chan.delta;
@@ -51,8 +51,8 @@ static void dev_write_chan_reg(u32_t base) {
/* ====== Mixer handling interface ======*/
/* Write the data to mixer register (### WRITE_MIXER_REG ###) */
void dev_mixer_write(u32_t *base, u32_t reg, u32_t val) {
u32_t i, data, base0 = base[0];
void dev_mixer_write(uint32_t *base, uint32_t reg, uint32_t val) {
uint32_t i, data, base0 = base[0];
for (i = 0; i < 50000; i++) {
data = sdr_in16(base0, REG_CODEC_WRITE);
if (!(data & STS_CODEC_BUSY))
@@ -65,8 +65,8 @@ void dev_mixer_write(u32_t *base, u32_t reg, u32_t val) {
}
/* Read the data from mixer register (### READ_MIXER_REG ###) */
u32_t dev_mixer_read(u32_t *base, u32_t reg) {
u32_t i, data, base0 = base[0];
uint32_t dev_mixer_read(uint32_t *base, uint32_t reg) {
uint32_t i, data, base0 = base[0];
data = (reg & 0x00ff) | STS_CODEC_BUSY;
sdr_out32(base0, REG_CODEC_READ, data);
for (i = 0; i < 50000; i++) {
@@ -83,34 +83,34 @@ u32_t dev_mixer_read(u32_t *base, u32_t reg) {
/* Reset the device (### RESET_HARDWARE_CAN_FAIL ###)
* -- Return OK means success, Others means failure */
static int dev_reset(u32_t *base) {
u32_t base0 = base[0];
static int dev_reset(uint32_t *base) {
uint32_t base0 = base[0];
sdr_out32(base0, REG_CODEC_CTRL, 0x000a);
return OK;
}
/* Configure hardware registers (### CONF_HARDWARE ###) */
static void dev_configure(u32_t *base) {
u32_t base0 = base[0];
static void dev_configure(uint32_t *base) {
uint32_t base0 = base[0];
sdr_out32(base0, REG_GCTRL, 0x3000);
}
/* Initialize the mixer (### INIT_MIXER ###) */
static void dev_init_mixer(u32_t *base) {
static void dev_init_mixer(uint32_t *base) {
dev_mixer_write(base, 0, 0);
}
/* Set DAC and ADC sample rate (### SET_SAMPLE_RATE ###) */
static void dev_set_sample_rate(u32_t *base, uint16_t sample_rate) {
u32_t base0 = base[0];
static void dev_set_sample_rate(uint32_t *base, uint16_t sample_rate) {
uint32_t base0 = base[0];
my_chan.delta = (sample_rate << 12) / 48000;
sdr_out16(base0, REG_SB_DELTA, (48000 << 12) / sample_rate);
}
/* Set DAC and ADC format (### SET_FORMAT ###)*/
static void dev_set_format(u32_t *base, u32_t bits, u32_t sign,
u32_t stereo, u32_t sample_count) {
u32_t data = 0, base0 = base[0];
static void dev_set_format(uint32_t *base, uint32_t bits, uint32_t sign,
uint32_t stereo, uint32_t sample_count) {
uint32_t data = 0, base0 = base[0];
if (bits == 16)
data |= CMD_FORMAT_BIT16;
if (sign == 1)
@@ -128,8 +128,8 @@ static void dev_set_format(u32_t *base, u32_t bits, u32_t sign,
}
/* Start the channel (### START_CHANNEL ###) */
static void dev_start_channel(u32_t *base, int sub_dev) {
u32_t data, base0 = base[0];
static void dev_start_channel(uint32_t *base, int sub_dev) {
uint32_t data, base0 = base[0];
if (sub_dev == DAC) {
my_chan.fmc = 3; my_chan.fms = 0; my_chan.ec = 0;
my_chan.alpha = 0; my_chan.cso = 0;
@@ -147,8 +147,8 @@ static void dev_start_channel(u32_t *base, int sub_dev) {
}
/* Stop the channel (### STOP_CHANNEL ###) */
static void dev_stop_channel(u32_t *base, int sub_dev) {
u32_t data, base0 = base[0];
static void dev_stop_channel(uint32_t *base, int sub_dev) {
uint32_t data, base0 = base[0];
if (sub_dev == DAC)
sdr_out32(base0, REG_STOP_A, 1);
else if (sub_dev == ADC)
@@ -156,8 +156,8 @@ static void dev_stop_channel(u32_t *base, int sub_dev) {
}
/* Set DMA address and length (### SET_DMA ###) */
static void dev_set_dma(u32_t *base, u32_t dma, u32_t len, int sub_dev) {
u32_t data, base0 = base[0];
static void dev_set_dma(uint32_t *base, uint32_t dma, uint32_t len, int sub_dev) {
uint32_t data, base0 = base[0];
my_chan.dma = dma;
my_chan.eso = len - 1;
if (sub_dev == ADC) {
@@ -170,8 +170,8 @@ static void dev_set_dma(u32_t *base, u32_t dma, u32_t len, int sub_dev) {
}
/* Read current address (### READ_DMA_CURRENT_ADDR ###) */
static u32_t dev_read_dma_current(u32_t *base, int sub_dev) {
u32_t data, base0 = base[0];
static uint32_t dev_read_dma_current(uint32_t *base, int sub_dev) {
uint32_t data, base0 = base[0];
sdr_out8(base0, REG_GCTRL, 0);
if (sub_dev == DAC)
data = sdr_in16(base0, REG_CHAN_BASE + 0x02);
@@ -182,8 +182,8 @@ static u32_t dev_read_dma_current(u32_t *base, int sub_dev) {
}
/* Pause the DMA (### PAUSE_DMA ###) */
static void dev_pause_dma(u32_t *base, int sub_dev) {
u32_t data, base0 = base[0];
static void dev_pause_dma(uint32_t *base, int sub_dev) {
uint32_t data, base0 = base[0];
if (sub_dev == DAC)
sdr_out32(base0, REG_STOP_A, 1);
else if (sub_dev == ADC) {
@@ -193,8 +193,8 @@ static void dev_pause_dma(u32_t *base, int sub_dev) {
}
/* Resume the DMA (### RESUME_DMA ###) */
static void dev_resume_dma(u32_t *base, int sub_dev) {
u32_t data, base0 = base[0];
static void dev_resume_dma(uint32_t *base, int sub_dev) {
uint32_t data, base0 = base[0];
if (sub_dev == DAC) {
data = sdr_in32(base0, REG_START_A);
sdr_out32(base0, REG_START_A, data | 0x01);
@@ -207,8 +207,8 @@ static void dev_resume_dma(u32_t *base, int sub_dev) {
/* Read and clear interrupt stats (### READ_CLEAR_INTR_STS ###)
* -- Return interrupt status */
static u32_t dev_read_clear_intr_status(u32_t *base) {
u32_t status, base0 = base[0];
static uint32_t dev_read_clear_intr_status(uint32_t *base) {
uint32_t status, base0 = base[0];
status = sdr_in32(base0, REG_INTR_STS);
if (status & INTR_STS_ADC) {
sdr_in8(base0, 0x1e);
@@ -218,8 +218,8 @@ static u32_t dev_read_clear_intr_status(u32_t *base) {
}
/* Enable or disable interrupt (### INTR_ENABLE_DISABLE ###) */
static void dev_intr_enable(u32_t *base, int flag) {
u32_t data, base0 = base[0];
static void dev_intr_enable(uint32_t *base, int flag) {
uint32_t data, base0 = base[0];
data = sdr_in32(base0, REG_INTR_CTRL_A);
data &= 0xfffe;
if (flag == INTR_ENABLE)
@@ -232,7 +232,7 @@ static void dev_intr_enable(u32_t *base, int flag) {
/* Probe the device */
static int dev_probe(void) {
int devind, i, ioflag;
u32_t device, bar, size, base;
uint32_t device, bar, size, base;
uint16_t vid, did, temp;
uint8_t *reg;
@@ -263,7 +263,7 @@ static int dev_probe(void) {
printf("SDR: Fail to map hardware registers from PCI\n");
return -EIO;
}
dev.base[i] = (u32_t)reg;
dev.base[i] = (uint32_t)reg;
}
#else
/* Get PCI BAR0-5 */
@@ -289,25 +289,25 @@ static int dev_probe(void) {
}
/* Set sample rate in configuration */
static int set_sample_rate(u32_t rate, int num) {
static int set_sample_rate(uint32_t rate, int num) {
aud_conf[num].sample_rate = rate;
return OK;
}
/* Set stereo in configuration */
static int set_stereo(u32_t stereo, int num) {
static int set_stereo(uint32_t stereo, int num) {
aud_conf[num].stereo = stereo;
return OK;
}
/* Set sample bits in configuration */
static int set_bits(u32_t bits, int num) {
static int set_bits(uint32_t bits, int num) {
aud_conf[num].nr_of_bits = bits;
return OK;
}
/* Set fragment size in configuration */
static int set_frag_size(u32_t frag_size, int num) {
static int set_frag_size(uint32_t frag_size, int num) {
if (frag_size > (sub_dev[num].DmaSize / sub_dev[num].NrOfDmaFragments) ||
frag_size < sub_dev[num].MinFragmentSize) {
return EINVAL;
@@ -317,20 +317,20 @@ static int set_frag_size(u32_t frag_size, int num) {
}
/* Set frame sign in configuration */
static int set_sign(u32_t val, int num) {
static int set_sign(uint32_t val, int num) {
aud_conf[num].sign = val;
return OK;
}
/* Get maximum fragment size */
static int get_max_frag_size(u32_t *val, int *len, int num) {
static int get_max_frag_size(uint32_t *val, int *len, int num) {
*len = sizeof(*val);
*val = (sub_dev[num].DmaSize / sub_dev[num].NrOfDmaFragments);
return OK;
}
/* Return 1 if there are free buffers */
static int free_buf(u32_t *val, int *len, int num) {
static int free_buf(uint32_t *val, int *len, int num) {
*len = sizeof(*val);
if (sub_dev[num].BufLength == sub_dev[num].NrOfExtraBuffers)
*val = 0;
@@ -340,11 +340,11 @@ static int free_buf(u32_t *val, int *len, int num) {
}
/* Get the current sample counter */
static int get_samples_in_buf(u32_t *result, int *len, int chan) {
u32_t res;
static int get_samples_in_buf(uint32_t *result, int *len, int chan) {
uint32_t res;
/* READ_DMA_CURRENT_ADDR */
res = dev_read_dma_current(dev.base, chan);
*result = (u32_t)(sub_dev[chan].BufLength * 8192) + res;
*result = (uint32_t)(sub_dev[chan].BufLength * 8192) + res;
return OK;
}
@@ -467,7 +467,7 @@ int drv_start(int sub_dev, int DmaMode) {
/* ======= [Audio interface] Driver start ======= */
int drv_stop(int sub_dev) {
u32_t data;
uint32_t data;
/* INTR_ENABLE_DISABLE */
dev_intr_enable(dev.base, INTR_DISABLE);
@@ -491,19 +491,19 @@ int drv_io_ctl(unsigned long request, void *val, int *len, int sub_dev) {
int status;
switch (request) {
case DSPIORATE:
status = set_sample_rate(*((u32_t *)val), sub_dev);
status = set_sample_rate(*((uint32_t *)val), sub_dev);
break;
case DSPIOSTEREO:
status = set_stereo(*((u32_t *)val), sub_dev);
status = set_stereo(*((uint32_t *)val), sub_dev);
break;
case DSPIOBITS:
status = set_bits(*((u32_t *)val), sub_dev);
status = set_bits(*((uint32_t *)val), sub_dev);
break;
case DSPIOSIZE:
status = set_frag_size(*((u32_t *)val), sub_dev);
status = set_frag_size(*((uint32_t *)val), sub_dev);
break;
case DSPIOSIGN:
status = set_sign(*((u32_t *)val), sub_dev);
status = set_sign(*((uint32_t *)val), sub_dev);
break;
case DSPIOMAX:
status = get_max_frag_size(val, len, sub_dev);
@@ -545,13 +545,13 @@ int drv_get_irq(char *irq) {
}
/* ======= [Audio interface] Get fragment size ======= */
int drv_get_frag_size(u32_t *frag_size, int sub_dev) {
int drv_get_frag_size(uint32_t *frag_size, int sub_dev) {
*frag_size = aud_conf[sub_dev].fragment_size;
return OK;
}
/* ======= [Audio interface] Set DMA channel ======= */
int drv_set_dma(u32_t dma, u32_t length, int chan) {
int drv_set_dma(uint32_t dma, uint32_t length, int chan) {
#ifdef DMA_LENGTH_BY_FRAME
length = length / (aud_conf[chan].nr_of_bits * (aud_conf[chan].stereo + 1) / 8);
#endif
@@ -562,7 +562,7 @@ int drv_set_dma(u32_t dma, u32_t length, int chan) {
/* ======= [Audio interface] Get interrupt summary status ======= */
int drv_int_sum(void) {
u32_t status;
uint32_t status;
/* ### READ_CLEAR_INTR_STS ### */
status = dev_read_clear_intr_status(dev.base);
dev.intr_status = status;
@@ -574,7 +574,7 @@ int drv_int_sum(void) {
/* ======= [Audio interface] Handle interrupt status ======= */
int drv_int(int sub_dev) {
u32_t mask;
uint32_t mask;
/* ### CHECK_INTR_DAC ### */
if (sub_dev == DAC)

26
minix/drivers/audio/trident/trident.h
View File

@@ -69,20 +69,20 @@
#define CMD_FORMAT_STEREO 0x04
typedef struct channel_info {
u32_t cso, alpha, fms, fmc, ec;
u32_t dma, eso, delta, bufhalf, index;
u32_t rvol, cvol, gvsel, pan, vol, ctrl;
uint32_t cso, alpha, fms, fmc, ec;
uint32_t dma, eso, delta, bufhalf, index;
uint32_t rvol, cvol, gvsel, pan, vol, ctrl;
} channel_info;
static channel_info my_chan;
/* Driver Data Structure */
typedef struct aud_sub_dev_conf_t {
u32_t stereo;
uint32_t stereo;
uint16_t sample_rate;
u32_t nr_of_bits;
u32_t sign;
u32_t busy;
u32_t fragment_size;
uint32_t nr_of_bits;
uint32_t sign;
uint32_t busy;
uint32_t fragment_size;
uint8_t format;
} aud_sub_dev_conf_t;
@@ -90,14 +90,14 @@ typedef struct DEV_STRUCT {
char *name;
uint16_t vid;
uint16_t did;
u32_t devind;
u32_t base[6];
uint32_t devind;
uint32_t base[6];
char irq;
char revision;
u32_t intr_status;
uint32_t intr_status;
} DEV_STRUCT;
void dev_mixer_write(u32_t *base, u32_t reg, u32_t val);
u32_t dev_mixer_read(u32_t *base, u32_t reg);
void dev_mixer_write(uint32_t *base, uint32_t reg, uint32_t val);
uint32_t dev_mixer_read(uint32_t *base, uint32_t reg);
#endif

2
minix/drivers/bus/i2c/arch/earm/omap_i2c.c
View File

@@ -394,7 +394,7 @@ static void
omap_i2c_padconf(int i2c_bus_id)
{
int r;
u32_t pinopts;
uint32_t pinopts;
if (omap_i2c_bus->bus_type == AM335X_I2C_BUS) {

2
minix/drivers/bus/i2c/i2c.c
View File

@@ -368,7 +368,7 @@ static void
ds_event(void)
{
char key[DS_MAX_KEYLEN];
u32_t value;
uint32_t value;
int type;
endpoint_t owner_endpoint;
int r;

6
minix/drivers/bus/pci/main.c
View File

@@ -393,7 +393,7 @@ static void
do_attr_r32(message *mp)
{
int r, devind, port;
u32_t v;
uint32_t v;
devind= mp->m2_i1;
port= mp->m2_i2;
@@ -459,7 +459,7 @@ static void
do_attr_w32(message *mp)
{
int r, devind, port;
u32_t v;
uint32_t v;
devind= mp->m2_i1;
port= mp->m2_i2;
@@ -479,7 +479,7 @@ static void
do_get_bar(message *mp)
{
int r, devind, port, ioflag;
u32_t base, size;
uint32_t base, size;
devind= mp->m_lsys_pci_busc_get_bar.devind;
port= mp->m_lsys_pci_busc_get_bar.port;

58
minix/drivers/bus/pci/pci.c
View File

@@ -50,10 +50,10 @@ static struct pcibus
int pb_busnr;
uint8_t (*pb_rreg8)(int busind, int devind, int port);
uint16_t (*pb_rreg16)(int busind, int devind, int port);
u32_t (*pb_rreg32)(int busind, int devind, int port);
uint32_t (*pb_rreg32)(int busind, int devind, int port);
void (*pb_wreg8)(int busind, int devind, int port, uint8_t value);
void (*pb_wreg16)(int busind, int devind, int port, uint16_t value);
void (*pb_wreg32)(int busind, int devind, int port, u32_t value);
void (*pb_wreg32)(int busind, int devind, int port, uint32_t value);
uint16_t (*pb_rsts)(int busind);
void (*pb_wsts)(int busind, uint16_t value);
} pcibus[NR_PCIBUS];
@@ -80,8 +80,8 @@ static struct pcidev
{
int pb_flags;
int pb_nr;
u32_t pb_base;
u32_t pb_size;
uint32_t pb_base;
uint32_t pb_size;
} pd_bar[BAM_NR];
int pd_bar_nr;
} pcidev[NR_PCIDEV];
@@ -99,7 +99,7 @@ static struct machine machine;
*===========================================================================*/
static unsigned
pci_inb(uint16_t port) {
u32_t value;
uint32_t value;
int s;
if ((s=sys_inb(port, &value)) !=OK)
printf("PCI: warning, sys_inb failed: %d\n", s);
@@ -108,7 +108,7 @@ pci_inb(uint16_t port) {
static unsigned
pci_inw(uint16_t port) {
u32_t value;
uint32_t value;
int s;
if ((s=sys_inw(port, &value)) !=OK)
printf("PCI: warning, sys_inw failed: %d\n", s);
@@ -117,7 +117,7 @@ pci_inw(uint16_t port) {
static unsigned
pci_inl(uint16_t port) {
u32_t value;
uint32_t value;
int s;
if ((s=sys_inl(port, &value)) !=OK)
printf("PCI: warning, sys_inl failed: %d\n", s);
@@ -139,7 +139,7 @@ pci_outw(uint16_t port, uint16_t value) {
}
static void
pci_outl(uint16_t port, u32_t value) {
pci_outl(uint16_t port, uint32_t value) {
int s;
if ((s=sys_outl(port, value)) !=OK)
printf("PCI: warning, sys_outl failed: %d\n", s);
@@ -185,10 +185,10 @@ pcii_rreg16(int busind, int devind, int port)
return v;
}
static u32_t
static uint32_t
pcii_rreg32(int busind, int devind, int port)
{
u32_t v;
uint32_t v;
int s;
v= PCII_RREG32_(pcibus[busind].pb_busnr,
@@ -240,7 +240,7 @@ pcii_wreg16(int busind, int devind, int port, uint16_t value)
}
static void
pcii_wreg32(int busind, int devind, int port, u32_t value)
pcii_wreg32(int busind, int devind, int port, uint32_t value)
{
int s;
#if 0
@@ -332,7 +332,7 @@ __pci_attr_r16(int devind, int port)
return pcibus[busind].pb_rreg16(busind, devind, port);
}
static u32_t
static uint32_t
__pci_attr_r32(int devind, int port)
{
int busnr, busind;
@@ -363,7 +363,7 @@ __pci_attr_w16(int devind, int port, uint16_t value)
}
static void
__pci_attr_w32(int devind, int port, u32_t value)
__pci_attr_w32(int devind, int port, uint32_t value)
{
int busnr, busind;
@@ -465,7 +465,7 @@ pci_vid_name(uint16_t vid)
static void
print_hyper_cap(int devind, uint8_t capptr)
{
u32_t v;
uint32_t v;
uint16_t cmd;
int type0, type1;
@@ -580,7 +580,7 @@ print_capabilities(int devind)
* ISA Bridge Helpers *
*===========================================================================*/
static void
update_bridge4dev_io(int devind, u32_t io_base, u32_t io_size)
update_bridge4dev_io(int devind, uint32_t io_base, uint32_t io_size)
{
int busnr, busind, type, br_devind;
uint16_t v16;
@@ -617,7 +617,7 @@ static int
do_piix(int devind)
{
int i, s, irqrc, irq;
u32_t elcr1, elcr2, elcr;
uint32_t elcr1, elcr2, elcr;
#if DEBUG
printf("in piix\n");
@@ -789,7 +789,7 @@ do_isabridge(int busind)
{
int i, j, r, type, busnr, unknown_bridge, bridge_dev;
uint16_t vid, did;
u32_t t3;
uint32_t t3;
const char *dstr;
unknown_bridge= -1;
@@ -1009,7 +1009,7 @@ static int
record_bar(int devind, int bar_nr, int last)
{
int reg, prefetch, type, dev_bar_nr, width;
u32_t bar, bar2;
uint32_t bar, bar2;
uint16_t cmd;
/* Start by assuming that this is a 32-bit bar, taking up one DWORD. */
@@ -1221,7 +1221,7 @@ record_bars_normal(int devind)
static void
record_bars_bridge(int devind)
{
u32_t base, limit, size;
uint32_t base, limit, size;
/* The generic BAR area of PCI-to-PCI bridges is two DWORDs in size.
* It may contain up to two 32-bit BARs, or one 64-bit BAR.
@@ -1270,7 +1270,7 @@ record_bars_bridge(int devind)
static void
record_bars_cardbus(int devind)
{
u32_t base, limit, size;
uint32_t base, limit, size;
/* The generic BAR area of CardBus devices is one DWORD in size. */
record_bars(devind, PCI_BAR);
@@ -1320,7 +1320,7 @@ static void
complete_bars(void)
{
int i, j, bar_nr, reg;
u32_t memgap_low, memgap_high, iogap_low, iogap_high, io_high,
uint32_t memgap_low, memgap_high, iogap_low, iogap_high, io_high,
base, size, v32, diff1, diff2;
kinfo_t kinfo;
@@ -1437,7 +1437,7 @@ complete_bars(void)
if (size < PAGE_SIZE)
size= PAGE_SIZE;
base= memgap_high-size;
base &= ~(u32_t)(size-1);
base &= ~(uint32_t)(size-1);
if (base < memgap_low)
panic("memory base too low: %d", base);
memgap_high= base;
@@ -1466,7 +1466,7 @@ complete_bars(void)
continue;
size= pcidev[i].pd_bar[j].pb_size;
base= iogap_high-size;
base &= ~(u32_t)(size-1);
base &= ~(uint32_t)(size-1);
/* Assume that ISA compatibility is required. Only
* use the lowest 256 bytes out of every 1024 bytes.
@@ -1786,7 +1786,7 @@ do_pcibridge(int busind)
int ind, type;
uint16_t vid, did;
uint8_t sbusn, baseclass, subclass, infclass, headt;
u32_t t3;
uint32_t t3;
vid= did= 0; /* lint */
busnr= pcibus[busind].pb_busnr;
@@ -1927,7 +1927,7 @@ pci_intel_init(void)
* Two times the value 0xffff suggests a system without a (compatible)
* PCI controller.
*/
u32_t bus, dev, func;
uint32_t bus, dev, func;
uint16_t vid, did;
int s, i, r, busind, busnr;
const char *dstr;
@@ -2040,7 +2040,7 @@ visible(struct rs_pci *aclp, int devind)
{
uint16_t acl_sub_vid, acl_sub_did;
int i;
u32_t class_id;
uint32_t class_id;
if (!aclp)
return TRUE; /* Should be changed when ACLs become
@@ -2441,7 +2441,7 @@ _pci_dev_name(uint16_t vid, uint16_t did)
* _pci_get_bar *
*===========================================================================*/
int
_pci_get_bar(int devind, int port, u32_t *base, u32_t *size,
_pci_get_bar(int devind, int port, uint32_t *base, uint32_t *size,
int *ioflag)
{
int i, reg;
@@ -2502,7 +2502,7 @@ _pci_attr_r16(int devind, int port, uint16_t *vp)
* _pci_attr_r32 *
*===========================================================================*/
int
_pci_attr_r32(int devind, int port, u32_t *vp)
_pci_attr_r32(int devind, int port, uint32_t *vp)
{
if (devind < 0 || devind >= nr_pcidev)
return EINVAL;
@@ -2547,7 +2547,7 @@ _pci_attr_w16(int devind, int port, uint16_t value)
* _pci_attr_w32 *
*===========================================================================*/
int
_pci_attr_w32(int devind, int port, u32_t value)
_pci_attr_w32(int devind, int port, uint32_t value)
{
if (devind < 0 || devind >= nr_pcidev)
return EINVAL;

6
minix/drivers/bus/pci/pci.h
View File

@@ -53,7 +53,7 @@ void _pci_rescan_bus(uint8_t busnr);
const char *_pci_dev_name(uint16_t vid, uint16_t did);
int _pci_get_bar(int devind, int port, u32_t *base, u32_t *size, int
int _pci_get_bar(int devind, int port, uint32_t *base, uint32_t *size, int
*ioflag);
int _pci_slot_name(int devind, char **cpp);
int _pci_ids(int devind, uint16_t *vidp, uint16_t *didp);
@@ -61,12 +61,12 @@ int _pci_ids(int devind, uint16_t *vidp, uint16_t *didp);
/* PCI Config Read functions */
int _pci_attr_r8(int devind, int port, uint8_t *vp);
int _pci_attr_r16(int devind, int port, uint16_t *vp);
int _pci_attr_r32(int devind, int port, u32_t *vp);
int _pci_attr_r32(int devind, int port, uint32_t *vp);
/* PCI Config Write functions */
int _pci_attr_w8(int devind, int port, uint8_t value);
int _pci_attr_w16(int devind, int port, uint16_t value);
int _pci_attr_w32(int devind, int port, u32_t value);
int _pci_attr_w32(int devind, int port, uint32_t value);
/* minix hooks into NetBSD PCI IDS DB */
typedef uint32_t pcireg_t;

4
minix/drivers/bus/ti1225/ti1225.c
View File

@@ -140,7 +140,7 @@ static void hw_init(struct port *pp, int devind)
{
uint8_t v8;
uint16_t v16;
u32_t v32;
uint32_t v32;
#if USE_INTS
int r, irq;
#endif
@@ -249,7 +249,7 @@ static void do_int(struct port *pp)
int devind, vcc_5v, vcc_3v, vcc_Xv, vcc_Yv,
socket_5v, socket_3v, socket_Xv, socket_Yv;
spin_t spin;
u32_t csr_event, csr_present, csr_control;
uint32_t csr_event, csr_present, csr_control;
uint8_t v8;
uint16_t v16;
#if USE_INTS

18
minix/drivers/bus/ti1225/ti1225.h
View File

@@ -19,15 +19,15 @@ Created: Dec 2005 by Philip Homburg
/* CardBus Socket Registers */
struct csr
{
/*00*/ u32_t csr_event;
/*04*/ u32_t csr_mask;
/*08*/ u32_t csr_present;
/*0C*/ u32_t csr_force_event;
/*10*/ u32_t csr_control;
/*14*/ u32_t csr_res0;
/*18*/ u32_t csr_res1;
/*1C*/ u32_t csr_res2;
/*20*/ u32_t csr_power;
/*00*/ uint32_t csr_event;
/*04*/ uint32_t csr_mask;
/*08*/ uint32_t csr_present;
/*0C*/ uint32_t csr_force_event;
/*10*/ uint32_t csr_control;
/*14*/ uint32_t csr_res0;
/*18*/ uint32_t csr_res1;
/*1C*/ uint32_t csr_res2;
/*20*/ uint32_t csr_power;
};
/* csr_mask */

4
minix/drivers/clock/readclock/arch/earm/omap_rtc.c
View File

@@ -122,8 +122,8 @@ static struct log log = {
.log_func = default_log
};
static u32_t use_count = 0;
static u32_t pwr_off_in_progress = 0;
static uint32_t use_count = 0;
static uint32_t pwr_off_in_progress = 0;
static void omap_rtc_unlock(void);
static void omap_rtc_lock(void);

2
minix/drivers/clock/readclock/arch/i386/arch_readclock.c
View File

@@ -213,7 +213,7 @@ arch_get_time(struct tm *t, int flags)
static int
read_register(int reg_addr)
{
u32_t r;
uint32_t r;
if (sys_outb(RTC_INDEX, reg_addr) != OK) {
log_warn(&log, "outb failed of %x\n", RTC_INDEX);

2
minix/drivers/eeprom/cat24c256/cat24c256.c
View File

@@ -401,7 +401,7 @@ static int
lu_state_restore(void)
{
/* Restore the state. */
u32_t value;
uint32_t value;
ds_retrieve_u32("bus", &value);
ds_delete_u32("bus");

2
minix/drivers/examples/hello/hello.c
View File

@@ -82,7 +82,7 @@ static int sef_cb_lu_state_save(int UNUSED(state), int UNUSED(flags)) {
static int lu_state_restore() {
/* Restore the state. */
u32_t value;
uint32_t value;
ds_retrieve_u32("open_counter", &value);
ds_delete_u32("open_counter");

10
minix/drivers/hid/pckbd/pckbd.c
View File

@@ -65,7 +65,7 @@ kbd_watchdog(int arg __unused)
static void
kbd_send(void)
{
u32_t sb;
uint32_t sb;
int r;
if (!kbdout.avail)
@@ -110,7 +110,7 @@ kbd_send(void)
static int
scan_keyboard(unsigned char *bp, int *isauxp)
{
u32_t b, sb;
uint32_t b, sb;
int r;
if ((r = sys_inb(KB_STATUS, &sb)) != OK) {
@@ -151,7 +151,7 @@ static int
kb_wait(void)
{
spin_t spin;
u32_t status;
uint32_t status;
int r, isaux;
unsigned char byte;
@@ -226,7 +226,7 @@ kbc_cmd1(int cmd, int data)
static int
kbc_read(void)
{
u32_t byte, status;
uint32_t byte, status;
spin_t spin;
int r;
@@ -373,7 +373,7 @@ kbd_process(unsigned char scode)
static void
kbdaux_process(unsigned char scode)
{
u32_t delta;
uint32_t delta;
int i;
if (aux_counter == 0 && !(scode & 0x08))

18
minix/drivers/iommu/amddev/amddev.c
View File

@@ -50,8 +50,8 @@ static uint8_t dev_capptr;
static uint8_t *table;
static int find_dev(int *devindp, uint8_t *capaddrp);
static u32_t read_reg(int function, int index);
static void write_reg(int function, int index, u32_t value);
static uint32_t read_reg(int function, int index);
static void write_reg(int function, int index, uint32_t value);
static void init_domain(int index);
static void init_map(unsigned int ix);
static int do_add4pci(const message *m);
@@ -119,7 +119,7 @@ static int sef_cb_init_fresh(int UNUSED(type), sef_init_info_t *UNUSED(info))
/* Initialize the amddev driver. */
int r, n_maps, n_domains, revision;
uint16_t flags;
u32_t bits;
uint32_t bits;
printf("amddev: starting\n");
@@ -266,14 +266,14 @@ uint8_t *capaddrp;
return 0;
}
static u32_t read_reg(int function, int index)
static uint32_t read_reg(int function, int index)
{
pci_attr_w32(dev_devind, dev_capptr + DEV_OP, ((function <<
DEV_OP_FUNC_SHIFT) | index));
return pci_attr_r32(dev_devind, dev_capptr + DEV_DATA);
}
static void write_reg(int function, int index, u32_t value)
static void write_reg(int function, int index, uint32_t value)
{
pci_attr_w32(dev_devind, dev_capptr + DEV_OP, ((function <<
DEV_OP_FUNC_SHIFT) | index));
@@ -313,7 +313,7 @@ printf("init_domain: busaddr = 0x%lx\n", busaddr);
static void init_map(unsigned int ix)
{
u32_t v, dom, busno, unit0, unit1;
uint32_t v, dom, busno, unit0, unit1;
dom= 1;
busno= 7;
@@ -441,7 +441,7 @@ static void add_range(phys_bytes busaddr, phys_bytes size)
for (o= 0; o<size; o += PAGE_SIZE)
{
u32_t bit= (busaddr+o)/PAGE_SIZE;
uint32_t bit= (busaddr+o)/PAGE_SIZE;
table[bit/8] &= ~(1U << (bit % 8));
}
}
@@ -457,7 +457,7 @@ static void del_range(phys_bytes busaddr, phys_bytes size)
for (o= 0; o<size; o += PAGE_SIZE)
{
u32_t bit= (busaddr+o)/PAGE_SIZE;
uint32_t bit= (busaddr+o)/PAGE_SIZE;
table[bit/8] |= (1 << (bit % 8));
}
}
@@ -465,7 +465,7 @@ static void del_range(phys_bytes busaddr, phys_bytes size)
static void report_exceptions(void)
{
u32_t status;
uint32_t status;
status= read_reg(DEVF_ERR_STATUS, 0);
if (!(status & 0x80000000))

26
minix/drivers/net/dec21140A/dec21140A.c
View File

@@ -17,8 +17,8 @@
#include "dec21140A.h"
static u32_t io_inl(uint16_t);
static void io_outl(uint16_t, u32_t);
static uint32_t io_inl(uint16_t);
static void io_outl(uint16_t, uint32_t);
static int do_init(unsigned int, netdriver_addr_t *, uint32_t *,
unsigned int *);
@@ -141,8 +141,8 @@ static uint16_t de_read_rom(const dpeth_t *dep, uint8_t addr, uint8_t nbAddrBits
{
uint16_t retVal = 0;
int i;
u32_t csr = 0;
u32_t csr2 = 0; /* csr2 is used to hold constant values that are
uint32_t csr = 0;
uint32_t csr2 = 0; /* csr2 is used to hold constant values that are
setup in the init phase, it makes this a little
more readable, the following macro is also just
to clear up the code a little.*/
@@ -201,7 +201,7 @@ static uint16_t de_read_rom(const dpeth_t *dep, uint8_t addr, uint8_t nbAddrBits
static ssize_t do_recv(struct netdriver_data *data, size_t max)
{
u32_t size;
uint32_t size;
dpeth_t *dep;
de_loc_descr_t *descr;
@@ -313,7 +313,7 @@ static void de_init_buf(dpeth_t *dep)
(phys_bytes *) &(loc_descr->descr->des[DES_BUF1]));
if(r != OK) panic("umap failed: %d", r);
loc_descr->descr->des[DES_BUF2] = 0;
memset(&loc_descr->descr->des[DES0],0,sizeof(u32_t));
memset(&loc_descr->descr->des[DES0],0,sizeof(uint32_t));
loc_descr->descr->des[DES1] = temp;
if(j==( (i==DESCR_RECV?DE_NB_RECV_DESCR:DE_NB_SEND_DESCR)-1))
loc_descr->descr->des[DES1] |= DES1_ER;
@@ -361,7 +361,7 @@ static void de_init_buf(dpeth_t *dep)
static void do_intr(unsigned int __unused mask)
{
dpeth_t *dep;
u32_t val;
uint32_t val;
dep = &de_state;
@@ -395,7 +395,7 @@ static void do_stop(void)
static void de_hw_conf(const dpeth_t *dep)
{
u32_t val;
uint32_t val;
/* CSR0 - global host bus prop */
val = CSR0_BAR | CSR0_CAL_8;
@@ -421,7 +421,7 @@ static void de_hw_conf(const dpeth_t *dep)
static void de_start(const dpeth_t *dep)
{
u32_t val;
uint32_t val;
val = io_inl(CSR_ADDR(dep, CSR6)) | CSR6_ST | CSR6_SR;
io_outl(CSR_ADDR(dep, CSR6), val);
}
@@ -429,7 +429,7 @@ static void de_start(const dpeth_t *dep)
static void de_setup_frame(const dpeth_t *dep, const netdriver_addr_t *addr)
{
int i;
u32_t val;
uint32_t val;
/* this is not perfect... we assume pass all multicast and only
filter non-multicast frames */
@@ -492,16 +492,16 @@ static int do_send(struct netdriver_data *data, size_t size)
return OK;
}
static u32_t io_inl(uint16_t port)
static uint32_t io_inl(uint16_t port)
{
u32_t value;
uint32_t value;
int rc;
if ((rc = sys_inl(port, &value)) != OK)
panic("sys_inl failed: %d", rc);
return value;
}
static void io_outl(uint16_t port, u32_t value)
static void io_outl(uint16_t port, uint32_t value)
{
int rc;
if ((rc = sys_outl(port, value)) != OK)

2
minix/drivers/net/dec21140A/dec21140A.h
View File

@@ -27,7 +27,7 @@ Created: 09/01/2009 Nicolas Tittley (first.last @ gmail DOT com)
#define DE_SETUP_FRAME_SIZE 192
typedef struct de_descr {
u32_t des[4];
uint32_t des[4];
} de_descr_t;
typedef struct de_local_descr {

2
minix/drivers/net/dp8390/3c503.c
View File

@@ -20,7 +20,7 @@
#if ENABLE_3C503
extern u32_t system_hz;
extern uint32_t system_hz;
#define MILLIS_TO_TICKS(m) (((m)*system_hz/1000)+1)

6
minix/drivers/net/dp8390/dp8390.c
View File

@@ -24,7 +24,7 @@
static dpeth_t de_state;
u32_t system_hz;
uint32_t system_hz;
/* Configuration */
typedef struct dp_conf
@@ -935,7 +935,7 @@ static void map_hw_buffer(dpeth_t *dep)
uint8_t inb(port_t port)
{
int r;
u32_t value;
uint32_t value;
r= sys_inb(port, &value);
if (r != OK)
@@ -949,7 +949,7 @@ uint8_t inb(port_t port)
uint16_t inw(port_t port)
{
int r;
u32_t value;
uint32_t value;
r= sys_inw(port, &value);
if (r != OK)

2
minix/drivers/net/dp8390/ne2000.c
View File

@@ -18,7 +18,7 @@ Created: March 15, 1994 by Philip Homburg <philip@f-mnx.phicoh.com>
#define N 100
extern u32_t system_hz;
extern uint32_t system_hz;
#define MILLIS_TO_TICKS(m) (((m)*system_hz/1000)+1)

2
minix/drivers/net/dp8390/rtl8029.c
View File

@@ -33,7 +33,7 @@ int skip;
{
int r, devind;
uint16_t vid, did;
u32_t bar;
uint32_t bar;
uint8_t ilr;
const char *dname;

4
minix/drivers/net/dpeth/devio.c
View File

@@ -25,7 +25,7 @@ static void warning(const char *type, int err)
*/
unsigned int inb(unsigned short port)
{
u32_t value;
uint32_t value;
int rc;
if ((rc = sys_inb(port, &value)) != OK) warning("inb", rc);
@@ -38,7 +38,7 @@ unsigned int inb(unsigned short port)
*/
unsigned int inw(unsigned short port)
{
u32_t value;
uint32_t value;
int rc;
if ((rc = sys_inw(port, &value)) != OK) warning("inw", rc);

24
minix/drivers/net/e1000/e1000.c
View File

@@ -30,7 +30,7 @@ static void e1000_reg_unset(e1000_t *e, uint32_t reg, uint32_t value);
static uint16_t eeprom_eerd(e1000_t *e, int reg);
static uint16_t eeprom_ich(e1000_t *e, int reg);
static int eeprom_ich_init(e1000_t *e);
static int eeprom_ich_cycle(e1000_t *e, u32_t timeout);
static int eeprom_ich_cycle(e1000_t *e, uint32_t timeout);
static int e1000_instance;
static e1000_t e1000_state;
@@ -102,7 +102,7 @@ e1000_init(unsigned int instance, netdriver_addr_t * addr, uint32_t * caps,
static void
e1000_map_flash(e1000_t * e, int devind, int did)
{
u32_t flash_addr, gfpreg, sector_base_addr;
uint32_t flash_addr, gfpreg, sector_base_addr;
size_t flash_size;
/* The flash memory is pointed to by BAR2. It may not be present. */
@@ -146,8 +146,8 @@ e1000_probe(e1000_t * e, int skip)
{
int r, devind, ioflag;
uint16_t vid, did, cr;
u32_t status;
u32_t base, size;
uint32_t status;
uint32_t base, size;
const char *dname;
E1000_DEBUG(3, ("%s: probe()\n", netdriver_name()));
@@ -448,7 +448,7 @@ e1000_set_hwaddr(const netdriver_addr_t * hwaddr)
e = &e1000_state;
e1000_reg_write(e, E1000_REG_RAL,
*(const u32_t *)(&hwaddr->na_addr[0]));
*(const uint32_t *)(&hwaddr->na_addr[0]));
e1000_reg_write(e, E1000_REG_RAH,
*(const uint16_t *)(&hwaddr->na_addr[4]));
e1000_reg_set(e, E1000_REG_RAH, E1000_REG_RAH_AV);
@@ -603,7 +603,7 @@ static void
e1000_intr(unsigned int __unused mask)
{
e1000_t *e;
u32_t cause;
uint32_t cause;
E1000_DEBUG(3, ("e1000: interrupt\n"));
@@ -687,7 +687,7 @@ e1000_reg_write(e1000_t * e, uint32_t reg, uint32_t value)
assert(reg < 0x1ffff);
/* Write to memory mapped register. */
*(volatile u32_t *)(e->regs + reg) = value;
*(volatile uint32_t *)(e->regs + reg) = value;
}
/*
@@ -726,7 +726,7 @@ e1000_reg_unset(e1000_t * e, uint32_t reg, uint32_t value)
static uint16_t
eeprom_eerd(e1000_t * e, int reg)
{
u32_t data;
uint32_t data;
/* Request EEPROM read. */
e1000_reg_write(e, E1000_REG_EERD,
@@ -815,12 +815,12 @@ eeprom_ich_init(e1000_t * e)
* Start ICH8 flash cycle.
*/
static int
eeprom_ich_cycle(e1000_t * e, u32_t timeout)
eeprom_ich_cycle(e1000_t * e, uint32_t timeout)
{
union ich8_hws_flash_ctrl hsflctl;
union ich8_hws_flash_status hsfsts;
int ret_val = -1;
u32_t i = 0;
uint32_t i = 0;
E1000_DEBUG(3, ("e1000_flash_cycle_ich8lan"));
@@ -851,8 +851,8 @@ eeprom_ich(e1000_t * e, int reg)
{
union ich8_hws_flash_status hsfsts;
union ich8_hws_flash_ctrl hsflctl;
u32_t flash_linear_addr;
u32_t flash_data = 0;
uint32_t flash_linear_addr;
uint32_t flash_data = 0;
int ret_val = -1;
uint8_t count = 0;
uint16_t data = 0;

6
minix/drivers/net/e1000/e1000.h
View File

@@ -75,7 +75,7 @@
* @param reg Register offset.
*/
#define E1000_READ_FLASH_REG(e,reg) \
*(u32_t *) (((e)->flash) + (reg))
*(uint32_t *) (((e)->flash) + (reg))
/**
* Read a 16-bit word from flash memory.
@@ -92,7 +92,7 @@
* @param value New value.
*/
#define E1000_WRITE_FLASH_REG(e,reg,value) \
*((u32_t *) (((e)->flash) + (reg))) = (value)
*((uint32_t *) (((e)->flash) + (reg))) = (value)
/**
* Write a 16-bit word to flash memory.
@@ -116,7 +116,7 @@ typedef struct e1000
int irq_hook; /**< Interrupt Request Vector Hook. */
uint8_t *regs; /**< Memory mapped hardware registers. */
uint8_t *flash; /**< Optional flash memory. */
u32_t flash_base_addr; /**< Flash base address. */
uint32_t flash_base_addr; /**< Flash base address. */
uint16_t (*eeprom_read)(struct e1000 *, int reg);
/**< Function to read the EEPROM. */
int eeprom_done_bit; /**< Offset of the EERD.DONE bit. */

8
minix/drivers/net/e1000/e1000_hw.h
View File

@@ -30,8 +30,8 @@
*/
typedef struct e1000_rx_desc
{
u32_t buffer; /**< Address of the receive data buffer (64-bit). */
u32_t buffer_h; /**< High 32-bits of the receive data buffer (unused). */
uint32_t buffer; /**< Address of the receive data buffer (64-bit). */
uint32_t buffer_h; /**< High 32-bits of the receive data buffer (unused). */
uint16_t length; /**< Size of the receive buffer. */
uint16_t checksum; /**< Packet checksum. */
uint8_t status; /**< Descriptor status. */
@@ -45,8 +45,8 @@ e1000_rx_desc_t;
*/
typedef struct e1000_tx_desc
{
u32_t buffer; /**< Address of the transmit buffer (64-bit). */
u32_t buffer_h; /**< High 32-bits of the transmit buffer (unused). */
uint32_t buffer; /**< Address of the transmit buffer (64-bit). */
uint32_t buffer_h; /**< High 32-bits of the transmit buffer (unused). */
uint16_t length; /**< Size of the transmit buffer contents. */
uint8_t checksum_off; /**< Checksum Offset. */
uint8_t command; /**< Command field. */

22
minix/drivers/net/fxp/fxp.c
View File

@@ -124,9 +124,9 @@ static uint16_t eeprom_read(fxp_t *fp, int reg);
static void eeprom_addrsize(fxp_t *fp);
static uint16_t mii_read(fxp_t *fp, int reg);
static uint8_t do_inb(port_t port);
static u32_t do_inl(port_t port);
static uint32_t do_inl(port_t port);
static void do_outb(port_t port, uint8_t v);
static void do_outl(port_t port, u32_t v);
static void do_outl(port_t port, uint32_t v);
static void tell_iommu(vir_bytes start, size_t size, int pci_bus, int
pci_dev, int pci_func);
@@ -235,7 +235,7 @@ static int fxp_probe(fxp_t *fp, int skip)
{
int r, devind;
uint16_t vid, did, cr;
u32_t bar;
uint32_t bar;
uint8_t ilr, rev;
const char *str;
#if VERBOSE
@@ -1041,7 +1041,7 @@ fxp_t *fp;
static void fxp_update_stats(void)
{
fxp_t *fp;
u32_t *p;
uint32_t *p;
fp= fxp_state;
@@ -1126,7 +1126,7 @@ static void fxp_check_ints(fxp_t *fp)
int n, prev_tail;
int fxp_tx_tail, fxp_tx_nbuf, fxp_tx_threshold;
port_t port;
u32_t busaddr;
uint32_t busaddr;
uint16_t tx_status;
uint8_t scb_status;
struct tx *txp;
@@ -1326,7 +1326,7 @@ static void fxp_report_link(fxp_t *fp)
uint16_t mii_ctrl, mii_status, mii_id1, mii_id2,
mii_ana, mii_anlpa, mii_ane, mii_extstat,
mii_ms_ctrl, mii_ms_status, scr;
u32_t oui;
uint32_t oui;
int model, rev;
int f, link_up;
@@ -1680,7 +1680,7 @@ static uint16_t mii_read(fxp_t *fp, int reg)
{
spin_t spin;
port_t port;
u32_t v;
uint32_t v;
port= fp->fxp_base_port;
@@ -1705,7 +1705,7 @@ static uint16_t mii_read(fxp_t *fp, int reg)
static uint8_t do_inb(port_t port)
{
int r;
u32_t value;
uint32_t value;
r= sys_inb(port, &value);
if (r != OK)
@@ -1713,10 +1713,10 @@ static uint8_t do_inb(port_t port)
return value;
}
static u32_t do_inl(port_t port)
static uint32_t do_inl(port_t port)
{
int r;
u32_t value;
uint32_t value;
r= sys_inl(port, &value);
if (r != OK)
@@ -1733,7 +1733,7 @@ static void do_outb(port_t port, uint8_t value)
panic("sys_outb failed: %d", r);
}
static void do_outl(port_t port, u32_t value)
static void do_outl(port_t port, uint32_t value)
{
int r;

56
minix/drivers/net/fxp/fxp.h
View File

@@ -169,7 +169,7 @@ struct ias
{
uint16_t ias_status;
uint16_t ias_command;
u32_t ias_linkaddr;
uint32_t ias_linkaddr;
uint8_t ias_ethaddr[6];
uint8_t ias_reserved[2];
};
@@ -180,7 +180,7 @@ struct cbl_conf
{
uint16_t cc_status;
uint16_t cc_command;
u32_t cc_linkaddr;
uint32_t cc_linkaddr;
uint8_t cc_bytes[CC_BYTES_NR];
};
@@ -424,8 +424,8 @@ struct tx
{
uint16_t tx_status;
uint16_t tx_command;
u32_t tx_linkaddr;
u32_t tx_tbda;
uint32_t tx_linkaddr;
uint32_t tx_tbda;
uint16_t tx_size;
uint8_t tx_tthresh;
uint8_t tx_ntbd;
@@ -459,39 +459,39 @@ struct tx
/* Statistical Counters */
struct sc
{
u32_t sc_tx_good; /* Transmit Good Frames */
u32_t sc_tx_maxcol; /* Transmit Maximum Collisions errors */
u32_t sc_tx_latecol; /* Transmit Late Collisions errors */
u32_t sc_tx_underrun; /* Transmit Underrun errors */
u32_t sc_tx_crs; /* Transmit Lost Carrier Sense */
u32_t sc_tx_defered; /* Transmit Defered */
u32_t sc_tx_scol; /* Transmit Single Collision */
u32_t sc_tx_mcol; /* Transmit Multiple Collisions */
u32_t sc_tx_totcol; /* Transmit Total Collisions */
u32_t sc_rx_good; /* Receive Good Frames */
u32_t sc_rx_crc; /* Receive CRC errors */
u32_t sc_rx_align; /* Receive Alignment errors */
u32_t sc_rx_resource; /* Receive Resource errors */
u32_t sc_rx_overrun; /* Receive Overrun errors */
u32_t sc_rx_cd; /* Receive Collision Detect errors */
u32_t sc_rx_short; /* Receive Short Frame errors */
uint32_t sc_tx_good; /* Transmit Good Frames */
uint32_t sc_tx_maxcol; /* Transmit Maximum Collisions errors */
uint32_t sc_tx_latecol; /* Transmit Late Collisions errors */
uint32_t sc_tx_underrun; /* Transmit Underrun errors */
uint32_t sc_tx_crs; /* Transmit Lost Carrier Sense */
uint32_t sc_tx_defered; /* Transmit Defered */
uint32_t sc_tx_scol; /* Transmit Single Collision */
uint32_t sc_tx_mcol; /* Transmit Multiple Collisions */
uint32_t sc_tx_totcol; /* Transmit Total Collisions */
uint32_t sc_rx_good; /* Receive Good Frames */
uint32_t sc_rx_crc; /* Receive CRC errors */
uint32_t sc_rx_align; /* Receive Alignment errors */
uint32_t sc_rx_resource; /* Receive Resource errors */
uint32_t sc_rx_overrun; /* Receive Overrun errors */
uint32_t sc_rx_cd; /* Receive Collision Detect errors */
uint32_t sc_rx_short; /* Receive Short Frame errors */
/* Short form ends here. The magic number will
* be stored in the next field.
*/
u32_t sc_tx_fcp; /* Transmit Flow Control Pause */
u32_t sc_rx_fcp; /* Receive Flow Control Pause */
u32_t sc_rx_fcu; /* Receive Flow Control Unsupported */
uint32_t sc_tx_fcp; /* Transmit Flow Control Pause */
uint32_t sc_rx_fcp; /* Receive Flow Control Pause */
uint32_t sc_rx_fcu; /* Receive Flow Control Unsupported */
/* Longer form (82558 and later) ends here.
* The magic number will be stored in the
* next field.
*/
u32_t sc_tx_tco; /* Transmit TCO frames */
u32_t sc_rx_tco; /* Receive TCO frames */
u32_t sc_magic; /* Dump of counters completed */
uint32_t sc_tx_tco; /* Transmit TCO frames */
uint32_t sc_rx_tco; /* Receive TCO frames */
uint32_t sc_magic; /* Dump of counters completed */
};
#define SCM_DSC 0x0000A005 /* Magic for SC_CU_DUMP_SC command */
@@ -502,8 +502,8 @@ struct rfd
{
uint16_t rfd_status;
uint16_t rfd_command;
u32_t rfd_linkaddr;
u32_t rfd_reserved;
uint32_t rfd_linkaddr;
uint32_t rfd_reserved;
uint16_t rfd_res;
uint16_t rfd_size;
uint8_t rfd_buf[NDEV_ETH_PACKET_MAX_TAGGED];

22
minix/drivers/net/ip1000/io.h
View File

@@ -6,8 +6,8 @@
#include "ip1000.h"
/* I/O function */
static uint8_t my_inb(u32_t port) {
u32_t value;
static uint8_t my_inb(uint32_t port) {
uint32_t value;
int r;
#ifdef DMA_BASE_IOMAP
value = *(volatile uint8_t *)(port);
@@ -19,8 +19,8 @@ static uint8_t my_inb(u32_t port) {
}
#define ndr_in8(port, offset) (my_inb((port) + (offset)))
static uint16_t my_inw(u32_t port) {
u32_t value;
static uint16_t my_inw(uint32_t port) {
uint32_t value;
int r;
#ifdef DMA_BASE_IOMAP
value = *(volatile uint16_t *)(port);
@@ -32,11 +32,11 @@ static uint16_t my_inw(u32_t port) {
}
#define ndr_in16(port, offset) (my_inw((port) + (offset)))
static u32_t my_inl(u32_t port) {
u32_t value;
static uint32_t my_inl(uint32_t port) {
uint32_t value;
int r;
#ifdef DMA_BASE_IOMAP
value = *(volatile u32_t *)(port);
value = *(volatile uint32_t *)(port);
#else
if ((r = sys_inl(port, &value)) != OK)
printf("NDR: sys_inl failed: %d\n", r);
@@ -45,7 +45,7 @@ static u32_t my_inl(u32_t port) {
}
#define ndr_in32(port, offset) (my_inl((port) + (offset)))
static void my_outb(u32_t port, u32_t value) {
static void my_outb(uint32_t port, uint32_t value) {
int r;
#ifdef DMA_BASE_IOMAP
*(volatile uint8_t *)(port) = value;
@@ -57,7 +57,7 @@ static void my_outb(u32_t port, u32_t value) {
#define ndr_out8(port, offset, value) \
(my_outb(((port) + (offset)), (value)))
static void my_outw(u32_t port, u32_t value) {
static void my_outw(uint32_t port, uint32_t value) {
int r;
#ifdef DMA_BASE_IOMAP
*(volatile uint16_t *)(port) = value;
@@ -69,10 +69,10 @@ static void my_outw(u32_t port, u32_t value) {
#define ndr_out16(port, offset, value) \
(my_outw(((port) + (offset)), (value)))
static void my_outl(u32_t port, u32_t value) {
static void my_outl(uint32_t port, uint32_t value) {
int r;
#ifdef DMA_BASE_IOMAP
*(volatile u32_t *)(port) = value;
*(volatile uint32_t *)(port) = value;
#else
if ((r = sys_outl(port, value)) != OK)
printf("NDR: sys_outl failed: %d\n", r);

110
minix/drivers/net/ip1000/ip1000.c
View File

@@ -29,34 +29,34 @@ static void dev_handler(NDR_driver *pdev);
static void dev_check_ints(NDR_driver *pdev);
/* developer interface */
static int dev_real_reset(u32_t *base);
static int dev_init_io(u32_t *base);
static int dev_init_mii(u32_t *base);
static void dev_intr_control(u32_t *base, int flag);
static void dev_rx_tx_control(u32_t *base, int flag);
static void dev_get_addr(u32_t *base, uint8_t *pa);
static int dev_check_link(u32_t *base);
static void dev_set_rec_mode(u32_t *base, int mode);
static void dev_start_tx(u32_t *base);
static u32_t dev_read_clear_intr_status(u32_t *base);
static int dev_real_reset(uint32_t *base);
static int dev_init_io(uint32_t *base);
static int dev_init_mii(uint32_t *base);
static void dev_intr_control(uint32_t *base, int flag);
static void dev_rx_tx_control(uint32_t *base, int flag);
static void dev_get_addr(uint32_t *base, uint8_t *pa);
static int dev_check_link(uint32_t *base);
static void dev_set_rec_mode(uint32_t *base, int mode);
static void dev_start_tx(uint32_t *base);
static uint32_t dev_read_clear_intr_status(uint32_t *base);
static void dev_init_rx_desc(NDR_desc *desc_start, int index, size_t buf_size,
phys_bytes buf_dma, int max_desc_num, phys_bytes desc_dma_start);
static void dev_init_tx_desc(NDR_desc *desc_start, int index, size_t buf_size,
phys_bytes buf_dma, int max_desc_num, phys_bytes desc_dma_start);
static void dev_set_desc_reg(u32_t *base, phys_bytes rx_addr,
static void dev_set_desc_reg(uint32_t *base, phys_bytes rx_addr,
phys_bytes tx_addr);
static int dev_rx_ok_desc(u32_t *base, NDR_desc *desc, int index);
static int dev_rx_len_desc(u32_t *base, NDR_desc *desc, int index);
static void dev_set_rx_desc_done(u32_t *base, NDR_desc *desc, int index);
static void dev_set_tx_desc_prepare(u32_t *base, NDR_desc *desc, int index,
static int dev_rx_ok_desc(uint32_t *base, NDR_desc *desc, int index);
static int dev_rx_len_desc(uint32_t *base, NDR_desc *desc, int index);
static void dev_set_rx_desc_done(uint32_t *base, NDR_desc *desc, int index);
static void dev_set_tx_desc_prepare(uint32_t *base, NDR_desc *desc, int index,
size_t data_size);
static int dev_tx_ok_desc(u32_t *base, NDR_desc *desc, int index);
static void dev_set_tx_desc_done(u32_t *base, NDR_desc *desc, int index);
static int dev_tx_ok_desc(uint32_t *base, NDR_desc *desc, int index);
static void dev_set_tx_desc_done(uint32_t *base, NDR_desc *desc, int index);
/* ======= Developer implemented function ======= */
/* ====== Self-defined function ======*/
static uint16_t read_eeprom(u32_t base, int addr) {
u32_t ret, data, val;
static uint16_t read_eeprom(uint32_t base, int addr) {
uint32_t ret, data, val;
int i;
val = EC_READ | (addr & 0xff);
@@ -74,9 +74,9 @@ static uint16_t read_eeprom(u32_t base, int addr) {
return ret;
}
static uint16_t read_phy_reg(u32_t base, int phy_addr, int phy_reg) {
static uint16_t read_phy_reg(uint32_t base, int phy_addr, int phy_reg) {
int i, j, fieldlen[8];
u32_t field[8];
uint32_t field[8];
uint8_t data, polar;
field[0] = 0xffffffff; fieldlen[0] = 32;
@@ -127,9 +127,9 @@ static uint16_t read_phy_reg(u32_t base, int phy_addr, int phy_reg) {
return field[6];
}
static void write_phy_reg(u32_t base, int phy_addr, int phy_reg, uint16_t val) {
static void write_phy_reg(uint32_t base, int phy_addr, int phy_reg, uint16_t val) {
int i, j, fieldlen[8];
u32_t field[8];
uint32_t field[8];
uint8_t data, polar;
field[0] = 0xffffffff; fieldlen[0] = 32;
@@ -165,8 +165,8 @@ static void write_phy_reg(u32_t base, int phy_addr, int phy_reg, uint16_t val) {
/* ====== Developer interface ======*/
/* Real hardware reset (### RESET_HARDWARE_CAN_FAIL ###)
* -- Return OK means success, Others means failure */
static int dev_real_reset(u32_t *base) {
u32_t data, base0 = base[0];
static int dev_real_reset(uint32_t *base) {
uint32_t data, base0 = base[0];
data = ndr_in32(base0, REG_ASIC_CTRL);
ndr_out32(base0, REG_ASIC_CTRL, data | AC_RESET_ALL);
micro_delay(5000);
@@ -177,8 +177,8 @@ static int dev_real_reset(u32_t *base) {
/* Intialize other hardware I/O registers (### INIT_HARDWARE_IO_CAN_FAIL ###)
* -- Return OK means success, Others means failure */
static int dev_init_io(u32_t *base) {
u32_t mac_ctrl, physet, mode0, mode1, base0 = base[0];
static int dev_init_io(uint32_t *base) {
uint32_t mac_ctrl, physet, mode0, mode1, base0 = base[0];
mode0 = read_eeprom(base0, 6);
mode1 = ndr_in16(base0, REG_ASIC_CTRL);
mode1 &= ~(AC_LED_MODE_B1 | AC_LED_MODE | AC_LED_SPEED);
@@ -210,12 +210,12 @@ static int dev_init_io(u32_t *base) {
/* Intialize MII interface (### MII_INIT_CAN_FAIL ###)
* -- Return OK means success, Others means failure */
static int dev_init_mii(u32_t *base) {
static int dev_init_mii(uint32_t *base) {
int i, phyaddr;
uint8_t revision;
uint16_t phyctrl, cr1000, length, address, value;
uint16_t *param;
u32_t status, base0 = base[0];
uint32_t status, base0 = base[0];
for (i = 0; i < 32; i++) {
phyaddr = (i + 0x01) % 32;
@@ -259,8 +259,8 @@ static int dev_init_mii(u32_t *base) {
}
/* Enable or disable interrupt (### INTR_ENABLE_DISABLE ###) */
static void dev_intr_control(u32_t *base, int flag) {
u32_t base0 = base[0];
static void dev_intr_control(uint32_t *base, int flag) {
uint32_t base0 = base[0];
if (flag == INTR_ENABLE)
ndr_out16(base0, REG_IMR, CMD_INTR_ENABLE);
else if (flag == INTR_DISABLE)
@@ -268,8 +268,8 @@ static void dev_intr_control(u32_t *base, int flag) {
}
/* Enable or disable Rx/Tx (### RX_TX_ENABLE_DISABLE ###) */
static void dev_rx_tx_control(u32_t *base, int flag) {
u32_t data, base0 = base[0];
static void dev_rx_tx_control(uint32_t *base, int flag) {
uint32_t data, base0 = base[0];
data = ndr_in32(base0, REG_MAC_CTRL);
if (flag == RX_TX_ENABLE)
ndr_out32(base0, REG_MAC_CTRL, data | (MC_RX_ENABLE | MC_TX_ENABLE));
@@ -280,8 +280,8 @@ static void dev_rx_tx_control(u32_t *base, int flag) {
}
/* Get MAC address to the array 'pa' (### GET_MAC_ADDR ###) */
static void dev_get_addr(u32_t *base, uint8_t *pa) {
u32_t i, sta_addr[3], base0 = base[0];
static void dev_get_addr(uint32_t *base, uint8_t *pa) {
uint32_t i, sta_addr[3], base0 = base[0];
for (i = 0; i < 3; i++) {
sta_addr[i] = read_eeprom(base0, 16 + i);
ndr_out16(base0, (REG_STA_ADDR0 + i * 2), sta_addr[i]);
@@ -296,8 +296,8 @@ static void dev_get_addr(u32_t *base, uint8_t *pa) {
/* Check link status (### CHECK_LINK ###)
* -- Return LINK_UP or LINK_DOWN */
static int dev_check_link(u32_t *base) {
u32_t phy_ctrl, mac_ctrl, base0 = base[0];
static int dev_check_link(uint32_t *base) {
uint32_t phy_ctrl, mac_ctrl, base0 = base[0];
int ret;
char speed[20], duplex[20];
@@ -335,8 +335,8 @@ static int dev_check_link(u32_t *base) {
}
/* Set driver receive mode (### SET_REC_MODE ###) */
static void dev_set_rec_mode(u32_t *base, int mode) {
u32_t data, base0 = base[0];
static void dev_set_rec_mode(uint32_t *base, int mode) {
uint32_t data, base0 = base[0];
data = ndr_in8(base0, REG_RCR);
data &= ~(CMD_RCR_UNICAST | CMD_RCR_MULTICAST | CMD_RCR_BROADCAST);
if (mode & NDEV_MODE_PROMISC)
@@ -350,14 +350,14 @@ static void dev_set_rec_mode(u32_t *base, int mode) {
}
/* Start Tx channel (### START_TX_CHANNEL ###) */
static void dev_start_tx(u32_t *base) {
u32_t base0 = base[0];
static void dev_start_tx(uint32_t *base) {
uint32_t base0 = base[0];
ndr_out32(base0, REG_DMA_CTRL, CMD_TX_START);
}
/* Read and clear interrupt (### READ_CLEAR_INTR_STS ###) */
static u32_t dev_read_clear_intr_status(u32_t *base) {
u32_t data, base0 = base[0];
static uint32_t dev_read_clear_intr_status(uint32_t *base) {
uint32_t data, base0 = base[0];
data = ndr_in16(base0, REG_ISR);
ndr_out16(base0, REG_ISR, 0);
return data;
@@ -390,9 +390,9 @@ static void dev_init_tx_desc(NDR_desc *desc_start, int index, size_t buf_size,
}
/* Set Rx/Tx descriptor address into device register (### SET_DESC_REG ###) */
static void dev_set_desc_reg(u32_t *base, phys_bytes rx_addr,
static void dev_set_desc_reg(uint32_t *base, phys_bytes rx_addr,
phys_bytes tx_addr) {
u32_t base0 = base[0];
uint32_t base0 = base[0];
ndr_out32(base0, REG_RX_DESC_BASEL, rx_addr);
ndr_out32(base0, REG_RX_DESC_BASEU, 0);
ndr_out32(base0, REG_TX_DESC_BASEL, tx_addr);
@@ -402,7 +402,7 @@ static void dev_set_desc_reg(u32_t *base, phys_bytes rx_addr,
/* Check whether Rx is OK from Rx descriptor (### CHECK_RX_OK_FROM_DESC ###)
* -- Current buffer number is index
* -- Return RX_OK or RX_SUSPEND or RX_ERROR */
static int dev_rx_ok_desc(u32_t *base, NDR_desc *desc, int index) {
static int dev_rx_ok_desc(uint32_t *base, NDR_desc *desc, int index) {
if (desc->status & RFS_RFD_DONE) {
if (desc->status & RFS_ERROR)
return RX_ERROR;
@@ -415,7 +415,7 @@ static int dev_rx_ok_desc(u32_t *base, NDR_desc *desc, int index) {
/* Get length from Rx descriptor (### GET_RX_LENGTH_FROM_DESC ###)
* -- Current buffer number is index
* -- Return the length */
static int dev_rx_len_desc(u32_t *base, NDR_desc *desc, int index) {
static int dev_rx_len_desc(uint32_t *base, NDR_desc *desc, int index) {
int totlen;
totlen = (int)(desc->status & RFS_FRAME_LEN);
return totlen;
@@ -423,13 +423,13 @@ static int dev_rx_len_desc(u32_t *base, NDR_desc *desc, int index) {
/* Set Rx descriptor after Rx done (### SET_RX_DESC_DONE ###)
* -- Current buffer number is index */
static void dev_set_rx_desc_done(u32_t *base, NDR_desc *desc, int index) {
static void dev_set_rx_desc_done(uint32_t *base, NDR_desc *desc, int index) {
desc->status = 0;
}
/* Set Tx descriptor to prepare transmitting (### SET_TX_DESC_PREPARE)
* -- Current buffer number is index */
static void dev_set_tx_desc_prepare(u32_t *base, NDR_desc *desc, int index,
static void dev_set_tx_desc_prepare(uint32_t *base, NDR_desc *desc, int index,
size_t data_size) {
desc->status = TFS_TFD_DONE;
desc->status |= (u64_t)(TFS_WORD_ALIGN | (TFS_FRAMEID & index)
@@ -442,7 +442,7 @@ static void dev_set_tx_desc_prepare(u32_t *base, NDR_desc *desc, int index,
/* Check whether Tx is OK from Tx descriptor (### CHECK_TX_OK_FROM_DESC ###)
* -- Current buffer number is index
* -- Return TX_OK or TX_SUSPEND or TX_ERROR */
static int dev_tx_ok_desc(u32_t *base, NDR_desc *desc, int index) {
static int dev_tx_ok_desc(uint32_t *base, NDR_desc *desc, int index) {
if (desc->status & TFS_TFD_DONE)
return TX_OK;
return TX_SUSPEND;
@@ -450,7 +450,7 @@ static int dev_tx_ok_desc(u32_t *base, NDR_desc *desc, int index) {
/* Set Tx descriptor after Tx done (### SET_TX_DESC_DONE ###)
* -- Current buffer number is index */
static void dev_set_tx_desc_done(u32_t *base, NDR_desc *desc, int index) {
static void dev_set_tx_desc_done(uint32_t *base, NDR_desc *desc, int index) {
desc->status = 0;
}
@@ -552,7 +552,7 @@ NDR_set_mode(unsigned int mode, const netdriver_addr_t * mcast_list __unused,
/* Receive data */
static ssize_t NDR_recv(struct netdriver_data *data, size_t max) {
NDR_driver *pdev = &g_driver;
u32_t totlen, packlen;
uint32_t totlen, packlen;
int index, ret, offset = 0;
NDR_desc *desc;
@@ -654,7 +654,7 @@ static void NDR_intr(unsigned int mask) {
static int dev_probe(NDR_driver *pdev, int instance) {
int devind, ioflag, i;
uint16_t cr, vid, did;
u32_t bar, size, base;
uint32_t bar, size, base;
uint8_t irq, rev;
uint8_t *reg;
@@ -689,7 +689,7 @@ static int dev_probe(NDR_driver *pdev, int instance) {
printf("NDR: Fail to map hardware registers from PCI\n");
return -EIO;
}
pdev->base[i] = (u32_t)reg;
pdev->base[i] = (uint32_t)reg;
}
#else
for (i = 0; i < 6; i++)
@@ -899,7 +899,7 @@ static int dev_init_buf(NDR_driver *pdev) {
/* Real handler interrupt */
static void dev_handler(NDR_driver *pdev) {
u32_t intr_status;
uint32_t intr_status;
int tx_head, tx_tail, index, flag = 0, ret;
NDR_desc *desc;

4
minix/drivers/net/ip1000/ip1000.h
View File

@@ -147,8 +147,8 @@ typedef struct NDR_desc {
typedef struct NDR_driver {
char *dev_name; /* Device name */
uint16_t vid, did; /* Vendor and device ID */
u32_t devind; /* Device index */
u32_t base[6]; /* Base address */
uint32_t devind; /* Device index */
uint32_t base[6]; /* Base address */
char irq; /* IRQ number */
char revision; /* Revision ID */

58
minix/drivers/net/lan8710a/lan8710a.c
View File

@@ -25,13 +25,13 @@ static void lan8710a_init_mdio(void);
static int lan8710a_init_hw(netdriver_addr_t *addr, unsigned int instance);
static void lan8710a_reset_hw(void);
static void lan8710a_phy_write(u32_t reg, u32_t value);
static u32_t lan8710a_phy_read(u32_t reg);
static void lan8710a_phy_write(uint32_t reg, uint32_t value);
static uint32_t lan8710a_phy_read(uint32_t reg);
static u32_t lan8710a_reg_read(volatile u32_t *reg);
static void lan8710a_reg_write(volatile u32_t *reg, u32_t value);
static void lan8710a_reg_set(volatile u32_t *reg, u32_t value);
static void lan8710a_reg_unset(volatile u32_t *reg, u32_t value);
static uint32_t lan8710a_reg_read(volatile uint32_t *reg);
static void lan8710a_reg_write(volatile uint32_t *reg, uint32_t value);
static void lan8710a_reg_set(volatile uint32_t *reg, uint32_t value);
static void lan8710a_reg_unset(volatile uint32_t *reg, uint32_t value);
/* Local variables */
static lan8710a_t lan8710a_state;
@@ -111,12 +111,12 @@ lan8710a_enable_interrupt(int interrupt)
static void
lan8710a_intr(unsigned int mask)
{
u32_t dma_status;
uint32_t dma_status;
/* Check the card for interrupt reason(s). */
u32_t rx_stat = lan8710a_reg_read(CPSW_WR_C0_RX_STAT);
u32_t tx_stat = lan8710a_reg_read(CPSW_WR_C0_TX_STAT);
u32_t cp;
uint32_t rx_stat = lan8710a_reg_read(CPSW_WR_C0_RX_STAT);
uint32_t tx_stat = lan8710a_reg_read(CPSW_WR_C0_TX_STAT);
uint32_t cp;
/* Handle interrupts. */
if (rx_stat) {
@@ -361,7 +361,7 @@ lan8710a_dma_config_tx(uint8_t desc_idx)
/* Setting HDP */
phys_addr = lan8710a_state.tx_desc_phy +
(desc_idx * sizeof(lan8710a_desc_t));
lan8710a_reg_write(CPDMA_STRAM_TX_HDP(i), (u32_t)phys_addr);
lan8710a_reg_write(CPDMA_STRAM_TX_HDP(i), (uint32_t)phys_addr);
}
/*============================================================================*
@@ -401,7 +401,7 @@ lan8710a_dma_reset_init(void)
* channel's Rx DMA state.
*/
lan8710a_reg_write(CPDMA_STRAM_RX_HDP(0),
(u32_t)lan8710a_state.rx_desc_phy);
(uint32_t)lan8710a_state.rx_desc_phy);
lan8710a_state.rx_desc_idx = 0;
lan8710a_state.tx_desc_idx = 0;
@@ -429,11 +429,11 @@ lan8710a_init_desc(void)
memset(p_rx_desc, 0x0, sizeof(lan8710a_desc_t));
p_rx_desc->pkt_len_flags = LAN8710A_DESC_FLAG_OWN;
p_rx_desc->buffer_length_off = LAN8710A_IOBUF_SIZE;
p_rx_desc->buffer_pointer = (u32_t)(buf_phys_addr +
p_rx_desc->buffer_pointer = (uint32_t)(buf_phys_addr +
(i * LAN8710A_IOBUF_SIZE));
p_rx_desc->next_pointer =
(u32_t)((i == (LAN8710A_NUM_RX_DESC - 1)) ?
(uint32_t)((i == (LAN8710A_NUM_RX_DESC - 1)) ?
(lan8710a_state.rx_desc_phy) :
(lan8710a_state.rx_desc_phy +
((i + 1) * sizeof(lan8710a_desc_t))));
@@ -448,7 +448,7 @@ lan8710a_init_desc(void)
for (i = 0; i < LAN8710A_NUM_TX_DESC; i++) {
p_tx_desc = &(lan8710a_state.tx_desc[i]);
memset(p_tx_desc, 0x0, sizeof(lan8710a_desc_t));
p_tx_desc->buffer_pointer = (u32_t)(buf_phys_addr +
p_tx_desc->buffer_pointer = (uint32_t)(buf_phys_addr +
(i * LAN8710A_IOBUF_SIZE));
}
lan8710a_state.rx_desc_idx = 0;
@@ -674,7 +674,7 @@ static void
lan8710a_init_mdio(void)
{
uint16_t address = 0;
u32_t r;
uint32_t r;
/* Clearing MDIOCONTROL register */
lan8710a_reg_write(MDIOCONTROL, 0);
@@ -756,7 +756,7 @@ lan8710a_recv(struct netdriver_data * data, size_t max)
{
lan8710a_t *e = &lan8710a_state;
lan8710a_desc_t *p_rx_desc;
u32_t flags;
uint32_t flags;
uint8_t *buf;
size_t off, size, chunk;
@@ -836,7 +836,7 @@ lan8710a_recv(struct netdriver_data * data, size_t max)
* lan8710a_phy_write *
*============================================================================*/
static void
lan8710a_phy_write(u32_t reg, u32_t value)
lan8710a_phy_write(uint32_t reg, uint32_t value)
{
if (!(lan8710a_reg_read(MDIOUSERACCESS0) & MDIO_GO)) {
/* Clearing MDIOUSERACCESS0 register */
@@ -859,10 +859,10 @@ lan8710a_phy_write(u32_t reg, u32_t value)
/*============================================================================*
* lan8710a_phy_read *
*============================================================================*/
static u32_t
lan8710a_phy_read(u32_t reg)
static uint32_t
lan8710a_phy_read(uint32_t reg)
{
u32_t value = 0xFFFFFFFF;
uint32_t value = 0xFFFFFFFF;
if (!(lan8710a_reg_read(MDIOUSERACCESS0) & MDIO_GO)) {
/* Clearing MDIOUSERACCESS0 register */
@@ -902,10 +902,10 @@ lan8710a_reset_hw(void)
/*============================================================================*
* lan8710a_reg_read *
*============================================================================*/
static u32_t
lan8710a_reg_read(volatile u32_t *reg)
static uint32_t
lan8710a_reg_read(volatile uint32_t *reg)
{
u32_t value;
uint32_t value;
/* Read from memory mapped register. */
value = *reg;
@@ -918,7 +918,7 @@ lan8710a_reg_read(volatile u32_t *reg)
* lan8710a_reg_write *
*============================================================================*/
static void
lan8710a_reg_write(volatile u32_t *reg, u32_t value)
lan8710a_reg_write(volatile uint32_t *reg, uint32_t value)
{
/* Write to memory mapped register. */
*reg = value;
@@ -928,9 +928,9 @@ lan8710a_reg_write(volatile u32_t *reg, u32_t value)
* lan8710a_reg_set *
*============================================================================*/
static void
lan8710a_reg_set(volatile u32_t *reg, u32_t value)
lan8710a_reg_set(volatile uint32_t *reg, uint32_t value)
{
u32_t data;
uint32_t data;
/* First read the current value. */
data = lan8710a_reg_read(reg);
@@ -943,9 +943,9 @@ lan8710a_reg_set(volatile u32_t *reg, u32_t value)
* lan8710a_reg_unset *
*============================================================================*/
static void
lan8710a_reg_unset(volatile u32_t *reg, u32_t value)
lan8710a_reg_unset(volatile uint32_t *reg, uint32_t value)
{
u32_t data;
uint32_t data;
/* First read the current value. */
data = lan8710a_reg_read(reg);

10
minix/drivers/net/lan8710a/lan8710a.h
View File

@@ -54,10 +54,10 @@
typedef struct lan8710a_desc_t
{
u32_t next_pointer;
u32_t buffer_pointer;
u32_t buffer_length_off;
u32_t pkt_len_flags;
uint32_t next_pointer;
uint32_t buffer_pointer;
uint32_t buffer_length_off;
uint32_t pkt_len_flags;
} lan8710a_desc_t;
typedef struct lan8710a_t
@@ -69,7 +69,7 @@ typedef struct lan8710a_t
int irq_rx_hook; /* Rx interrupt Request Vector Hook. */
int irq_tx_hook; /* Tx interrupt Request Vector Hook. */
uint8_t *regs;
u32_t phy_address;
uint32_t phy_address;
uint8_t *p_rx_buf; /* pointer to the buffer with receive frames */
uint8_t *p_tx_buf; /* pointer to the buffer with transmit frames */

168
minix/drivers/net/lan8710a/lan8710a_reg.h
View File

@@ -10,20 +10,20 @@
/* MDIO Registers */
#define MDIO_BASE_ADDR (0x4A101000)
#define MDIOVER ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x00))
#define MDIOCONTROL ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x04))
#define MDIOALIVE ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x08))
#define MDIOLINK ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x0C))
#define MDIOLINKINTRAW ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x10))
#define MDIOLINKINTMASKED ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x14))
#define MDIOUSERINTRAW ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x20))
#define MDIOUSERINTMASKED ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x24))
#define MDIOUSERINTMASKSET ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x28))
#define MDIOUSERINTMASKCLR ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x2C))
#define MDIOUSERACCESS0 ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x80))
#define MDIOUSERPHYSEL0 ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x84))
#define MDIOUSERACCESS1 ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x88))
#define MDIOUSERPHYSEL1 ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x8C))
#define MDIOVER ((volatile uint32_t *)( lan8710a_state.regs_mdio + 0x00))
#define MDIOCONTROL ((volatile uint32_t *)( lan8710a_state.regs_mdio + 0x04))
#define MDIOALIVE ((volatile uint32_t *)( lan8710a_state.regs_mdio + 0x08))
#define MDIOLINK ((volatile uint32_t *)( lan8710a_state.regs_mdio + 0x0C))
#define MDIOLINKINTRAW ((volatile uint32_t *)( lan8710a_state.regs_mdio + 0x10))
#define MDIOLINKINTMASKED ((volatile uint32_t *)( lan8710a_state.regs_mdio + 0x14))
#define MDIOUSERINTRAW ((volatile uint32_t *)( lan8710a_state.regs_mdio + 0x20))
#define MDIOUSERINTMASKED ((volatile uint32_t *)( lan8710a_state.regs_mdio + 0x24))
#define MDIOUSERINTMASKSET ((volatile uint32_t *)( lan8710a_state.regs_mdio + 0x28))
#define MDIOUSERINTMASKCLR ((volatile uint32_t *)( lan8710a_state.regs_mdio + 0x2C))
#define MDIOUSERACCESS0 ((volatile uint32_t *)( lan8710a_state.regs_mdio + 0x80))
#define MDIOUSERPHYSEL0 ((volatile uint32_t *)( lan8710a_state.regs_mdio + 0x84))
#define MDIOUSERACCESS1 ((volatile uint32_t *)( lan8710a_state.regs_mdio + 0x88))
#define MDIOUSERPHYSEL1 ((volatile uint32_t *)( lan8710a_state.regs_mdio + 0x8C))
#define MDIO_PREAMBLE (1 << 20)
#define MDCLK_DIVIDER (0x255)
@@ -38,26 +38,26 @@
/* CONTROL MODULE Registers */
#define CTRL_MOD_BASE_ADR (0x44E10000)
#define CTRL_MAC_ID0_LO ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x630))
#define CTRL_MAC_ID0_HI ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x634))
#define GMII_SEL ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x650))
#define CONF_MII1_COL ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x908))
#define CONF_MII1_CRS ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x90C))
#define CONF_MII1_RX_ER ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x910))
#define CONF_MII1_TX_EN ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x914))
#define CONF_MII1_RX_DV ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x918))
#define CONF_MII1_TXD3 ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x91C))
#define CONF_MII1_TXD2 ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x920))
#define CONF_MII1_TXD1 ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x924))
#define CONF_MII1_TXD0 ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x928))
#define CONF_MII1_TX_CLK ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x92C))
#define CONF_MII1_RX_CLK ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x930))
#define CONF_MII1_RXD3 ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x934))
#define CONF_MII1_RXD2 ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x938))
#define CONF_MII1_RXD1 ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x93C))
#define CONF_MII1_RXD0 ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x940))
#define CONF_MDIO ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x948))
#define CONF_MDC ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x94C))
#define CTRL_MAC_ID0_LO ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x630))
#define CTRL_MAC_ID0_HI ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x634))
#define GMII_SEL ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x650))
#define CONF_MII1_COL ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x908))
#define CONF_MII1_CRS ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x90C))
#define CONF_MII1_RX_ER ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x910))
#define CONF_MII1_TX_EN ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x914))
#define CONF_MII1_RX_DV ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x918))
#define CONF_MII1_TXD3 ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x91C))
#define CONF_MII1_TXD2 ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x920))
#define CONF_MII1_TXD1 ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x924))
#define CONF_MII1_TXD0 ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x928))
#define CONF_MII1_TX_CLK ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x92C))
#define CONF_MII1_RX_CLK ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x930))
#define CONF_MII1_RXD3 ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x934))
#define CONF_MII1_RXD2 ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x938))
#define CONF_MII1_RXD1 ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x93C))
#define CONF_MII1_RXD0 ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x940))
#define CONF_MDIO ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x948))
#define CONF_MDC ((volatile uint32_t *)( lan8710a_state.regs_ctrl_mod + 0x94C))
#define CONF_MOD_SLEW_CTRL (1 << 6)
#define CONF_MOD_RX_ACTIVE (1 << 5)
@@ -73,16 +73,16 @@
/* CLOCK MODULE Registers */
#define CM_PER_BASE_ADR (0x44E00000)
#define CM_PER_CPSW_CLKSTCTRL ((volatile u32_t *)( lan8710a_state.regs_cp_per + 0x144))
#define CM_PER_CPSW_CLKSTCTRL ((volatile uint32_t *)( lan8710a_state.regs_cp_per + 0x144))
#define CM_PER_CPSW_CLKSTCTRL_BIT1 (1 << 1)
#define CM_PER_CPSW_CLKSTCTRL_BIT0 (1 << 0)
/* CPSW_ALE Registers */
#define CPSW_ALE_BASE_ADR (0x4A100D00)
#define CPSW_ALE_CONTROL ((volatile u32_t *)( lan8710a_state.regs_cpsw_ale + 0x08))
#define CPSW_ALE_PORTCTL0 ((volatile u32_t *)( lan8710a_state.regs_cpsw_ale + 0x40))
#define CPSW_ALE_PORTCTL1 ((volatile u32_t *)( lan8710a_state.regs_cpsw_ale + 0x44))
#define CPSW_ALE_CONTROL ((volatile uint32_t *)( lan8710a_state.regs_cpsw_ale + 0x08))
#define CPSW_ALE_PORTCTL0 ((volatile uint32_t *)( lan8710a_state.regs_cpsw_ale + 0x40))
#define CPSW_ALE_PORTCTL1 ((volatile uint32_t *)( lan8710a_state.regs_cpsw_ale + 0x44))
#define CPSW_ALE_ENABLE (1 << 31)
#define CPSW_ALE_BYPASS (1 << 4)
@@ -90,13 +90,13 @@
/* CPSW_SL Registers */
#define CPSW_SL_BASE_ADR (0x4A100D80)
#define CPSW_SL_MACCONTROL(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x04))
#define CPSW_SL_SOFT_RESET(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x0C))
#define CPSW_SL_RX_MAXLEN(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x10))
#define CPSW_SL_BOFFTEST(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x14))
#define CPSW_SL_EMCONTROL(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x20))
#define CPSW_SL_RX_PRI_MAP(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x24))
#define CPSW_SL_TX_GAP(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x28))
#define CPSW_SL_MACCONTROL(x) ((volatile uint32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x04))
#define CPSW_SL_SOFT_RESET(x) ((volatile uint32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x0C))
#define CPSW_SL_RX_MAXLEN(x) ((volatile uint32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x10))
#define CPSW_SL_BOFFTEST(x) ((volatile uint32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x14))
#define CPSW_SL_EMCONTROL(x) ((volatile uint32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x20))
#define CPSW_SL_RX_PRI_MAP(x) ((volatile uint32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x24))
#define CPSW_SL_TX_GAP(x) ((volatile uint32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x28))
#define CPSW_SL_GMII_EN (1 << 5)
#define CPSW_SL_FULLDUPLEX (1 << 0)
@@ -105,30 +105,30 @@
/* CPSW_STATS Registers */
#define CPSW_STATS_BASE_ADR (0x4A100900)
#define CPSW_STATS_MEM_LIMIT (0x90)
#define CPSW_STAT_RX_GOOD ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x00))
#define CPSW_STAT_RX_CRC_ERR ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x10))
#define CPSW_STAT_RX_AGNCD_ERR ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x14))
#define CPSW_STAT_RX_OVERSIZE ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x18))
#define CPSW_STAT_TX_GOOD ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x34))
#define CPSW_STAT_COLLISIONS ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x48))
#define CPSW_STAT_TX_UNDERRUN ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x5C))
#define CPSW_STAT_CARR_SENS_ERR ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x60))
#define CPSW_STAT_RX_OVERRUN ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x8C))
#define CPSW_STAT_RX_GOOD ((volatile uint32_t *)( lan8710a_state.regs_cpsw_stats + 0x00))
#define CPSW_STAT_RX_CRC_ERR ((volatile uint32_t *)( lan8710a_state.regs_cpsw_stats + 0x10))
#define CPSW_STAT_RX_AGNCD_ERR ((volatile uint32_t *)( lan8710a_state.regs_cpsw_stats + 0x14))
#define CPSW_STAT_RX_OVERSIZE ((volatile uint32_t *)( lan8710a_state.regs_cpsw_stats + 0x18))
#define CPSW_STAT_TX_GOOD ((volatile uint32_t *)( lan8710a_state.regs_cpsw_stats + 0x34))
#define CPSW_STAT_COLLISIONS ((volatile uint32_t *)( lan8710a_state.regs_cpsw_stats + 0x48))
#define CPSW_STAT_TX_UNDERRUN ((volatile uint32_t *)( lan8710a_state.regs_cpsw_stats + 0x5C))
#define CPSW_STAT_CARR_SENS_ERR ((volatile uint32_t *)( lan8710a_state.regs_cpsw_stats + 0x60))
#define CPSW_STAT_RX_OVERRUN ((volatile uint32_t *)( lan8710a_state.regs_cpsw_stats + 0x8C))
/* CPSW_CPDMA Registers */
#define CPSW_CPDMA_BASE_ADR (0x4A100800)
#define CPDMA_SOFT_RESET ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x1C))
#define CPDMA_TX_CONTROL ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x04))
#define CPDMA_RX_CONTROL ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x14))
#define CPDMA_CONTROL ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x20))
#define CPDMA_STATUS ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x24))
#define CPDMA_RX_BUFFER_OFFSET ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x28))
#define CPDMA_EMCONTROL ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x2C))
#define CPDMA_TX_INTMASK_SET ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x88))
#define CPDMA_TX_INTMASK_CLEAR ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x8C))
#define CPDMA_EOI_VECTOR ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x94))
#define CPDMA_RX_INTMASK_SET ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0xA8))
#define CPDMA_RX_INTMASK_CLEAR ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0xAC))
#define CPDMA_SOFT_RESET ((volatile uint32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x1C))
#define CPDMA_TX_CONTROL ((volatile uint32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x04))
#define CPDMA_RX_CONTROL ((volatile uint32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x14))
#define CPDMA_CONTROL ((volatile uint32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x20))
#define CPDMA_STATUS ((volatile uint32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x24))
#define CPDMA_RX_BUFFER_OFFSET ((volatile uint32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x28))
#define CPDMA_EMCONTROL ((volatile uint32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x2C))
#define CPDMA_TX_INTMASK_SET ((volatile uint32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x88))
#define CPDMA_TX_INTMASK_CLEAR ((volatile uint32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x8C))
#define CPDMA_EOI_VECTOR ((volatile uint32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x94))
#define CPDMA_RX_INTMASK_SET ((volatile uint32_t *)( lan8710a_state.regs_cpsw_cpdma + 0xA8))
#define CPDMA_RX_INTMASK_CLEAR ((volatile uint32_t *)( lan8710a_state.regs_cpsw_cpdma + 0xAC))
#define CPDMA_IDLE (1 << 31)
#define CPDMA_TX_RLIM (0xFF << 8)
@@ -147,9 +147,9 @@
/* CPSW_SS Registers */
#define CPSW_SS_BASE_ADR (0x4A100000)
#define CPSW_SS_SOFT_RESET ((volatile u32_t *)( lan8710a_state.regs_cpsw_ss + 0x08))
#define CPSW_SS_STAT_PORT_EN ((volatile u32_t *)( lan8710a_state.regs_cpsw_ss + 0x0C))
#define CPSW_SS_TX_START_WDS ((volatile u32_t *)( lan8710a_state.regs_cpsw_ss + 0x20))
#define CPSW_SS_SOFT_RESET ((volatile uint32_t *)( lan8710a_state.regs_cpsw_ss + 0x08))
#define CPSW_SS_STAT_PORT_EN ((volatile uint32_t *)( lan8710a_state.regs_cpsw_ss + 0x0C))
#define CPSW_SS_TX_START_WDS ((volatile uint32_t *)( lan8710a_state.regs_cpsw_ss + 0x20))
#define CPSW_P2_STAT_EN (1 << 2)
#define CPSW_P1_STAT_EN (1 << 1)
@@ -157,23 +157,23 @@
/* CPSW_WR Registers */
#define CPSW_WR_BASE_ADR (0x4A101200)
#define CPSW_WR_INT_CONTROL ((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x0C))
#define CPSW_WR_C0_RX_EN ((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x14))
#define CPSW_WR_C1_RX_EN ((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x24))
#define CPSW_WR_C2_RX_EN ((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x34))
#define CPSW_WR_C0_RX_STAT ((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x44))
#define CPSW_WR_C0_TX_EN ((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x18))
#define CPSW_WR_C0_TX_STAT ((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x48))
#define CPSW_WR_INT_CONTROL ((volatile uint32_t *)( lan8710a_state.regs_cpsw_wr + 0x0C))
#define CPSW_WR_C0_RX_EN ((volatile uint32_t *)( lan8710a_state.regs_cpsw_wr + 0x14))
#define CPSW_WR_C1_RX_EN ((volatile uint32_t *)( lan8710a_state.regs_cpsw_wr + 0x24))
#define CPSW_WR_C2_RX_EN ((volatile uint32_t *)( lan8710a_state.regs_cpsw_wr + 0x34))
#define CPSW_WR_C0_RX_STAT ((volatile uint32_t *)( lan8710a_state.regs_cpsw_wr + 0x44))
#define CPSW_WR_C0_TX_EN ((volatile uint32_t *)( lan8710a_state.regs_cpsw_wr + 0x18))
#define CPSW_WR_C0_TX_STAT ((volatile uint32_t *)( lan8710a_state.regs_cpsw_wr + 0x48))
#define CPSW_FIRST_CHAN_INT (1 << 0)
#define CPSW_ALL_CHAN_INT (0xFF << 0)
/* INTERRUPTION CONTROLLER Registers */
#define INTC_BASE_ADR (0x48200000)
#define INTC_SYSCONFIG ((volatile u32_t *)( lan8710a_state.regs_intc + 0x10))
#define INTC_IDLE ((volatile u32_t *)( lan8710a_state.regs_intc + 0x50))
#define INTC_MIR_CLEAR1 ((volatile u32_t *)( lan8710a_state.regs_intc + 0xA8))
#define INTC_ILR(x) ((volatile u32_t *)( lan8710a_state.regs_intc + 0x100 + 4*(x)))
#define INTC_SYSCONFIG ((volatile uint32_t *)( lan8710a_state.regs_intc + 0x10))
#define INTC_IDLE ((volatile uint32_t *)( lan8710a_state.regs_intc + 0x50))
#define INTC_MIR_CLEAR1 ((volatile uint32_t *)( lan8710a_state.regs_intc + 0xA8))
#define INTC_ILR(x) ((volatile uint32_t *)( lan8710a_state.regs_intc + 0x100 + 4*(x)))
#define INTC_AUTOIDLE (1 << 0)
#define INTC_FUNCIDLE (1 << 0)
@@ -184,10 +184,10 @@
/* DMA STATERAM Registers */
#define CPDMA_STRAM_BASE_ADR (0x4A100A00)
#define CPDMA_STRAM_TX_HDP(x) ((volatile u32_t *)( lan8710a_state.regs_cpdma_stram + 4*(x)))
#define CPDMA_STRAM_RX_HDP(x) ((volatile u32_t *)( lan8710a_state.regs_cpdma_stram + 0x20 + 4*(x)))
#define CPDMA_STRAM_TX_CP(x) ((volatile u32_t *)( lan8710a_state.regs_cpdma_stram + 0x40 + 4*(x)))
#define CPDMA_STRAM_RX_CP(x) ((volatile u32_t *)( lan8710a_state.regs_cpdma_stram + 0x60 + 4*(x)))
#define CPDMA_STRAM_TX_HDP(x) ((volatile uint32_t *)( lan8710a_state.regs_cpdma_stram + 4*(x)))
#define CPDMA_STRAM_RX_HDP(x) ((volatile uint32_t *)( lan8710a_state.regs_cpdma_stram + 0x20 + 4*(x)))
#define CPDMA_STRAM_TX_CP(x) ((volatile uint32_t *)( lan8710a_state.regs_cpdma_stram + 0x40 + 4*(x)))
#define CPDMA_STRAM_RX_CP(x) ((volatile uint32_t *)( lan8710a_state.regs_cpdma_stram + 0x60 + 4*(x)))
#define ALL_BITS (0xFFFFFFFF)

4
minix/drivers/net/lance/lance.c
View File

@@ -841,7 +841,7 @@ static void lance_init_hw(ether_card_t *ec, netdriver_addr_t *addr,
static uint8_t in_byte(port_t port)
{
int r;
u32_t value;
uint32_t value;
r= sys_inb(port, &value);
if (r != OK)
@@ -855,7 +855,7 @@ static uint8_t in_byte(port_t port)
static uint16_t in_word(port_t port)
{
int r;
u32_t value;
uint32_t value;
r= sys_inw(port, &value);
if (r != OK)

24
minix/drivers/net/rtl8139/rtl8139.c
View File

@@ -19,21 +19,21 @@
static re_t re_state;
static unsigned my_inb(uint16_t port) {
u32_t value;
uint32_t value;
int s;
if ((s=sys_inb(port, &value)) !=OK)
printf("RTL8139: warning, sys_inb failed: %d\n", s);
return value;
}
static unsigned my_inw(uint16_t port) {
u32_t value;
uint32_t value;
int s;
if ((s=sys_inw(port, &value)) !=OK)
printf("RTL8139: warning, sys_inw failed: %d\n", s);
return value;
}
static unsigned my_inl(uint16_t port) {
u32_t value;
uint32_t value;
int s;
if ((s=sys_inl(port, &value)) !=OK)
printf("RTL8139: warning, sys_inl failed: %d\n", s);
@@ -53,7 +53,7 @@ static void my_outw(uint16_t port, uint16_t value) {
if ((s=sys_outw(port, value)) !=OK)
printf("RTL8139: warning, sys_outw failed: %d\n", s);
}
static void my_outl(uint16_t port, u32_t value) {
static void my_outl(uint16_t port, uint32_t value) {
int s;
if ((s=sys_outl(port, value)) !=OK)
printf("RTL8139: warning, sys_outl failed: %d\n", s);
@@ -259,7 +259,7 @@ static int rl_probe(re_t *rep, unsigned int skip)
{
int r, devind;
uint16_t cr, vid, did;
u32_t bar;
uint32_t bar;
uint8_t ilr;
#if VERBOSE
const char *dname;
@@ -406,7 +406,7 @@ static void rl_init_hw(re_t *rep, netdriver_addr_t *addr,
static void rl_reset_hw(re_t *rep)
{
port_t port;
u32_t t;
uint32_t t;
phys_bytes bus_buf;
int i;
@@ -515,7 +515,7 @@ static void rl_set_hwaddr(const netdriver_addr_t *addr)
{
re_t *rep;
port_t port;
u32_t w;
uint32_t w;
int i;
rep = &re_state;
@@ -574,7 +574,7 @@ static void rl_confaddr(re_t *rep, netdriver_addr_t *addr,
static void rl_rec_mode(re_t *rep)
{
port_t port;
u32_t rcr;
uint32_t rcr;
port= rep->re_base_port;
rcr= rl_inl(port, RL_RCR);
@@ -599,7 +599,7 @@ static ssize_t rl_recv(struct netdriver_data *data, size_t max)
port_t port;
unsigned amount, totlen, packlen;
uint16_t d_start, d_end;
u32_t l, rxstat;
uint32_t l, rxstat;
re_t *rep;
rep= &re_state;
@@ -632,7 +632,7 @@ static ssize_t rl_recv(struct netdriver_data *data, size_t max)
else
amount= d_end+RX_BUFSIZE - d_start;
rxstat = *(u32_t *) (rep->v_re_rx_buf + d_start);
rxstat = *(uint32_t *) (rep->v_re_rx_buf + d_start);
/* Should convert from little endian to host byte order */
@@ -1175,7 +1175,7 @@ static void rl_do_reset(re_t *rep)
static void dump_phy(re_t *rep)
{
port_t port;
u32_t t;
uint32_t t;
port= rep->re_base_port;
@@ -1273,7 +1273,7 @@ static int rl_handler(re_t *rep)
{
int i, port, tx_head, tx_tail, link_up;
uint16_t isr, tsad;
u32_t tsd, tcr, ertxth;
uint32_t tsd, tcr, ertxth;
port= rep->re_base_port;

2
minix/drivers/net/rtl8139/rtl8139.h
View File

@@ -467,7 +467,7 @@ typedef struct re
phys_bytes ret_buf;
char * v_ret_buf;
} re_tx[N_TX_BUF];
u32_t re_ertxth; /* Early Tx Threshold */
uint32_t re_ertxth; /* Early Tx Threshold */
int re_hook_id; /* IRQ hook id at kernel */
} re_t;

64
minix/drivers/net/rtl8169/rtl8169.c
View File

@@ -27,30 +27,30 @@
typedef struct re_desc
{
u32_t status; /* command/status */
u32_t vlan; /* VLAN */
u32_t addr_low; /* low 32-bits of physical buffer address */
u32_t addr_high; /* high 32-bits of physical buffer address */
uint32_t status; /* command/status */
uint32_t vlan; /* VLAN */
uint32_t addr_low; /* low 32-bits of physical buffer address */
uint32_t addr_high; /* high 32-bits of physical buffer address */
} re_desc;
typedef struct re_dtcc
{
u32_t TxOk_low; /* low 32-bits of Tx Ok packets */
u32_t TxOk_high; /* high 32-bits of Tx Ok packets */
u32_t RxOk_low; /* low 32-bits of Rx Ok packets */
u32_t RxOk_high; /* high 32-bits of Rx Ok packets */
u32_t TxEr_low; /* low 32-bits of Tx errors */
u32_t TxEr_high; /* high 32-bits of Tx errors */
u32_t RxEr; /* Rx errors */
uint32_t TxOk_low; /* low 32-bits of Tx Ok packets */
uint32_t TxOk_high; /* high 32-bits of Tx Ok packets */
uint32_t RxOk_low; /* low 32-bits of Rx Ok packets */
uint32_t RxOk_high; /* high 32-bits of Rx Ok packets */
uint32_t TxEr_low; /* low 32-bits of Tx errors */
uint32_t TxEr_high; /* high 32-bits of Tx errors */
uint32_t RxEr; /* Rx errors */
uint16_t MissPkt; /* Missed packets */
uint16_t FAE; /* Frame Alignment Error packets (MII only) */
u32_t Tx1Col; /* Tx Ok packets with 1 collision before Tx */
u32_t TxMCol; /* Tx Ok packets with 2..15 collisions */
u32_t RxOkPhy_low; /* low 32-bits of Rx Ok packets for us */
u32_t RxOkPhy_high; /* high 32-bits of Rx Ok packets for us */
u32_t RxOkBrd_low; /* low 32-bits of Rx Ok broadcast packets */
u32_t RxOkBrd_high; /* high 32-bits of Rx Ok broadcast packets */
u32_t RxOkMul; /* Rx Ok multicast packets */
uint32_t Tx1Col; /* Tx Ok packets with 1 collision before Tx */
uint32_t TxMCol; /* Tx Ok packets with 2..15 collisions */
uint32_t RxOkPhy_low; /* low 32-bits of Rx Ok packets for us */
uint32_t RxOkPhy_high; /* high 32-bits of Rx Ok packets for us */
uint32_t RxOkBrd_low; /* low 32-bits of Rx Ok broadcast packets */
uint32_t RxOkBrd_high; /* high 32-bits of Rx Ok broadcast packets */
uint32_t RxOkMul; /* Rx Ok multicast packets */
uint16_t TxAbt; /* Tx abort packets */
uint16_t TxUndrn; /* Tx underrun packets */
} re_dtcc;
@@ -65,7 +65,7 @@ typedef struct re {
int re_report_link;
int re_need_reset;
int re_tx_alive;
u32_t re_mac;
uint32_t re_mac;
const char *re_model;
/* Rx */
@@ -92,15 +92,15 @@ typedef struct re {
int re_hook_id; /* IRQ hook id at kernel */
phys_bytes dtcc_buf; /* Dump Tally Counter buffer physical */
re_dtcc *v_dtcc_buf; /* Dump Tally Counter buffer */
u32_t dtcc_counter; /* DTCC update counter */
u32_t interrupts;
uint32_t dtcc_counter; /* DTCC update counter */
uint32_t interrupts;
} re_t;
static re_t re_state;
static unsigned my_inb(uint16_t port)
{
u32_t value;
uint32_t value;
int s;
if ((s = sys_inb(port, &value)) != OK)
printf("RTL8169: warning, sys_inb failed: %d\n", s);
@@ -108,7 +108,7 @@ static unsigned my_inb(uint16_t port)
}
static unsigned my_inw(uint16_t port)
{
u32_t value;
uint32_t value;
int s;
if ((s = sys_inw(port, &value)) != OK)
printf("RTL8169: warning, sys_inw failed: %d\n", s);
@@ -116,7 +116,7 @@ static unsigned my_inw(uint16_t port)
}
static unsigned my_inl(uint16_t port)
{
u32_t value;
uint32_t value;
int s;
if ((s = sys_inl(port, &value)) != OK)
printf("RTL8169: warning, sys_inl failed: %d\n", s);
@@ -140,7 +140,7 @@ static void my_outw(uint16_t port, uint16_t value)
if ((s = sys_outw(port, value)) != OK)
printf("RTL8169: warning, sys_outw failed: %d\n", s);
}
static void my_outl(uint16_t port, u32_t value)
static void my_outl(uint16_t port, uint32_t value)
{
int s;
@@ -401,7 +401,7 @@ static int rl_probe(re_t *rep, unsigned int skip)
{
int r, devind;
uint16_t vid, did;
u32_t bar;
uint32_t bar;
uint8_t ilr;
#if VERBOSE
const char *dname;
@@ -677,7 +677,7 @@ static void rtl8169scd_phy_config(port_t port)
static void rl_reset_hw(re_t *rep)
{
port_t port;
u32_t t;
uint32_t t;
int i;
port = rep->re_base_port;
@@ -849,7 +849,7 @@ static void rl_set_hwaddr(const netdriver_addr_t *addr)
{
re_t *rep;
port_t port;
u32_t w;
uint32_t w;
int i;
rep = &re_state;
@@ -873,8 +873,8 @@ static void rl_set_hwaddr(const netdriver_addr_t *addr)
static void rl_rec_mode(re_t *rep)
{
port_t port;
u32_t rcr;
u32_t mc_filter[2]; /* Multicast hash filter */
uint32_t rcr;
uint32_t mc_filter[2]; /* Multicast hash filter */
port = rep->re_base_port;
@@ -903,7 +903,7 @@ static ssize_t rl_recv(struct netdriver_data *data, size_t max)
port_t port;
unsigned totlen, packlen;
re_desc *desc;
u32_t rxstat;
uint32_t rxstat;
re_t *rep;
rep = &re_state;
@@ -1140,7 +1140,7 @@ static void rl_do_reset(re_t *rep)
static void dump_phy(const re_t *rep)
{
port_t port;
u32_t t;
uint32_t t;
port = rep->re_base_port;

6
minix/drivers/net/virtio_net/virtio_net.c
View File

@@ -133,8 +133,8 @@ virtio_net_probe(unsigned int skip)
static void
virtio_net_config(netdriver_addr_t * addr)
{
u32_t mac14;
u32_t mac56;
uint32_t mac14;
uint32_t mac56;
int i;
if (virtio_host_supports(net_dev, VIRTIO_NET_F_MAC)) {
@@ -152,7 +152,7 @@ virtio_net_config(netdriver_addr_t * addr)
}
if (virtio_host_supports(net_dev, VIRTIO_NET_F_STATUS)) {
dput(("Current Status %x", (u32_t)virtio_sread16(net_dev, 6)));
dput(("Current Status %x", (uint32_t)virtio_sread16(net_dev, 6)));
} else {
dput(("No status"));
}

2
minix/drivers/net/virtio_net/virtio_net.h
View File

@@ -137,7 +137,7 @@ typedef uint8_t virtio_net_ctrl_ack;
* is available.
*/
struct virtio_net_ctrl_mac {
u32_t entries;
uint32_t entries;
#define ETH_ALEN 6
uint8_t macs[][ETH_ALEN];
} __attribute__((packed));

22
minix/drivers/net/vt6105/io.h
View File

@@ -6,8 +6,8 @@
#include "vt6105.h"
/* I/O function */
static uint8_t my_inb(u32_t port) {
u32_t value;
static uint8_t my_inb(uint32_t port) {
uint32_t value;
int r;
#ifdef DMA_BASE_IOMAP
value = *(volatile uint8_t *)(port);
@@ -19,8 +19,8 @@ static uint8_t my_inb(u32_t port) {
}
#define ndr_in8(port, offset) (my_inb((port) + (offset)))
static uint16_t my_inw(u32_t port) {
u32_t value;
static uint16_t my_inw(uint32_t port) {
uint32_t value;
int r;
#ifdef DMA_BASE_IOMAP
value = *(volatile uint16_t *)(port);
@@ -32,11 +32,11 @@ static uint16_t my_inw(u32_t port) {
}
#define ndr_in16(port, offset) (my_inw((port) + (offset)))
static u32_t my_inl(u32_t port) {
u32_t value;
static uint32_t my_inl(uint32_t port) {
uint32_t value;
int r;
#ifdef DMA_BASE_IOMAP
value = *(volatile u32_t *)(port);
value = *(volatile uint32_t *)(port);
#else
if ((r = sys_inl(port, &value)) != OK)
printf("NDR: sys_inl failed: %d\n", r);
@@ -45,7 +45,7 @@ static u32_t my_inl(u32_t port) {
}
#define ndr_in32(port, offset) (my_inl((port) + (offset)))
static void my_outb(u32_t port, u32_t value) {
static void my_outb(uint32_t port, uint32_t value) {
int r;
#ifdef DMA_BASE_IOMAP
*(volatile uint8_t *)(port) = value;
@@ -57,7 +57,7 @@ static void my_outb(u32_t port, u32_t value) {
#define ndr_out8(port, offset, value) \
(my_outb(((port) + (offset)), (value)))
static void my_outw(u32_t port, u32_t value) {
static void my_outw(uint32_t port, uint32_t value) {
int r;
#ifdef DMA_BASE_IOMAP
*(volatile uint16_t *)(port) = value;
@@ -69,10 +69,10 @@ static void my_outw(u32_t port, u32_t value) {
#define ndr_out16(port, offset, value) \
(my_outw(((port) + (offset)), (value)))
static void my_outl(u32_t port, u32_t value) {
static void my_outl(uint32_t port, uint32_t value) {
int r;
#ifdef DMA_BASE_IOMAP
*(volatile u32_t *)(port) = value;
*(volatile uint32_t *)(port) = value;
#else
if ((r = sys_outl(port, value)) != OK)
printf("NDR: sys_outl failed: %d\n", r);

98
minix/drivers/net/vt6105/vt6105.c
View File

@@ -29,29 +29,29 @@ static void dev_handler(NDR_driver *pdev);
static void dev_check_ints(NDR_driver *pdev);
/* developer interface */
static int dev_real_reset(u32_t *base);
static int dev_init_io(u32_t *base);
static int dev_init_mii(u32_t *base);
static void dev_intr_control(u32_t *base, int flag);
static void dev_rx_tx_control(u32_t *base, int flag);
static void dev_get_addr(u32_t *base, uint8_t *pa);
static int dev_check_link(u32_t *base);
static void dev_set_rec_mode(u32_t *base, int mode);
static void dev_start_tx(u32_t *base);
static u32_t dev_read_clear_intr_status(u32_t *base);
static int dev_real_reset(uint32_t *base);
static int dev_init_io(uint32_t *base);
static int dev_init_mii(uint32_t *base);
static void dev_intr_control(uint32_t *base, int flag);
static void dev_rx_tx_control(uint32_t *base, int flag);
static void dev_get_addr(uint32_t *base, uint8_t *pa);
static int dev_check_link(uint32_t *base);
static void dev_set_rec_mode(uint32_t *base, int mode);
static void dev_start_tx(uint32_t *base);
static uint32_t dev_read_clear_intr_status(uint32_t *base);
static void dev_init_rx_desc(NDR_desc *desc_start, int index, size_t buf_size,
phys_bytes buf_dma, int max_desc_num, phys_bytes desc_dma_start);
static void dev_init_tx_desc(NDR_desc *desc_start, int index, size_t buf_size,
phys_bytes buf_dma, int max_desc_num, phys_bytes desc_dma_start);
static void dev_set_desc_reg(u32_t *base, phys_bytes rx_addr,
static void dev_set_desc_reg(uint32_t *base, phys_bytes rx_addr,
phys_bytes tx_addr);
static int dev_rx_ok_desc(u32_t *base, NDR_desc *desc, int index);
static int dev_rx_len_desc(u32_t *base, NDR_desc *desc, int index);
static void dev_set_rx_desc_done(u32_t *base, NDR_desc *desc, int index);
static void dev_set_tx_desc_prepare(u32_t *base, NDR_desc *desc, int index,
static int dev_rx_ok_desc(uint32_t *base, NDR_desc *desc, int index);
static int dev_rx_len_desc(uint32_t *base, NDR_desc *desc, int index);
static void dev_set_rx_desc_done(uint32_t *base, NDR_desc *desc, int index);
static void dev_set_tx_desc_prepare(uint32_t *base, NDR_desc *desc, int index,
size_t data_size);
static int dev_tx_ok_desc(u32_t *base, NDR_desc *desc, int index);
static void dev_set_tx_desc_done(u32_t *base, NDR_desc *desc, int index);
static int dev_tx_ok_desc(uint32_t *base, NDR_desc *desc, int index);
static void dev_set_tx_desc_done(uint32_t *base, NDR_desc *desc, int index);
/* ======= Developer implemented function ======= */
/* ====== Self-defined function ======*/
@@ -59,8 +59,8 @@ static void dev_set_tx_desc_done(u32_t *base, NDR_desc *desc, int index);
/* ====== Developer interface ======*/
/* Real hardware reset (### RESET_HARDWARE_CAN_FAIL ###)
* -- Return OK means success, Others means failure */
static int dev_real_reset(u32_t *base) {
u32_t base0 = base[0];
static int dev_real_reset(uint32_t *base) {
uint32_t base0 = base[0];
ndr_out16(base0, REG_CR, CMD_RESET);
micro_delay(5000);
if (ndr_in16(base0, REG_CR) & CMD_RESET) {
@@ -74,8 +74,8 @@ static int dev_real_reset(u32_t *base) {
/* Intialize other hardware I/O registers (### INIT_HARDWARE_IO_CAN_FAIL ###)
* -- Return OK means success, Others means failure */
static int dev_init_io(u32_t *base) {
u32_t base0 = base[0];
static int dev_init_io(uint32_t *base) {
uint32_t base0 = base[0];
uint8_t stick;
stick = ndr_in8(base0, REG_STICK);
ndr_out8(base0, REG_STICK, stick & 0xfc);
@@ -87,8 +87,8 @@ static int dev_init_io(u32_t *base) {
/* Intialize MII interface (### MII_INIT_CAN_FAIL ###)
-- Return OK means success, Others means failure */
static int dev_init_mii(u32_t *base) {
u32_t base0 = base[0];
static int dev_init_mii(uint32_t *base) {
uint32_t base0 = base[0];
ndr_out8(base0, REG_MII_CR, 0);
ndr_out8(base0, REG_MII_REG, 0x01);
ndr_out8(base0, REG_MII_CR, 0x80);
@@ -102,8 +102,8 @@ static int dev_init_mii(u32_t *base) {
}
/* Enable or disable interrupt (### INTR_ENABLE_DISABLE ###) */
static void dev_intr_control(u32_t *base, int flag) {
u32_t data, base0 = base[0];
static void dev_intr_control(uint32_t *base, int flag) {
uint32_t data, base0 = base[0];
data = ndr_in16(base0, REG_IMR);
if (flag == INTR_ENABLE)
ndr_out16(base0, REG_IMR, data | CMD_INTR_ENABLE);
@@ -112,8 +112,8 @@ static void dev_intr_control(u32_t *base, int flag) {
}
/* Enable or disable Rx/Tx (### RX_TX_ENABLE_DISABLE ###) */
static void dev_rx_tx_control(u32_t *base, int flag) {
u32_t data, base0 = base[0];
static void dev_rx_tx_control(uint32_t *base, int flag) {
uint32_t data, base0 = base[0];
if (flag == RX_TX_ENABLE) {
data = CMD_START | CMD_RX_ON | CMD_TX_ON | CMD_NO_POLL | CMD_FDUPLEX;
ndr_out16(base0, REG_CR, data);
@@ -124,16 +124,16 @@ static void dev_rx_tx_control(u32_t *base, int flag) {
}
/* Get MAC address to the array 'pa' (### GET_MAC_ADDR ###) */
static void dev_get_addr(u32_t *base, uint8_t *pa) {
u32_t i, base0 = base[0];
static void dev_get_addr(uint32_t *base, uint8_t *pa) {
uint32_t i, base0 = base[0];
for (i = 0; i < 6; i++)
pa[i] = ndr_in8(base0, REG_ADDR + i);
}
/* Check link status (### CHECK_LINK ###)
* -- Return LINK_UP or LINK_DOWN */
static int dev_check_link(u32_t *base) {
u32_t data, base0 = base[0];
static int dev_check_link(uint32_t *base) {
uint32_t data, base0 = base[0];
ndr_out8(base0, REG_MII_PHY, 0x01);
ndr_out8(base0, REG_MII_REG, 0x01);
ndr_out8(base0, REG_MII_CR, 0x40);
@@ -147,8 +147,8 @@ static int dev_check_link(u32_t *base) {
}
/* Set driver receive mode (### SET_REC_MODE ###) */
static void dev_set_rec_mode(u32_t *base, int mode) {
u32_t data, base0 = base[0];
static void dev_set_rec_mode(uint32_t *base, int mode) {
uint32_t data, base0 = base[0];
data = ndr_in8(base0, REG_RCR);
data &= ~(CMD_RCR_UNICAST | CMD_RCR_MULTICAST | CMD_RCR_BROADCAST);
if (mode & NDEV_MODE_PROMISC)
@@ -162,15 +162,15 @@ static void dev_set_rec_mode(u32_t *base, int mode) {
}
/* Start Tx channel (### START_TX_CHANNEL ###) */
static void dev_start_tx(u32_t *base) {
u32_t data, base0 = base[0];
static void dev_start_tx(uint32_t *base) {
uint32_t data, base0 = base[0];
data = ndr_in8(base0, REG_CR);
ndr_out8(base0, REG_CR, data | CMD_TX_DEMAND);
}
/* Read and clear interrupt (### READ_CLEAR_INTR_STS ###) */
static u32_t dev_read_clear_intr_status(u32_t *base) {
u32_t data, base0 = base[0];
static uint32_t dev_read_clear_intr_status(uint32_t *base) {
uint32_t data, base0 = base[0];
data = ndr_in16(base0, REG_ISR);
ndr_out16(base0, REG_ISR, data & INTR_STS_CLEAR);
return data;
@@ -203,9 +203,9 @@ static void dev_init_tx_desc(NDR_desc *desc_start, int index, size_t buf_size,
}
/* Set Rx/Tx descriptor address into device register (### SET_DESC_REG ###) */
static void dev_set_desc_reg(u32_t *base, phys_bytes rx_addr,
static void dev_set_desc_reg(uint32_t *base, phys_bytes rx_addr,
phys_bytes tx_addr) {
u32_t base0 = base[0];
uint32_t base0 = base[0];
ndr_out32(base0, REG_RX_DESC_BASE, rx_addr);
ndr_out32(base0, REG_TX_DESC_BASE, tx_addr);
}
@@ -213,7 +213,7 @@ static void dev_set_desc_reg(u32_t *base, phys_bytes rx_addr,
/* Check whether Rx is OK from Rx descriptor (### CHECK_RX_OK_FROM_DESC ###)
* -- Current buffer number is index
* -- Return RX_OK or RX_SUSPEND or RX_ERROR */
static int dev_rx_ok_desc(u32_t *base, NDR_desc *desc, int index) {
static int dev_rx_ok_desc(uint32_t *base, NDR_desc *desc, int index) {
if (!(desc->status & DESC_OWN)) {
if (desc->status & DESC_RX_ERROR)
return RX_ERROR;
@@ -226,19 +226,19 @@ static int dev_rx_ok_desc(u32_t *base, NDR_desc *desc, int index) {
/* Get length from Rx descriptor (### GET_RX_LENGTH_FROM_DESC ###)
* -- Current buffer number is index
* -- Return the length */
static int dev_rx_len_desc(u32_t *base, NDR_desc *desc, int index) {
static int dev_rx_len_desc(uint32_t *base, NDR_desc *desc, int index) {
return ((desc->status & DESC_RX_LENMASK) >> 16) - NDEV_ETH_PACKET_CRC;
}
/* Set Rx descriptor after Rx done (### SET_RX_DESC_DONE ###)
* -- Current buffer number is index */
static void dev_set_rx_desc_done(u32_t *base, NDR_desc *desc, int index) {
static void dev_set_rx_desc_done(uint32_t *base, NDR_desc *desc, int index) {
desc->status = DESC_OWN;
}
/* Set Tx descriptor to prepare transmitting (### SET_TX_DESC_PREPARE)
* -- Current buffer number is index */
static void dev_set_tx_desc_prepare(u32_t *base, NDR_desc *desc, int index,
static void dev_set_tx_desc_prepare(uint32_t *base, NDR_desc *desc, int index,
size_t data_size) {
desc->status = DESC_OWN | DESC_FIRST | DESC_LAST;
desc->length = 0x00e08000 | (data_size > 60 ? data_size : 60);
@@ -247,7 +247,7 @@ static void dev_set_tx_desc_prepare(u32_t *base, NDR_desc *desc, int index,
/* Check whether Tx is OK from Tx descriptor (### CHECK_TX_OK_FROM_DESC ###)
* -- Current buffer number is index
* -- Return TX_OK or TX_SUSPEND or TX_ERROR */
static int dev_tx_ok_desc(u32_t *base, NDR_desc *desc, int index) {
static int dev_tx_ok_desc(uint32_t *base, NDR_desc *desc, int index) {
if (!(desc->status & DESC_OWN)) {
if (desc->status & DESC_TX_ERROR)
return TX_ERROR;
@@ -258,7 +258,7 @@ static int dev_tx_ok_desc(u32_t *base, NDR_desc *desc, int index) {
/* Set Tx descriptor after Tx done (### SET_TX_DESC_DONE ###)
* -- Current buffer number is index */
static void dev_set_tx_desc_done(u32_t *base, NDR_desc *desc, int index) {
static void dev_set_tx_desc_done(uint32_t *base, NDR_desc *desc, int index) {
desc->status = 0;
}
@@ -360,7 +360,7 @@ NDR_set_mode(unsigned int mode, const netdriver_addr_t * mcast_list __unused,
/* Receive data */
static ssize_t NDR_recv(struct netdriver_data *data, size_t max) {
NDR_driver *pdev = &g_driver;
u32_t totlen, packlen;
uint32_t totlen, packlen;
int index, ret, offset = 0;
NDR_desc *desc;
@@ -462,7 +462,7 @@ static void NDR_intr(unsigned int mask) {
static int dev_probe(NDR_driver *pdev, int instance) {
int devind, ioflag, i;
uint16_t cr, vid, did;
u32_t bar, size, base;
uint32_t bar, size, base;
uint8_t irq, rev;
uint8_t *reg;
@@ -497,7 +497,7 @@ static int dev_probe(NDR_driver *pdev, int instance) {
printf("NDR: Fail to map hardware registers from PCI\n");
return -EIO;
}
pdev->base[i] = (u32_t)reg;
pdev->base[i] = (uint32_t)reg;
}
#else
for (i = 0; i < 6; i++)
@@ -707,7 +707,7 @@ static int dev_init_buf(NDR_driver *pdev) {
/* Real handler interrupt */
static void dev_handler(NDR_driver *pdev) {
u32_t intr_status;
uint32_t intr_status;
int tx_head, tx_tail, index, flag = 0, ret;
NDR_desc *desc;

12
minix/drivers/net/vt6105/vt6105.h
View File

@@ -85,18 +85,18 @@
/* ======= Data Descriptor ======= */
typedef struct NDR_desc {
u32_t status;
u32_t length;
u32_t addr;
u32_t next;
uint32_t status;
uint32_t length;
uint32_t addr;
uint32_t next;
} NDR_desc;
/* Driver Data Structure */
typedef struct NDR_driver {
char *dev_name; /* Device name */
uint16_t vid, did; /* Vendor and device ID */
u32_t devind; /* Device index */
u32_t base[6]; /* Base address */
uint32_t devind; /* Device index */
uint32_t base[6]; /* Base address */
char irq; /* IRQ number */
char revision; /* Revision ID */

16
minix/drivers/power/acpi/osminixxf.c
View File

@@ -58,24 +58,24 @@
extern struct machine machine;
static u32_t pci_inb(uint16_t port) {
u32_t value;
static uint32_t pci_inb(uint16_t port) {
uint32_t value;
int s;
if ((s=sys_inb(port, &value)) !=OK)
printf("ACPI: warning, sys_inb failed: %d\n", s);
return value;
}
static u32_t pci_inw(uint16_t port) {
u32_t value;
static uint32_t pci_inw(uint16_t port) {
uint32_t value;
int s;
if ((s=sys_inw(port, &value)) !=OK)
printf("ACPI: warning, sys_inw failed: %d\n", s);
return value;
}
static u32_t pci_inl(uint16_t port) {
u32_t value;
static uint32_t pci_inl(uint16_t port) {
uint32_t value;
int s;
if ((s=sys_inl(port, &value)) !=OK)
printf("ACPI: warning, sys_inl failed: %d\n", s);
@@ -94,7 +94,7 @@ static void pci_outw(uint16_t port, uint16_t value) {
printf("ACPI: warning, sys_outw failed: %d\n", s);
}
static void pci_outl(uint16_t port, u32_t value) {
static void pci_outl(uint16_t port, uint32_t value) {
int s;
if ((s=sys_outl(port, value)) !=OK)
printf("ACPI: warning, sys_outl failed: %d\n", s);
@@ -966,7 +966,7 @@ AcpiOsReadPciConfiguration (
PciId->Function, Register);
break;
case 32:
*(u32_t *)Value = PCII_RREG32_(PciId->Bus, PciId->Device,
*(uint32_t *)Value = PCII_RREG32_(PciId->Bus, PciId->Device,
PciId->Function, Register);
break;
default:

2
minix/drivers/power/tps65217/tps65217.c
View File

@@ -249,7 +249,7 @@ static int
lu_state_restore(void)
{
/* Restore the state. */
u32_t value;
uint32_t value;
ds_retrieve_u32("bus", &value);
ds_delete_u32("bus");

2
minix/drivers/power/tps65950/tps65950.c
View File

@@ -153,7 +153,7 @@ static int
lu_state_restore(void)
{
/* Restore the state. */
u32_t value;
uint32_t value;
ds_retrieve_u32("bus", &value);
ds_delete_u32("bus");

4
minix/drivers/printer/printer/printer.c
View File

@@ -163,7 +163,7 @@ static ssize_t printer_write(devminor_t UNUSED(minor), u64_t UNUSED(position),
{
/* The printer is used by sending write requests to it. Process one. */
int retries;
u32_t status;
uint32_t status;
/* Reject command if last write is not yet finished, the count is not
* positive, or we're asked not to block.
@@ -350,7 +350,7 @@ static void printer_intr(unsigned int UNUSED(mask))
* IRQ yet!
*/
u32_t status;
uint32_t status;
pvb_pair_t char_out[3];
if (oleft == 0) {

2
minix/drivers/sensors/bmp085/bmp085.c
View File

@@ -478,7 +478,7 @@ static int
lu_state_restore(void)
{
/* Restore the state. */
u32_t value;
uint32_t value;
ds_retrieve_u32("bus", &value);
ds_delete_u32("bus");

2
minix/drivers/sensors/sht21/sht21.c
View File

@@ -381,7 +381,7 @@ static int
lu_state_restore(void)
{
/* Restore the state. */
u32_t value;
uint32_t value;
ds_retrieve_u32("bus", &value);
ds_delete_u32("bus");

2
minix/drivers/sensors/tsl2550/tsl2550.c
View File

@@ -330,7 +330,7 @@ static int
lu_state_restore(void)
{
/* Restore the state. */
u32_t value;
uint32_t value;
ds_retrieve_u32("bus", &value);
ds_delete_u32("bus");

56
minix/drivers/storage/ahci/ahci.c
View File

@@ -121,7 +121,7 @@
/* Host Bus Adapter (HBA) state. */
static struct {
volatile u32_t *base; /* base address of memory-mapped registers */
volatile uint32_t *base; /* base address of memory-mapped registers */
size_t size; /* size of memory-mapped register area */
int nr_ports; /* addressable number of ports (1..NR_PORTS) */
@@ -141,16 +141,16 @@ static struct port_state {
int state; /* port state */
unsigned int flags; /* port flags */
volatile u32_t *reg; /* memory-mapped port registers */
volatile uint32_t *reg; /* memory-mapped port registers */
uint8_t *mem_base; /* primary memory buffer virtual address */
phys_bytes mem_phys; /* primary memory buffer physical address */
vir_bytes mem_size; /* primary memory buffer size */
/* the FIS, CL, CT[0] and TMP buffers are all in the primary buffer */
u32_t *fis_base; /* FIS receive buffer virtual address */
uint32_t *fis_base; /* FIS receive buffer virtual address */
phys_bytes fis_phys; /* FIS receive buffer physical address */
u32_t *cl_base; /* command list buffer virtual address */
uint32_t *cl_base; /* command list buffer virtual address */
phys_bytes cl_phys; /* command list buffer physical address */
uint8_t *ct_base[NR_CMDS]; /* command table virtual address */
phys_bytes ct_phys[NR_CMDS]; /* command table physical address */
@@ -162,7 +162,7 @@ static struct port_state {
vir_bytes pad_size; /* sector padding buffer size */
u64_t lba_count; /* number of valid Logical Block Addresses */
u32_t sector_size; /* medium sector size in bytes */
uint32_t sector_size; /* medium sector size in bytes */
int open_count; /* number of times this port is opened */
@@ -175,7 +175,7 @@ static struct port_state {
/* (only used for signature probing) */
int queue_depth; /* NCQ queue depth */
u32_t pend_mask; /* commands not yet complete */
uint32_t pend_mask; /* commands not yet complete */
struct {
thread_id_t tid;/* ID of the worker thread */
minix_timer_t timer; /* timer associated with each request */
@@ -202,7 +202,7 @@ static clock_t ahci_flush_timeout;
/* Timeout environment variable names and default values. */
static struct {
char *name; /* environment variable name */
u32_t default_ms; /* default in milliseconds */
uint32_t default_ms; /* default in milliseconds */
clock_t *ptr; /* clock ticks value pointer */
} ahci_timevar[] = {
{ "ahci_init_timeout", SPINUP_TIMEOUT, &ahci_spinup_timeout },
@@ -826,10 +826,10 @@ static void ct_set_prdt(uint8_t *ct, prd_t *prdt, int nr_prds)
{
/* Fill in the PRDT part of a command table.
*/
u32_t *p;
uint32_t *p;
int i;
p = (u32_t *) &ct[AHCI_CT_PRDT_OFF];
p = (uint32_t *) &ct[AHCI_CT_PRDT_OFF];
for (i = 0; i < nr_prds; i++, prdt++) {
*p++ = prdt->vp_addr;
@@ -849,7 +849,7 @@ static void port_set_cmd(struct port_state *ps, int cmd, cmd_fis_t *fis,
* table and setting up a command list entry pointing to the table.
*/
uint8_t *ct;
u32_t *cl;
uint32_t *cl;
vir_bytes size;
/* Set a port-specific flag that tells us if the command being
@@ -890,7 +890,7 @@ static void port_set_cmd(struct port_state *ps, int cmd, cmd_fis_t *fis,
(nr_prds > 0 || packet != NULL)) ? AHCI_CL_PREFETCHABLE : 0) |
(write ? AHCI_CL_WRITE : 0) |
((packet != NULL) ? AHCI_CL_ATAPI : 0) |
((size / sizeof(u32_t)) << AHCI_CL_CFL_SHIFT);
((size / sizeof(uint32_t)) << AHCI_CL_CFL_SHIFT);
cl[2] = ps->ct_phys[cmd];
}
@@ -942,7 +942,7 @@ static void port_check_cmds(struct port_state *ps)
{
/* Check what commands have completed, and finish them.
*/
u32_t mask, done;
uint32_t mask, done;
int i;
/* See which commands have completed. */
@@ -1237,7 +1237,7 @@ static void port_override(struct port_state *ps)
/* Override the port's BSY and/or DRQ flags. This may only be done
* prior to starting the port.
*/
u32_t cmd;
uint32_t cmd;
cmd = port_read(ps, AHCI_PORT_CMD);
port_write(ps, AHCI_PORT_CMD, cmd | AHCI_PORT_CMD_CLO);
@@ -1256,7 +1256,7 @@ static void port_start(struct port_state *ps)
/* Start the given port, allowing for the execution of commands and the
* transfer of data on that port.
*/
u32_t cmd;
uint32_t cmd;
/* Reset status registers. */
port_write(ps, AHCI_PORT_SERR, ~0);
@@ -1276,7 +1276,7 @@ static void port_stop(struct port_state *ps)
{
/* Stop the given port, if not already stopped.
*/
u32_t cmd;
uint32_t cmd;
cmd = port_read(ps, AHCI_PORT_CMD);
@@ -1439,7 +1439,7 @@ static void port_connect(struct port_state *ps)
/* A device has been found to be attached to this port. Start the port,
* and do timed polling for its signature to become available.
*/
u32_t status, sig;
uint32_t status, sig;
dprintf(V_INFO, ("%s: device connected\n", ahci_portname(ps)));
@@ -1524,7 +1524,7 @@ static void port_dev_check(struct port_state *ps)
{
/* Perform device detection by means of polling.
*/
u32_t status, tfd;
uint32_t status, tfd;
assert(ps->state == STATE_WAIT_DEV);
@@ -1596,7 +1596,7 @@ static void port_intr(struct port_state *ps)
{
/* Process an interrupt on this port.
*/
u32_t smask, emask;
uint32_t smask, emask;
int success;
if (ps->state == STATE_NO_PORT) {
@@ -1885,7 +1885,7 @@ static void port_alloc(struct port_state *ps)
*/
size_t fis_off, tmp_off, ct_off; int i;
size_t ct_offs[NR_CMDS];
u32_t cmd;
uint32_t cmd;
fis_off = AHCI_CL_SIZE + AHCI_FIS_SIZE - 1;
fis_off -= fis_off % AHCI_FIS_SIZE;
@@ -1908,11 +1908,11 @@ static void port_alloc(struct port_state *ps)
panic("unable to allocate port memory");
memset(ps->mem_base, 0, ps->mem_size);
ps->cl_base = (u32_t *) ps->mem_base;
ps->cl_base = (uint32_t *) ps->mem_base;
ps->cl_phys = ps->mem_phys;
assert(ps->cl_phys % AHCI_CL_SIZE == 0);
ps->fis_base = (u32_t *) (ps->mem_base + fis_off);
ps->fis_base = (uint32_t *) (ps->mem_base + fis_off);
ps->fis_phys = ps->mem_phys + fis_off;
assert(ps->fis_phys % AHCI_FIS_SIZE == 0);
@@ -1949,7 +1949,7 @@ static void port_free(struct port_state *ps)
/* Disable FIS receipt for the given port, and free previously
* allocated memory.
*/
u32_t cmd;
uint32_t cmd;
/* Disable FIS receive. */
cmd = port_read(ps, AHCI_PORT_CMD);
@@ -1974,7 +1974,7 @@ static void port_init(struct port_state *ps)
{
/* Initialize the given port.
*/
u32_t cmd;
uint32_t cmd;
int i;
/* Initialize the port state structure. */
@@ -1987,7 +1987,7 @@ static void port_init(struct port_state *ps)
for (i = 0; i < NR_CMDS; i++)
init_timer(&ps->cmd_info[i].timer);
ps->reg = (u32_t *) ((uint8_t *) hba_state.base +
ps->reg = (uint32_t *) ((uint8_t *) hba_state.base +
AHCI_MEM_BASE_SIZE + AHCI_MEM_PORT_SIZE * (ps - port_state));
/* Allocate memory for the port. */
@@ -2043,7 +2043,7 @@ static void ahci_reset(void)
{
/* Reset the HBA. Do not enable AHCI mode afterwards.
*/
u32_t ghc;
uint32_t ghc;
ghc = hba_read(AHCI_HBA_GHC);
@@ -2064,7 +2064,7 @@ static void ahci_init(int devind)
{
/* Initialize the device.
*/
u32_t base, size, cap, ghc, mask;
uint32_t base, size, cap, ghc, mask;
int r, port, ioflag;
if ((r = pci_get_bar(devind, PCI_BAR_6, &base, &size, &ioflag)) != OK)
@@ -2084,7 +2084,7 @@ static void ahci_init(int devind)
hba_state.nr_ports = (size - AHCI_MEM_BASE_SIZE) / AHCI_MEM_PORT_SIZE;
/* Map the register area into local memory. */
hba_state.base = (u32_t *) vm_map_phys(SELF, (void *) base, size);
hba_state.base = (uint32_t *) vm_map_phys(SELF, (void *) base, size);
hba_state.size = size;
if (hba_state.base == MAP_FAILED)
panic("unable to map HBA memory");
@@ -2190,7 +2190,7 @@ static void ahci_intr(unsigned int UNUSED(mask))
/* Process an interrupt.
*/
struct port_state *ps;
u32_t mask;
uint32_t mask;
int r, port;
/* Handle an interrupt for each port that has the interrupt bit set. */

8
minix/drivers/storage/ahci/ahci.h
View File

@@ -133,7 +133,7 @@
/* Command List constants. */
#define AHCI_CL_ENTRY_SIZE 32 /* Command List header size */
#define AHCI_CL_ENTRY_DWORDS (AHCI_CL_ENTRY_SIZE / sizeof(u32_t))
#define AHCI_CL_ENTRY_DWORDS (AHCI_CL_ENTRY_SIZE / sizeof(uint32_t))
#define AHCI_CL_PRDTL_SHIFT 16 /* PRD Table Length */
#define AHCI_CL_PREFETCHABLE (1L << 7) /* Prefetchable */
@@ -230,7 +230,7 @@
#define AHCI_CL_SIZE 1024 /* size of command list buffer */
#define AHCI_TMP_SIZE ATA_ID_SIZE /* size of temporary storage buffer */
#define AHCI_TMP_ALIGN 2 /* required alignment for temp buf */
#define AHCI_CT_SIZE (128 + NR_PRDS * sizeof(u32_t) * 4)
#define AHCI_CT_SIZE (128 + NR_PRDS * sizeof(uint32_t) * 4)
/* size of command table buffer */
#define AHCI_CT_ALIGN 128 /* required alignment for CT buffer */
@@ -243,9 +243,9 @@
typedef struct {
uint8_t cf_cmd; /* Command */
uint8_t cf_feat; /* Features */
u32_t cf_lba; /* LBA (24-bit) */
uint32_t cf_lba; /* LBA (24-bit) */
uint8_t cf_dev; /* Device */
u32_t cf_lba_exp; /* LBA (exp) (24-bit) */
uint32_t cf_lba_exp; /* LBA (exp) (24-bit) */
uint8_t cf_feat_exp; /* Features (exp) */
uint8_t cf_sec; /* Sector Count */
uint8_t cf_sec_exp; /* Sector Count (exp) */

34
minix/drivers/storage/at_wini/at_wini.c
View File

@@ -54,7 +54,7 @@ static long w_atapi_dma;
static int w_testing = 0;
static int w_silent = 0;
static u32_t system_hz;
static uint32_t system_hz;
/* The struct wini is indexed by drive (0-3). */
static struct wini { /* main drive struct, one entry per drive */
@@ -358,7 +358,7 @@ static void w_init(int devind, uint16_t vid, uint16_t did)
int r, irq, native_hook, compat_hook, is_ide, nhooks;
uint8_t bcr, scr, interface;
uint16_t cr;
u32_t base_cmd, base_ctl, base_dma;
uint32_t base_cmd, base_ctl, base_dma;
bcr= pci_attr_r8(devind, PCI_BCR);
scr= pci_attr_r8(devind, PCI_SCR);
@@ -552,10 +552,10 @@ static struct device *w_part(devminor_t device)
#define id_byte(n) (&tmp_buf[2 * (n)])
#define id_word(n) (((uint16_t) id_byte(n)[0] << 0) \
|((uint16_t) id_byte(n)[1] << 8))
#define id_longword(n) (((u32_t) id_byte(n)[0] << 0) \
|((u32_t) id_byte(n)[1] << 8) \
|((u32_t) id_byte(n)[2] << 16) \
|((u32_t) id_byte(n)[3] << 24))
#define id_longword(n) (((uint32_t) id_byte(n)[0] << 0) \
|((uint32_t) id_byte(n)[1] << 8) \
|((uint32_t) id_byte(n)[2] << 16) \
|((uint32_t) id_byte(n)[3] << 24))
/*===========================================================================*
* check_dma *
@@ -563,7 +563,7 @@ static struct device *w_part(devminor_t device)
static void
check_dma(struct wini *wn)
{
u32_t dma_status, dma_base;
uint32_t dma_status, dma_base;
int id_dma, ultra_dma;
uint16_t w;
@@ -683,7 +683,7 @@ static int w_identify(void)
wn->cylinders = id_word(1);
wn->heads = id_word(3);
wn->sectors = id_word(6);
size = (u32_t) wn->cylinders * wn->heads * wn->sectors;
size = (uint32_t) wn->cylinders * wn->heads * wn->sectors;
w= id_word(ID_CAPABILITIES);
if ((w & ID_CAP_LBA) && size > 512L*1024*2) {
@@ -944,7 +944,7 @@ static void stop_dma(const struct wini *wn)
static void start_dma(const struct wini *wn, int do_write)
{
u32_t v;
uint32_t v;
int r;
/* Assume disk reads. Start DMA */
@@ -961,7 +961,7 @@ static void start_dma(const struct wini *wn, int do_write)
static int error_dma(const struct wini *wn)
{
int r;
u32_t v;
uint32_t v;
#define DMAERR(msg) \
printf("at_wini%ld: bad DMA: %s. Disabling DMA for drive %d.\n", \
@@ -1007,7 +1007,7 @@ static ssize_t w_transfer(
iovec_t *iop, *iov_end = iov + nr_req;
int r, s, errors, do_dma;
unsigned long block;
u32_t w_status;
uint32_t w_status;
u64_t dv_size;
unsigned int n, nbytes;
unsigned dma_buf_offset;
@@ -1330,7 +1330,7 @@ static int setup_dma(
phys_bytes user_phys;
unsigned n, offset, size;
int i, j, r;
u32_t v;
uint32_t v;
struct wini *wn = w_wn;
/* First try direct scatter/gather to the supplied buffers */
@@ -1572,7 +1572,7 @@ static void w_intr_wait(void)
/* Wait for a task completion interrupt. */
int r;
u32_t w_status;
uint32_t w_status;
message m;
int ipc_status;
@@ -1627,7 +1627,7 @@ static int at_intr_wait(void)
{
/* Wait for an interrupt, study the status bits and return error/success. */
int r, s;
u32_t inbval;
uint32_t inbval;
w_intr_wait();
if ((w_wn->w_status & (STATUS_BSY | STATUS_WF | STATUS_ERR)) == 0) {
@@ -1654,7 +1654,7 @@ int value; /* required status */
{
/* Wait until controller is in the required state. Return zero on timeout.
*/
u32_t w_status;
uint32_t w_status;
spin_t spin;
int s;
@@ -1680,7 +1680,7 @@ unsigned value; /* required status */
{
/* Wait until controller is in the required state. Return zero on timeout.
*/
u32_t w_status;
uint32_t w_status;
spin_t spin;
int s;
@@ -2116,7 +2116,7 @@ static void w_hw_int(unsigned int UNUSED(irqs))
{
/* Leftover interrupt(s) received; ack it/them. For native drives only. */
unsigned int drive;
u32_t w_status;
uint32_t w_status;
for (drive = 0; drive < MAX_DRIVES; drive++) {
if (!(wini[drive].state & IGNORING) && wini[drive].native) {

12
minix/drivers/storage/fbd/action.c
View File

@@ -7,12 +7,12 @@
/*===========================================================================*
* get_rand *
*===========================================================================*/
static u32_t get_rand(u32_t max)
static uint32_t get_rand(uint32_t max)
{
/* Las Vegas algorithm for getting a random number in the range from
* 0 to max, inclusive.
*/
u32_t val, top;
uint32_t val, top;
/* Get an initial random number. */
val = lrand48() ^ (lrand48() << 1);
@@ -24,7 +24,7 @@ static u32_t get_rand(u32_t max)
* number from the range, throwing away any random numbers not below
* this largest multiple.
*/
top = (((u32_t) -1) / max) * max;
top = (((uint32_t) -1) / max) * max;
while (val >= top)
val = lrand48() ^ (lrand48() << 1);
@@ -108,7 +108,7 @@ static void action_io_corrupt(struct fbd_rule *rule, char *buf, size_t size,
u64_t pos, int UNUSED(flag))
{
u64_t skip;
u32_t val;
uint32_t val;
buf += get_range(rule, pos, &size, &skip);
@@ -128,7 +128,7 @@ static void action_io_corrupt(struct fbd_rule *rule, char *buf, size_t size,
val = ex64lo(skip);
for ( ; size >= sizeof(val); size -= sizeof(val)) {
*((u32_t *) buf) = val ^ 0xdeadbeefUL;
*((uint32_t *) buf) = val ^ 0xdeadbeefUL;
val += sizeof(val);
buf += sizeof(val);
@@ -180,7 +180,7 @@ static void action_pre_misdir(struct fbd_rule *rule, iovec_t *UNUSED(iov),
/* Randomize the request position to fall within the range (and have
* the alignment) given by the rule.
*/
u32_t range, choice;
uint32_t range, choice;
/* Unfortunately, we cannot interpret 0 as end as "up to end of disk"
* here, because we have no idea about the actual disk size, and the

2
minix/drivers/storage/filter/driver.c
View File

@@ -1008,7 +1008,7 @@ void ds_event()
{
char key[DS_MAX_KEYLEN];
char *blkdriver_prefix = "drv.blk.";
u32_t value;
uint32_t value;
int type;
endpoint_t owner_endpoint;
int r;

8
minix/drivers/storage/floppy/floppy.c
View File

@@ -237,7 +237,7 @@ static uint8_t f_results[MAX_RESULTS];/* the controller can give lots of output
* floppy disk drive contains a 'fl_tmr_stop' timer.
*/
static minix_timer_t f_tmr_timeout; /* timer for various timeouts */
static u32_t system_hz; /* system clock frequency */
static uint32_t system_hz; /* system clock frequency */
static void f_expire_tmrs(clock_t stamp);
static void stop_motor(int arg);
static void f_timeout(int arg);
@@ -942,7 +942,7 @@ static int fdc_results(void)
*/
int s, result_nr;
u32_t status;
uint32_t status;
spin_t spin;
/* Extract bytes from FDC until it says it has no more. The loop is
@@ -959,7 +959,7 @@ static int fdc_results(void)
panic("Sys_inb in fdc_results() failed: %d", s);
status &= (MASTER | DIRECTION | CTL_BUSY);
if (status == (MASTER | DIRECTION | CTL_BUSY)) {
u32_t tmp_r;
uint32_t tmp_r;
if (result_nr >= MAX_RESULTS) break; /* too many results */
if ((s=sys_inb(FDC_DATA, &tmp_r)) != OK)
panic("Sys_inb in fdc_results() failed: %d", s);
@@ -1019,7 +1019,7 @@ static void fdc_out(
*/
spin_t spin;
int s;
u32_t status;
uint32_t status;
if (need_reset) return; /* if controller is not listening, return */

4
minix/drivers/storage/memory/memory.c
View File

@@ -517,7 +517,7 @@ static int m_block_ioctl(devminor_t minor, unsigned long request,
* - MIOCRAMSIZE: to set the size of the RAM disk.
*/
struct device *dv;
u32_t ramdev_size;
uint32_t ramdev_size;
int s;
void *mem;
int is_imgrd = 0;
@@ -555,7 +555,7 @@ static int m_block_ioctl(devminor_t minor, unsigned long request,
return(EBUSY);
}
if(m_vaddrs[minor]) {
u32_t a, o;
uint32_t a, o;
u64_t size;
int r;
if(ex64hi(dv->dv_size)) {

14
minix/drivers/storage/mmc/mmchost_mmchs.c
View File

@@ -79,13 +79,13 @@ static struct log log = {
#define HSMMCSD_0_FREQ_50MHZ 50000000 /* 50MHz */
void
mmc_set32(vir_bytes reg, u32_t mask, u32_t value)
mmc_set32(vir_bytes reg, uint32_t mask, uint32_t value)
{
assert(reg >= 0 && reg <= mmchs->io_size);
set32(mmchs->io_base + reg, mask, value);
}
u32_t
uint32_t
mmc_read32(vir_bytes reg)
{
assert(reg >= 0 && reg <= mmchs->io_size);
@@ -93,20 +93,20 @@ mmc_read32(vir_bytes reg)
}
void
mmc_write32(vir_bytes reg, u32_t value)
mmc_write32(vir_bytes reg, uint32_t value)
{
assert(reg >= 0 && reg <= mmchs->io_size);
write32(mmchs->io_base + reg, value);
}
void
mmchs_set_bus_freq(u32_t freq)
mmchs_set_bus_freq(uint32_t freq)
{
u32_t freq_in = HSMMCSD_0_IN_FREQ;
u32_t freq_out = freq;
uint32_t freq_in = HSMMCSD_0_IN_FREQ;
uint32_t freq_out = freq;
/* Calculate and program the divisor */
u32_t clkd = div_roundup(freq_in, freq_out);
uint32_t clkd = div_roundup(freq_in, freq_out);
clkd = (clkd < 2) ? 2 : clkd;
clkd = (clkd > 1023) ? 1023 : clkd;

4
minix/drivers/storage/virtio_blk/virtio_blk.c
View File

@@ -634,7 +634,7 @@ virtio_blk_feature_setup(void)
static int
virtio_blk_config(void)
{
u32_t sectors_low, sectors_high, size_mbs;
uint32_t sectors_low, sectors_high, size_mbs;
/* capacity is always there */
sectors_low = virtio_sread32(blk_dev, 0);
@@ -642,7 +642,7 @@ virtio_blk_config(void)
blk_config.capacity = ((u64_t)sectors_high << 32) | sectors_low;
/* If this gets truncated, you have a big disk... */
size_mbs = (u32_t)(blk_config.capacity * 512 / 1024 / 1024);
size_mbs = (uint32_t)(blk_config.capacity * 512 / 1024 / 1024);
dprintf(("Capacity: %d MB", size_mbs));
/* do feature setup */

20
minix/drivers/storage/virtio_blk/virtio_blk.h
View File

@@ -48,9 +48,9 @@ struct virtio_blk_config {
/* The capacity (in 512-byte sectors). */
u64_t capacity;
/* The maximum segment size (if VIRTIO_BLK_F_SIZE_MAX) */
u32_t size_max;
uint32_t size_max;
/* The maximum number of segments (if VIRTIO_BLK_F_SEG_MAX) */
u32_t seg_max;
uint32_t seg_max;
/* geometry the device (if VIRTIO_BLK_F_GEOMETRY) */
struct virtio_blk_geometry {
uint16_t cylinders;
@@ -59,7 +59,7 @@ struct virtio_blk_config {
} geometry;
/* block size of device (if VIRTIO_BLK_F_BLK_SIZE) */
u32_t blk_size;
uint32_t blk_size;
/* the next 4 entries are guarded by VIRTIO_BLK_F_TOPOLOGY */
/* exponent for physical block per logical block. */
@@ -69,7 +69,7 @@ struct virtio_blk_config {
/* minimum I/O size without performance penalty in logical blocks. */
uint16_t min_io_size;
/* optimal sustained I/O size in logical blocks. */
u32_t opt_io_size;
uint32_t opt_io_size;
} __attribute__((packed));
@@ -103,18 +103,18 @@ struct virtio_blk_config {
/* This is the first element of the read scatter-gather list. */
struct virtio_blk_outhdr {
/* VIRTIO_BLK_T* */
u32_t type;
uint32_t type;
/* io priority. */
u32_t ioprio;
uint32_t ioprio;
/* Sector (ie. 512 byte offset) */
u64_t sector;
};
struct virtio_scsi_inhdr {
u32_t errors;
u32_t data_len;
u32_t sense_len;
u32_t residual;
uint32_t errors;
uint32_t data_len;
uint32_t sense_len;
uint32_t residual;
};
/* And this is the final byte of the write scatter-gather list. */

2
minix/drivers/system/random/main.c
View File

@@ -234,7 +234,7 @@ static void r_random(clock_t UNUSED(stamp))
int s;
static int bin = 0;
static struct k_randomness_bin krandom_bin;
u32_t hi, lo;
uint32_t hi, lo;
rand_t r;
int nextperiod = random_isseeded() ? KRANDOM_PERIOD*500 : KRANDOM_PERIOD;

4
minix/drivers/system/random/random.c
View File

@@ -27,8 +27,8 @@ static SHA256_CTX pool_ctx[NR_POOLS];
static unsigned samples= 0;
static int got_seeded= 0;
static uint8_t random_key[2*AES_BLOCKSIZE];
static u32_t count_lo, count_hi;
static u32_t reseed_count;
static uint32_t count_lo, count_hi;
static uint32_t reseed_count;
static void add_sample(int source, unsigned long sample);
static void data_block(rd_keyinstance *keyp, void *data);

2
minix/drivers/tty/pty/tty.c
View File

@@ -85,7 +85,7 @@ static const char lined[TTLINEDNAMELEN] = "termios"; /* line discipline */
/* Global variables for the TTY task (declared extern in tty.h). */
tty_t tty_table[NR_PTYS];
u32_t system_hz;
uint32_t system_hz;
int tty_gid;
static struct optset optset_table[] = {

2
minix/drivers/tty/pty/tty.h
View File

@@ -85,7 +85,7 @@ typedef struct tty {
/* Memory allocated in tty.c, so extern here. */
extern tty_t tty_table[NR_PTYS];
extern u32_t system_hz; /* system clock frequency */
extern uint32_t system_hz; /* system clock frequency */
extern int tty_gid; /* group ID of the "tty" group */
/* Values for the fields. */

2
minix/drivers/tty/tty/arch/earm/rs232.c
View File

@@ -189,7 +189,7 @@ serial_out(rs232_t *rs, int offset, int val)
static void
rs_reset(rs232_t *rs)
{
u32_t syss;
uint32_t syss;
serial_out(rs, OMAP3_SYSC, UART_SYSC_SOFTRESET);

8
minix/drivers/tty/tty/arch/i386/console.c
View File

@@ -756,7 +756,7 @@ int reg; /* which register pair to set */
unsigned *val; /* 16-bit value to set it to */
{
char v1, v2;
u32_t v;
uint32_t v;
/* Get a register pair inside the 6845. */
sys_outb(vid_port + INDEX, reg);
sys_inb(vid_port + DATA, &v);
@@ -797,7 +797,7 @@ static void beep()
*/
static minix_timer_t tmr_stop_beep;
pvb_pair_t char_out[3];
u32_t port_b_val;
uint32_t port_b_val;
if (beep_disabled()) return;
@@ -868,7 +868,7 @@ clock_t dur;
*/
static minix_timer_t tmr_stop_beep;
pvb_pair_t char_out[3];
u32_t port_b_val;
uint32_t port_b_val;
if (beep_disabled()) return;
@@ -898,7 +898,7 @@ clock_t dur;
static void stop_beep(int arg __unused)
{
/* Turn off the beeper by turning off bits 0 and 1 in PORT_B. */
u32_t port_b_val;
uint32_t port_b_val;
if (sys_inb(PORT_B, &port_b_val)==OK &&
sys_outb(PORT_B, (port_b_val & ~3))==OK)
beeping = FALSE;

14
minix/drivers/tty/tty/arch/i386/rs232.c
View File

@@ -223,7 +223,7 @@ static void rs232_handler(rs232_t *rs);
static int my_inb(port_t port)
{
int r;
u32_t v = 0;
uint32_t v = 0;
r = sys_inb(port, &v);
if (r != OK)
printf("RS232 warning: failed inb 0x%x\n", port);
@@ -443,7 +443,7 @@ static void rs_config(rs232_t *rs)
void rs_init(tty_t *tp)
/* tp which TTY */
{
u32_t dummy;
uint32_t dummy;
/* Initialize RS232 for one line. */
register rs232_t *rs;
@@ -657,7 +657,7 @@ static int rs_break_on(tty_t *tp, int UNUSED(dummy))
{
/* Raise break condition. */
rs232_t *rs = tp->tty_priv;
u32_t line_controls;
uint32_t line_controls;
int s;
if ((s = sys_inb(rs->line_ctl_port, &line_controls)) != OK)
@@ -673,7 +673,7 @@ static int rs_break_off(tty_t *tp, int UNUSED(dummy))
{
/* Clear break condition. */
rs232_t *rs = tp->tty_priv;
u32_t line_controls;
uint32_t line_controls;
int s;
if ((s = sys_inb(rs->line_ctl_port, &line_controls)) != OK)
@@ -708,7 +708,7 @@ static void rs232_handler(struct rs232 *rs)
int trying = 1000;
while (trying--) {
u32_t v;
uint32_t v;
/* Loop to pick up ALL pending interrupts for device.
* This usually just wastes time unless the hardware has a buffer
* (and then we have to worry about being stuck in the loop too long).
@@ -754,7 +754,7 @@ static void in_int(register rs232_t *rs)
* Set a flag for the clock interrupt handler to eventually notify TTY.
*/
int s;
u32_t c;
uint32_t c;
#if 0 /* Enable this if you want serial input in the kernel */
return;
@@ -796,7 +796,7 @@ static void line_int(register rs232_t *rs)
{
/* Check for and record errors. */
int r;
u32_t s;
uint32_t s;
if ((r = sys_inb(rs->line_status_port, &s)) != OK)
printf("TTY: sys_inb() failed: %d", r);

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