[MAJOR] Initial commit for the SPI driver
There are no opportunity to choose the SPI mode and bus speed. It will be added in the future commits (maybe as the ioctl call) It hasn't been debuged yet. Don't use it.
This commit is contained in:
Korobov Nikita
@@ -7,6 +7,7 @@ SUBDIR+= ti1225
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. if ${MACHINE_ARCH} == "earm"
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SUBDIR+= i2c
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SUBDIR+= spi
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. endif # ${MACHINE_ARCH} == "earm"
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.endif # ${MKIMAGEONLY} == "no"
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14
minix/drivers/bus/spi/Makefile
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14
minix/drivers/bus/spi/Makefile
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@@ -0,0 +1,14 @@
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# Makefile for the SPI broadcom driver
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PROG= spi
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SRCS= spi.c
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FILESNAME=${PROG}
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FILESDIR= /etc/system.conf.d
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DPADD+= ${LIBCHARDRIVER} ${LIBSYS}
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LDADD+= -lchardriver -lsys
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# This is a system driver.
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CPPFLAGS+= -D_SYSTEM=1
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.include <minix.service.mk>
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380
minix/drivers/bus/spi/spi.c
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380
minix/drivers/bus/spi/spi.c
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@@ -0,0 +1,380 @@
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#include <minix/drivers.h>
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#include <minix/chardriver.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <minix/ds.h>
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#include <minix/log.h>
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#include <minix/com.h>
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#include <minix/vm.h>
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#include <minix/mmio.h>
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#include <minix/type.h>
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#include <sys/mman.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <minix/padconf.h>
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#include <inttypes.h>
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#include "spi.h"
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/*
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* Function prototypes for the spi driver.
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*/
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static int spi_open(devminor_t minor, int access, endpoint_t user_endpt);
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static int spi_close(devminor_t minor);
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static ssize_t spi_read(devminor_t minor, u64_t position, endpoint_t endpt,
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cp_grant_id_t grant, size_t size, int flags, cdev_id_t id);
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static ssize_t spi_write(devminor_t minor, u64_t position, endpoint_t endpt,
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cp_grant_id_t grant, size_t size, int flags, cdev_id_t id);
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#define COPYBUF_SIZE 0x1000 /* 4k buff */
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static unsigned char copybuf[COPYBUF_SIZE];
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/* SEF functions and variables. */
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static void sef_local_startup(void);
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static int sef_cb_init(int type, sef_init_info_t *info);
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static int sef_cb_lu_state_save(int, int);
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static int lu_state_restore(void);
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/* Entry points to the spi driver. */
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static struct chardriver spi_tab =
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{
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.cdr_open = spi_open,
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.cdr_close = spi_close,
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.cdr_read = spi_read,
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.cdr_write = spi_write,
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};
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typedef struct
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{
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vir_bytes CS;
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vir_bytes FIFO;
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vir_bytes CLK;
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vir_bytes DLEN;
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vir_bytes LTOH;
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vir_bytes DC;
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} spi_regs_t;
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static spi_regs_t spi_reg = {
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.CS = SPI_CS,
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.FIFO = SPI_FIFO,
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.CLK = SPI_CLK,
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.DLEN = SPI_DLEN,
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.LTOH = SPI_LTOH,
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.DC = SPI_DC,
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};
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vir_bytes io_base;
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spi_regs_t *rpi_spi_bus;
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/*
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* Define a structure to be used for logging
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*/
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static struct log log = {
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.name = "spi",
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.log_level = LEVEL_DEBUG,
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.log_func = default_log
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};
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#define div_roundup(x, y) (((x)+((y)-1))/(y))
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static int spi_reset()
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{
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/* Disable interrupts */
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spi_set32(rpi_spi_bus->CS, SPI_CS_INTR | SPI_CS_INTD | SPI_CS_DMAEN | SPI_CS_TA, 0);
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/* Clear fifo */
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spi_set32(rpi_spi_bus->CS, SPI_CS_RX_CLEAR | SPI_CS_TX_CLEAR,
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SPI_CS_RX_CLEAR | SPI_CS_TX_CLEAR);
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spi_write32(rpi_spi_bus->DLEN, 0);
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return OK;
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}
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static void spi_padconf()
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{
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int r;
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uint32_t pinopts;
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pinopts = CONTROL_BCM_CONF_SPI0_MISO |
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CONTROL_BCM_CONF_SPI0_CE1 | CONTROL_BCM_CONF_SPI0_CE0;
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r = sys_padconf(GPFSEL09, pinopts,
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pinopts);
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if (r != OK) {
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log_warn(&log, "padconf failed (r=%d)\n", r);
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}
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log_debug(&log, "pinopts=0x%x\n", pinopts);
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pinopts = CONTROL_BCM_CONF_SPI0_MOSI | CONTROL_BCM_CONF_SPI0_SCLK;
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r = sys_padconf(GPFSEL1019, pinopts,
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pinopts);
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if (r != OK) {
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log_warn(&log, "padconf failed (r=%d)\n", r);
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}
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log_debug(&log, "pinopts=0x%x\n", pinopts);
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}
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static int spi_open(devminor_t UNUSED(minor), int UNUSED(access),
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endpoint_t UNUSED(user_endpt))
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{
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log_debug(&log, "spi_open\n");
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/* Clear fifo */
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spi_set32(rpi_spi_bus->CS, SPI_CS_RX_CLEAR | SPI_CS_TX_CLEAR,
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SPI_CS_RX_CLEAR | SPI_CS_TX_CLEAR);
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return OK;
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}
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static int spi_close(devminor_t UNUSED(minor))
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{
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log_debug(&log, "spi_close\n");
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spi_reset();
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return OK;
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}
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static uint32_t
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spi_poll(uint32_t mask)
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{
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spin_t spin;
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uint32_t status;
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/* poll for up to 1 s */
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spin_init(&spin, 1000000);
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do {
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status = spi_read32(rpi_spi_bus->CS);
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if ((status & mask) != 0) { /* any bits in mask set */
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return status;
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}
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} while (spin_check(&spin));
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return status; /* timeout reached, abort */
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}
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static int spi_read_bytes(uint32_t size)
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{
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int i;
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uint32_t status;
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uint32_t pollmask;
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for(i = 0; i < size; i++) {
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pollmask = SPI_CS_RXD;
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status = spi_poll(pollmask);
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if ((pollmask & status) == 0) {
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log_warn(&log, "Can't wait RXD interrupt. Status = 0x%08x\n", status);
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return (-EIO);
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}
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copybuf[i] = spi_read32(rpi_spi_bus->FIFO);
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pollmask = SPI_CS_DONE;
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status = spi_poll(pollmask);
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if ((pollmask & status) == 0) {
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log_warn(&log, "Can't wait DONE interrupt. Status = 0x%08x\n", status);
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return (-EIO);
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}
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}
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return i;
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}
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static int spi_write_bytes(uint32_t size)
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{
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int i;
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uint32_t status;
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uint32_t pollmask;
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for(i = 0; i < size; i++) {
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pollmask = SPI_CS_TXD;
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status = spi_poll(pollmask);
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if ((pollmask & status) == 0) {
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log_warn(&log, "Can't wait TXD interrupt. Status = 0x%08x\n", status);
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return (-EIO);
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}
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spi_write32(rpi_spi_bus->FIFO, copybuf[i]);
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pollmask = SPI_CS_DONE;
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status = spi_poll(pollmask);
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if ((pollmask & status) == 0) {
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log_warn(&log, "Can't wait DONE interrupt. Status = 0x%08x\n", status);
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return (-EIO);
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}
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}
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return i;
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}
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static int spi_transfer(uint32_t size, int mode)
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{
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int retv;
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spi_set32(rpi_spi_bus->CS, SPI_CS_CS, 0);
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spi_set32(rpi_spi_bus->CS, SPI_CS_MODE, SPI_CS_MODE0);
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/* Start transfer */
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spi_set32(rpi_spi_bus->CS, SPI_CS_TA, SPI_CS_TA);
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log_debug(&log, "size %d\n", size);
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if (mode == WRITE_MODE) {
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retv = spi_write_bytes(size);
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} else {
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spi_set32(rpi_spi_bus->CS, SPI_CS_REN, SPI_CS_REN);
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retv = spi_read_bytes(size);
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}
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if (retv < 0) {
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log_warn(&log, "Transfer failed\n");
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return (-EIO);
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}
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/* Stop transfer */
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spi_set32(rpi_spi_bus->CS, SPI_CS_TA, 0);
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return retv;
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}
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static ssize_t spi_read(devminor_t UNUSED(minor), u64_t position,
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endpoint_t endpt, cp_grant_id_t grant, size_t size, int UNUSED(flags),
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cdev_id_t UNUSED(id))
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{
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int retv;
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log_debug(&log, "spi_read\n");
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if(size < 0 || size > COPYBUF_SIZE) {
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log_warn(&log, "illegal size\n");
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return EINVAL;
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}
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retv = spi_transfer(size, READ_MODE);
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ssize_t ret;
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if ((ret = sys_safecopyto(endpt, grant, 0, (vir_bytes) copybuf, size)) != OK)
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return ret;
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return retv;
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}
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static ssize_t spi_write(devminor_t UNUSED(minor), u64_t position,
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endpoint_t endpt, cp_grant_id_t grant, size_t size, int UNUSED(flags),
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cdev_id_t UNUSED(id))
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{
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int retv;
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log_debug(&log, "spi_write\n");
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if(size < 0 || size > COPYBUF_SIZE) {
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log_warn(&log, "illegal size\n");
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return EINVAL;
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}
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ssize_t ret;
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if ((ret = sys_safecopyfrom(endpt, grant, 0, (vir_bytes) copybuf, size)) != OK)
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return ret;
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retv = spi_transfer(size, WRITE_MODE);
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return retv;
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}
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static void sef_local_startup()
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{
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/*
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* Register init callbacks. Use the same function for all event types
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*/
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sef_setcb_init_fresh(sef_cb_init);
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sef_setcb_init_lu(sef_cb_init);
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sef_setcb_init_restart(sef_cb_init);
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/* Let SEF perform startup. */
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sef_startup();
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}
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static int sef_cb_init(int type, sef_init_info_t *UNUSED(info))
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{
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spi_reset();
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/* 3.9 MHz */
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spi_write32(rpi_spi_bus->CLK, SPI_SPEED_3DOT9);
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/* Enable interrupts */
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spi_set32(rpi_spi_bus->CS, SPI_CS_INTR | SPI_CS_INTD | SPI_CS_DMAEN | SPI_CS_TA,
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SPI_CS_INTR | SPI_CS_INTD | SPI_CS_TA);
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chardriver_announce();
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/* Initialization completed successfully. */
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return OK;
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}
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int main(void)
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{
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struct minix_mem_range mr;
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/* Configure memory access */
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mr.mr_base = SPI_BASE; /* start addr */
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mr.mr_limit = mr.mr_base + SPI_REG_SIZE; /* end addr */
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/* ask for privileges to access the SPI memory range */
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if (sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr) != OK) {
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panic("Unable to obtain spi memory range privileges");
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}
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/* map the memory into this process */
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io_base = (vir_bytes) vm_map_phys(SELF,
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(void *) SPI_BASE, SPI_REG_SIZE);
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if (io_base == (vir_bytes) MAP_FAILED) {
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panic("Unable to map spi registers");
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}
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uint32_t hook_id = 1;
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if (sys_irqsetpolicy(SPI_IRQ, 0, &hook_id) != OK) {
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log_warn(&log, "couldn't set IRQ policy %d\n",
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SPI_IRQ);
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return 1;
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}
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rpi_spi_bus = &spi_reg;
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spi_padconf();
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/*
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* Perform initialization.
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*/
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sef_local_startup();
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/*
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* Run the main loop.
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*/
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chardriver_task(&spi_tab);
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log_debug(&log, "Started\n");
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return OK;
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}
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void
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spi_set32(vir_bytes reg, uint32_t mask, uint32_t value)
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{
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if(reg < 0 || reg > SPI_REG_SIZE) {
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log_warn(&log, "Non-existent register");
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return;
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}
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set32(io_base + reg, mask, value);
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}
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uint32_t
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spi_read32(vir_bytes reg)
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{
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if(reg < 0 || reg > SPI_REG_SIZE) {
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log_warn(&log, "Non-existent register");
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return 0;
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}
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return read32(io_base + reg);
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}
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void
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spi_write32(vir_bytes reg, uint32_t value)
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{
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if(reg < 0 || reg > SPI_REG_SIZE) {
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log_warn(&log, "Non-existent register");
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return;
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}
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write32(io_base + reg, value);
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}
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42
minix/drivers/bus/spi/spi.h
Normal file
42
minix/drivers/bus/spi/spi.h
Normal file
@@ -0,0 +1,42 @@
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#ifndef _SPI_H_
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#define _SPI_H_
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#define SPI_BASE 0x3f204000
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#define SPI_REG_SIZE 0x100
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#define SPI_IRQ 48
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#define SPI_SPEED3DOT9 64
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#define SPI_CS 0x0
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#define SPI_FIFO 0x4
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#define SPI_CLK 0x8
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#define SPI_DLEN 0xc
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#define SPI_LTOH 0x10
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#define SPI_DC 0x14
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#define SPI_CS_CS 0x3
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#define SPI_CS_MODE 0xc
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#define SPI_CS_MODE0 0x0
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#define SPI_CS_MODE1 0x4
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#define SPI_CS_MODE2 0x8
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#define SPI_CS_MODE3 0xc
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#define SPI_CS_TX_CLEAR 0x10
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#define SPI_CS_RX_CLEAR 0x20
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#define SPI_CS_TA 0x80
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#define SPI_CS_DMAEN 0x100
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#define SPI_CS_INTD 0x200
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#define SPI_CS_INTR 0x400
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#define SPI_CS_REN 0x1000
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#define SPI_CS_DONE 0x10000
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#define SPI_CS_RXD 0x20000
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#define SPI_CS_TXD 0x40000
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#define SPI_CS_CSPOL0 0x200000
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#define WRITE_MODE 1
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#define READ_MODE 0
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uint32_t spi_read32(vir_bytes port);
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void spi_write32(vir_bytes port, uint32_t value);
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void spi_set32(vir_bytes port, uint32_t mask, uint32_t value);
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#endif /* _SPI_H_ */
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