ARM/IntegratorCP: Tidying, remove unused code, make the interrupt dispatcher operation more clear.

ports/arm/atomport-asm.s

@@ -37,13 +37,11 @@
 .global    contextEnterCritical
 .global    contextExitCritical
 .global    contextEnableInterrupts
-.global    contextId
 .global    contextStart
 .global    contextSwitch
-.global    contextInit
 
 
-.extern __context_preempt_handler 
+.extern __interrupt_dispatcher 
 
 /**/
 .equ USR_MODE,            0x10
@@ -61,16 +59,6 @@
 .text
 .code 32
 
-/**
- *  \b contextInit
- *
- *  Architecture-specific one time initialization.
- *
- *  @return None
- */
-contextInit:
-
-        BX      lr
 
 /**
  *  \b contextSwitch
@@ -79,8 +67,8 @@ contextInit:
  *
  *  Note that interrupts are always locked out when this routine is
  *  called. For cooperative switches, the scheduler will have entered
- *  a critical region. For preemptions (called from an ISR), the
- *  interrupts will have disabled in the tick_Handler.
+ *  a critical region. For preemptions (called from an ISR), interrupts
+ *  will have been disabled in the IRQ wrapper.
  *
  *  @param[in] [r0] -> Address to save old stack pointer
  *  @param[in] [r1] -> Address where new stack pointer is stored
@@ -96,12 +84,13 @@ contextSwitch:
 
     LDMFD       sp!, {r4 - r11, pc}             /* Load new registers */
 
+
 /**
  *  \b contextStart
  *
  *  Architecture-specific context start routine.
  *
- *  @param[in] [r0] -> Address where stack pointer is stored
+ *  @param[in] [r0] -> Address where new stack pointer is stored
  *
  *  @return Does not return
  */
@@ -110,16 +99,6 @@ contextStart:
     MOV         sp, r0                          /* Load new stack pointer */
     LDMFD       sp!, {r4 - r11, pc}             /* Load new registers */
 
-/**
- *  \b contextId
- *
- *  Returns a unique ID for the context
- *
- *  @return ID
- */
-contextId:
-    MOV         r0, #0
-    BX          lr
 
 /**
  *  \b contextEnableInterrupts
@@ -135,6 +114,7 @@ contextEnableInterrupts:
     MSR         CPSR_c, r0
     BX          lr
 
+
 /**
  *  \b contextExitCritical
  *
@@ -148,6 +128,7 @@ contextExitCritical:
     MSR         CPSR_cxsf, r0
     BX          lr
 
+
 /**
  *  \b contextEnterCritical
  *
@@ -162,15 +143,14 @@ contextEnterCritical:
     BX          lr
 
 
-
 /**
  *  \b archIRQHandler
  *
  *  IRQ entry point.
  *
- *  Save the process/thread context onto its own stackm before calling __context_preempt_handler ().
- *  __context_preempt_handler() might switch stacks. On return the same context is poped from the 
- *  stack and  control is returned to the process.
+ *  Save the process/thread context onto its own stack before calling __interrupt_dispatcher().
+ *  __interrupt_dispatcher() might switch stacks. On return the same context is popped from the 
+ *  stack and control is returned to the process.
  *
  *  @return None
  */
@@ -186,10 +166,11 @@ archIRQHandler:
     MSR         cpsr_c, #(SVC_MODE | I_BIT)     
     STMFD       sp!, {r1, r2}                   
                                                 
-    BL          __context_preempt_handler       /* Dispatch the interrupt to archTickHandler for
+    BL          __interrupt_dispatcher          /* Dispatch the interrupt to platform folder for
                                                    the timer tick interrupt or a simular function
-                                                   for other interrupts which might call atomthread
-                                                   functions. */
+                                                   for other interrupts. Some of those IRQs may
+                                                   call Atomthreads kernel routines and cause a
+                                                   thread switch. */
 
     LDMFD       sp!, {r1, r2}                   /* Restore lr_irq and spsr_irq from process stack */
     MSR         cpsr_c, #(IRQ_MODE | I_BIT)     
@@ -202,5 +183,3 @@ archIRQHandler:
     MSR         cpsr_c, #(IRQ_MODE | I_BIT)     /* Exit from IRQ */
     LDMFD       sp!, {pc}^
 
-
-

ports/arm/atomport-private.h

@@ -32,9 +32,9 @@
 
 
 /* Function prototypes */
-extern void archIRQHandler (void) ;
+extern void archIRQHandler (void);
 
-/* Required interface */
-extern void __context_preempt_handler (void) ;
+/* Platform-specific interrupt dispatcher called on receipt of IRQ */
+extern void __interrupt_dispatcher (void);
 
 #endif /* __ATOM_PORT_PRIVATE_H */

ports/arm/atomport.c

@@ -26,25 +26,24 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
+
 #include "atom.h"
 #include "atomport.h"
 
 
-/* *
- *
- * Functions defined in atomport_s.S
- *
+/**
+ * Functions defined in atomport_s.s
  */
 typedef void * SYSCONTEXT ;
-
 extern void             contextSwitch (SYSCONTEXT* save_context, SYSCONTEXT* new_context) ;
 extern void             contextStart (SYSCONTEXT* context) ;
 extern void             contextEnableInterrupts (void) ;
 
+
 /**
  * \b thread_shell
  *
- * Documented in atomThreads.
+ * Documented in Atomthreads.
  *
  */
 void
@@ -77,7 +76,7 @@ thread_shell (void)
 /**
  * \b archThreadContextInit
  *
- * Documented in atomThreads.
+ * Documented in Atomthreads.
  *
  */
 void
@@ -117,7 +116,7 @@ archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top, void (*entry_point)(u
 /**
  * \b archFirstThreadRestore
  *
- * Documented in atomThreads.
+ * Documented in Atomthreads.
  *
  */
 void
@@ -130,7 +129,7 @@ archFirstThreadRestore(ATOM_TCB * p_sp_new)
 /**
  * \b archContextSwitch
  *
- * Documented in atomThreads.
+ * Documented in Atomthreads.
  *
  */
 void
@@ -138,3 +137,4 @@ archContextSwitch (ATOM_TCB * p_sp_old, ATOM_TCB * p_sp_new)
 {
     contextSwitch (&p_sp_old->sp_save_ptr, &p_sp_new->sp_save_ptr) ;
 }
+

ports/arm/atomport.h

@@ -55,7 +55,6 @@
  * Functions defined in atomport_arm.asm
  *
  */
-extern void						contextInit (void) ;
 extern uint32_t					contextEnterCritical (void) ;
 extern void						contextExitCritical (uint32_t posture) ;
 

ports/arm/platforms/qemu_integratorcp/modules.c

@@ -105,7 +105,7 @@ void _mainCRTStartup(void)
 /**
  * \b low_level_init
  *
- * Initializes the PIC and start the system timer tick intrerupt.
+ * Initializes the PIC and starts the system timer tick interrupt.
  *
  */
 int
@@ -122,7 +122,6 @@ low_level_init (void)
     board_timer_0->CONTROL = ICP_TIMER_CONTROL_ENABLE |
                             ICP_TIMER_CONTROL_MODE |
                             ICP_TIMER_CONTROL_IE |
-                            /*ICP_TIMER_CONTROL_PRESCALE_256 |*/
                             ICP_TIMER_CONTROL_TIMER_SIZE ;
 
     return 0 ;
@@ -130,31 +129,44 @@ low_level_init (void)
 
 
 /**
- * \b __context_preempt_handler
+ * \b __interrupt_dispatcher
  *
- * System timer tic interupt handler.
+ * Interrupt dispatcher: determines the source of the IRQ and calls
+ * the appropriate ISR.
+ *
+ * Currently only the OS system tick ISR is implemented.
+ *
+ * Note that any ISRs which call Atomthreads OS routines that can
+ * cause rescheduling of threads must be surrounded by calls to
+ * atomIntEnter() and atomIntExit().
  *
  */
 void
-__context_preempt_handler (void) 
+__interrupt_dispatcher (void) 
 {
-    unsigned int status = board_pic->IRQ_STATUS ;
+    unsigned int status;
 
-    if (status | ICP_PIC_IRQ_TIMERINT0) {
-        
+    /* Read STATUS register to determine the source of the interrupt */
+    status = board_pic->IRQ_STATUS;
+
+    /* Timer tick interrupt (call Atomthreads timer tick ISR) */
+    if (status | ICP_PIC_IRQ_TIMERINT0)
+    {
+        /*
+         * Let the Atomthreads kernel know we're about to enter an OS-aware
+         * interrupt handler which could cause scheduling of threads.
+         */
         atomIntEnter();
 
         /* Call the OS system tick handler */
         atomTimerTick();
 
-        /* ack the interrupt */
-        board_timer_0->INTCLR = 0x1 ;
+        /* Ack the interrupt */
+        board_timer_0->INTCLR = 0x1;
 
         /* Call the interrupt exit routine */
         atomIntExit(TRUE);
-
     }
 
-
 }