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Renamed directory from arm7a to armv7a to mean "ARM v7 Application" Architecture.

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Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Anup Patel
2011-07-07 17:35:38 +05:30
parent a88b9b542e
commit 1239eb1827
30 changed files with 0 additions and 4226 deletions
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1161
ports/arm7a/Doxyfile
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138
ports/arm7a/Makefile
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##########################################
# Toplevel makefile for all ARM7a boards #
##########################################
# Build directory
ifdef O
build_dir=$(shell readlink -f $(O))
else
build_dir=$(CURDIR)/build
endif
# Source directory
src_dir=$(CURDIR)
# Configuration
CPU=cortex-a8
BOARD=pb-a8
CC=$(CROSS_COMPILE)gcc
OBJCOPY=$(CROSS_COMPILE)objcopy
# Enable stack-checking. WARNING: the full automated test suite currently
# requires a little over 1KB RAM with stack-checking enabled. If you are
# using a device with 1KB internal SRAM and no external SRAM then you
# must disable stack-checking to run all of the automated tests.
#STACK_CHECK=true
# Location of atomthreads sources
board_dir=$(src_dir)/$(BOARD)
kernel_dir=$(src_dir)/../../kernel
tests_dir=$(src_dir)/../../tests
# Check if verbosity is ON for build process
VERBOSE_DEFAULT := 0
CMD_PREFIX_DEFAULT := @
ifdef VERBOSE
ifeq ("$(origin VERBOSE)", "command line")
VB := $(VERBOSE)
else
VB := $(VERBOSE_DEFAULT)
endif
else
VB := $(VERBOSE_DEFAULT)
endif
ifeq ($(VB), 1)
V :=
else
V := $(CMD_PREFIX_DEFAULT)
endif
# object files
objs = arm_irq.o
objs += arm_main.o
objs += atomport.o
objs += arm_entry.o
objs += atomport-asm.o
# include board makefile for board specific objects
-include $(board_dir)/Makefile
# library object files
objs += printk.o
objs += string.o
objs += vsprintf.o
# Kernel object files
objs += atomkernel.o
objs += atomsem.o
objs += atommutex.o
objs += atomtimer.o
objs += atomqueue.o
# Collection of built objects (excluding test applications)
build_objs = $(foreach obj,$(objs),$(build_dir)/$(obj))
# Target application filenames .elf for each test object
tobjs = $(notdir $(patsubst %.c,%.o,$(wildcard $(tests_dir)/*.c)))
telfs = $(patsubst %.o,%.elf,$(tobjs))
build_tobjs = $(foreach tobj,$(tobjs),$(build_dir)/$(tobj))
build_telfs = $(foreach telf,$(telfs),$(build_dir)/$(telf))
# GCC flags
CFLAGS= -g \
-Wall \
-Werror \
-mcpu=$(CPU) \
-nostdinc \
-nostdlib \
-nodefaultlibs \
-fno-builtin \
-I$(src_dir) \
-I$(board_dir) \
-I$(kernel_dir) \
-I$(tests_dir)
# Enable stack-checking (disable if not required)
ifeq ($(STACK_CHECK),true)
CFLAGS += -DATOM_STACK_CHECKING
endif
# All
.PHONY: all
all: $(build_telfs) $(build_tobjs) $(build_objs) Makefile
$(build_dir)/%.elf: $(build_dir)/%.o $(build_objs)
$(V)mkdir -p `dirname $@`
$(if $(V), @echo " (ELF) $(subst $(build_dir)/,,$@)")
$(V)$(CC) $(CFLAGS) $(build_objs) $< -static-libgcc -lgcc -Wl -T linker.ld -o $@
$(build_dir)/%.o: $(src_dir)/%.S
$(V)mkdir -p `dirname $@`
$(if $(V), @echo " (AS) $(subst $(build_dir)/,,$@)")
$(V)$(CC) $(CFLAGS) -D__ASSEMBLY__ -I`dirname $<` -c $< -o $@
$(build_dir)/%.o: $(src_dir)/%.c
$(V)mkdir -p `dirname $@`
$(if $(V), @echo " (CC) $(subst $(build_dir)/,,$@)")
$(V)$(CC) $(CFLAGS) $(CFLAGS) -I`dirname $<` -c $< -o $@
$(build_dir)/%.o: $(kernel_dir)/%.c
$(V)mkdir -p `dirname $@`
$(if $(V), @echo " (CC) $(subst $(build_dir)/,,$@)")
$(V)$(CC) $(CFLAGS) $(CFLAGS) -I`dirname $<` -c $< -o $@
$(build_dir)/%.o: $(tests_dir)/%.c
$(V)mkdir -p `dirname $@`
$(if $(V), @echo " (CC) $(subst $(build_dir)/,,$@)")
$(V)$(CC) $(CFLAGS) $(CFLAGS) -I`dirname $<` -c $< -o $@
# Clean
.PHONY: clean
clean:
rm -rf doxygen-kernel
rm -rf doxygen-avr
rm -rf $(build_dir)
# Docs
.PHONY: doxygen
doxygen:
doxygen $(kernel_dir)/Doxyfile
doxygen ./Doxyfile

123
ports/arm7a/arm_asm_macro.h
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/*
* Copyright (c) 2011, Anup Patel. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARM_ASM_MACRO_H__
#define __ARM_ASM_MACRO_H__
#include <arm_defines.h>
#ifdef __ASSEMBLY__
.macro SET_CURRENT_FLAGS flags, treg
mrs \treg, cpsr
orr \treg, \treg, #(\flags)
msr cpsr, \treg
.endm
.macro SET_CURRENT_MODE mode
cps #(\mode)
.endm
.macro SET_CURRENT_STACK new_stack
ldr sp, \new_stack
.endm
.macro START_EXCEPTION_HANDLER irqname, lroffset
.align 5
\irqname:
sub lr, lr, #\lroffset
.endm
/* Save User Registers */
.macro PUSH_USER_REGS
str lr, [sp, #-4]!; /* Push the return address */
sub sp, sp, #(4*15); /* Adjust the stack pointer */
stmia sp, {r0-r12}; /* Push user mode registers */
add r0, sp, #(4*13); /* Adjust the stack pointer */
stmia r0, {r13-r14}^; /* Push user mode registers */
mov r0, r0; /* NOP for previous inst */
mrs r0, spsr_all; /* Put the SPSR on the stack */
str r0, [sp, #-4]!
.endm
/* If came from priviledged mode then push banked registers */
.macro PUSH_BANKED_REGS skip_lable
mov r4, r0
and r0, r0, #CPSR_MODE_MASK
cmp r0, #CPSR_MODE_USER
beq \skip_lable
add r1, sp, #(4*14)
mrs r5, cpsr
orr r4, r4, #(CPSR_IRQ_DISABLED | CPSR_FIQ_DISABLED)
msr cpsr, r4
str sp, [r1, #0]
str lr, [r1, #4]
msr cpsr, r5
\skip_lable:
.endm
/* Call C function to handle exception */
.macro CALL_EXCEPTION_CFUNC cfunc
mov r0, sp
bl \cfunc
.endm
/* If going back to priviledged mode then pull banked registers */
.macro PULL_BANKED_REGS skip_lable
ldr r0, [sp, #0]
mov r4, r0
and r0, r0, #CPSR_MODE_MASK
cmp r0, #CPSR_MODE_USER
beq \skip_lable
add r1, sp, #(4*14)
mrs r5, cpsr
orr r4, r4, #(CPSR_IRQ_DISABLED | CPSR_FIQ_DISABLED)
msr cpsr, r4
ldr sp, [r1, #0]
ldr lr, [r1, #4]
msr cpsr, r5
\skip_lable:
.endm
/* Restore User Registers */
.macro PULL_USER_REGS
ldr r0, [sp], #0x0004; /* Get SPSR from stack */
msr spsr_all, r0;
ldmia sp, {r0-r14}^; /* Restore registers (user) */
mov r0, r0; /* NOP for previous isnt */
add sp, sp, #(4*15); /* Adjust the stack pointer */
ldr lr, [sp], #0x0004 /* Pull return address */
.endm
.macro END_EXCEPTION_HANDLER
movs pc, lr
.endm
#endif
#endif

68
ports/arm7a/arm_defines.h
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/*
* Copyright (c) 2010, Atomthreads Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARM_DEFINES_H_
#define __ARM_DEFINES_H_
#define CPSR_VALIDBITS_MASK 0xFF0FFFFF
#define CPSR_USERBITS_MASK 0xFFFFFC00
#define CPSR_USERBITS_SHIFT 10
#define CPSR_PRIVBITS_MASK 0x000003FF
#define CPSR_PRIVBITS_SHIFT 0
#define CPSR_MODE_MASK 0x0000001f
#define CPSR_MODE_USER 0x00000010
#define CPSR_MODE_FIQ 0x00000011
#define CPSR_MODE_IRQ 0x00000012
#define CPSR_MODE_SUPERVISOR 0x00000013
#define CPSR_MODE_MONITOR 0x00000016
#define CPSR_MODE_ABORT 0x00000017
#define CPSR_MODE_UNDEFINED 0x0000001b
#define CPSR_MODE_SYSTEM 0x0000001f
#define CPSR_THUMB_ENABLED (1 << 5)
#define CPSR_FIQ_DISABLED (1 << 6)
#define CPSR_IRQ_DISABLED (1 << 7)
#define CPSR_ASYNC_ABORT_DISABLED (1 << 8)
#define CPSR_BE_ENABLED (1 << 9)
#define CPSR_IT2_MASK 0x0000FC00
#define CPSR_IT2_SHIFT 10
#define CPSR_GE_MASK 0x000F0000
#define CPSR_GE_SHIFT 16
#define CPSR_JAZZLE_ENABLED (1 << 24)
#define CPSR_IT1_MASK 0x06000000
#define CPSR_IT1_SHIFT 25
#define CPSR_COND_OVERFLOW_MASK (1 << 28)
#define CPSR_COND_OVERFLOW_SHIFT 28
#define CPSR_COND_CARRY_MASK (1 << 29)
#define CPSR_COND_CARRY_SHIFT 29
#define CPSR_COND_ZERO_MASK (1 << 30)
#define CPSR_COND_ZERO_SHIFT 30
#define CPSR_COND_NEGATIVE_MASK (1 << 31)
#define CPSR_COND_NEGATIVE_SHIFT 31
#endif /* __ARM_DEFINES_H_ */

151
ports/arm7a/arm_entry.S
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/*
* Copyright (c) 2011, Anup Patel. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arm_asm_macro.h>
.section .expvect, "ax", %progbits
.globl _start_vect
_start_vect:
ldr pc, __reset
ldr pc, __undefined_instruction
ldr pc, __software_interrupt
ldr pc, __prefetch_abort
ldr pc, __data_abort
ldr pc, __not_used
ldr pc, __irq
ldr pc, __fiq
__reset:
.word _reset
__undefined_instruction:
.word _undefined_instruction
__software_interrupt:
.word _software_interrupt
__prefetch_abort:
.word _prefetch_abort
__data_abort:
.word _data_abort
__not_used:
.word _not_used
__irq:
.word _irq
__fiq:
.word _fiq
.global _end_vect
_end_vect:
__initial_stack_end:
.word _initial_stack_end
.globl _reset
_reset:
/* Clear a register for temporary usage */
mov r8, #0
/* Disable IRQ & FIQ */
cpsid if
/* Set Supervisor Mode Stack */
SET_CURRENT_MODE CPSR_MODE_SUPERVISOR
SET_CURRENT_STACK __initial_stack_end
/* Set Undefined Mode Stack */
SET_CURRENT_MODE CPSR_MODE_UNDEFINED
SET_CURRENT_STACK __initial_stack_end
/* Set Abort Mode Stack */
SET_CURRENT_MODE CPSR_MODE_ABORT
SET_CURRENT_STACK __initial_stack_end
/* Set IRQ Mode Stack */
SET_CURRENT_MODE CPSR_MODE_IRQ
SET_CURRENT_STACK __initial_stack_end
/* Set FIQ Mode Stack */
SET_CURRENT_MODE CPSR_MODE_FIQ
SET_CURRENT_STACK __initial_stack_end
/* Set System Mode Stack */
SET_CURRENT_MODE CPSR_MODE_SYSTEM
SET_CURRENT_STACK __initial_stack_end
/* Set to Supervisor Mode */
SET_CURRENT_MODE CPSR_MODE_SUPERVISOR
/* Call main function */
bl main
/* We should never reach here */
b .
START_EXCEPTION_HANDLER _undefined_instruction, 4
PUSH_USER_REGS
PUSH_BANKED_REGS _undefined_instruction_bankpush_skip
CALL_EXCEPTION_CFUNC do_undefined_instruction
PULL_BANKED_REGS _undefined_instruction_bankpull_skip
PULL_USER_REGS
END_EXCEPTION_HANDLER
START_EXCEPTION_HANDLER _software_interrupt, 4
PUSH_USER_REGS
PUSH_BANKED_REGS _software_interrupt_bankpush_skip
CALL_EXCEPTION_CFUNC do_software_interrupt
PULL_BANKED_REGS _software_interrupt_bankpull_skip
PULL_USER_REGS
END_EXCEPTION_HANDLER
START_EXCEPTION_HANDLER _prefetch_abort, 4
PUSH_USER_REGS
PUSH_BANKED_REGS _prefetch_abort_bankpush_skip
CALL_EXCEPTION_CFUNC do_prefetch_abort
PULL_BANKED_REGS _prefetch_abort_bankpull_skip
PULL_USER_REGS
END_EXCEPTION_HANDLER
START_EXCEPTION_HANDLER _data_abort, 8
PUSH_USER_REGS
PUSH_BANKED_REGS _data_abort_bankpush_skip
CALL_EXCEPTION_CFUNC do_data_abort
PULL_BANKED_REGS _data_abort_bankpull_skip
PULL_USER_REGS
END_EXCEPTION_HANDLER
START_EXCEPTION_HANDLER _not_used, 4
PUSH_USER_REGS
PUSH_BANKED_REGS _not_used_bankpush_skip
CALL_EXCEPTION_CFUNC do_not_used
PULL_BANKED_REGS _not_used_bankpull_skip
PULL_USER_REGS
END_EXCEPTION_HANDLER
START_EXCEPTION_HANDLER _irq, 4
PUSH_USER_REGS
PUSH_BANKED_REGS _irq_bankpush_skip
CALL_EXCEPTION_CFUNC do_irq
PULL_BANKED_REGS _irq_bankpull_skip
PULL_USER_REGS
END_EXCEPTION_HANDLER
START_EXCEPTION_HANDLER _fiq, 4
PUSH_USER_REGS
PUSH_BANKED_REGS _fiq_bankpush_skip
CALL_EXCEPTION_CFUNC do_fiq
PULL_BANKED_REGS _fiq_bankpull_skip
PULL_USER_REGS
END_EXCEPTION_HANDLER

45
ports/arm7a/arm_io.h
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/*
* Copyright (c) 2011, Anup Patel. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARM_IO_H_
#define __ARM_IO_H_
#include <atomport.h>
static inline uint32_t arm_readl(void * addr)
{
return *((uint32_t *)addr);
}
static inline void arm_writel(uint32_t data, void * addr)
{
*((uint32_t *)addr) = data;
}
#endif /* __ARM_IO_H_ */

201
ports/arm7a/arm_irq.c
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@@ -1,201 +0,0 @@
/*
* Copyright (c) 2011, Anup Patel. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <atom.h>
#include <arm_config.h>
#include <arm_pic.h>
#include <arm_irq.h>
arm_irq_handler_t irq_hndls[NR_IRQS_PBA8];
void do_undefined_instruction(pt_regs_t *regs)
{
/* Call the interrupt entry routine */
atomIntEnter();
/* Call the interrupt exit routine */
atomIntExit(TRUE);
}
void do_software_interrupt(pt_regs_t *regs)
{
/* Call the interrupt entry routine */
atomIntEnter();
/* Call the interrupt exit routine */
atomIntExit(TRUE);
}
void do_prefetch_abort(pt_regs_t *regs)
{
/* Call the interrupt entry routine */
atomIntEnter();
/* Call the interrupt exit routine */
atomIntExit(TRUE);
}
void do_data_abort(pt_regs_t *regs)
{
/* Call the interrupt entry routine */
atomIntEnter();
/* Call the interrupt exit routine */
atomIntExit(TRUE);
}
void do_not_used(pt_regs_t *regs)
{
/* Call the interrupt entry routine */
atomIntEnter();
/* Call the interrupt exit routine */
atomIntExit(TRUE);
}
void do_irq(pt_regs_t *uregs)
{
int rc = 0;
int irq = arm_pic_active_irq();
/* Call the interrupt entry routine */
atomIntEnter();
if (-1 < irq) {
if (irq_hndls[irq]) {
rc = irq_hndls[irq](irq, uregs);
if (rc) {
while (1);
}
}
rc = arm_pic_ack_irq(irq);
if (rc) {
while (1);
}
}
/* Call the interrupt exit routine */
atomIntExit(TRUE);
}
void do_fiq(pt_regs_t *uregs)
{
/* Call the interrupt entry routine */
atomIntEnter();
/* Call the interrupt exit routine */
atomIntExit(TRUE);
}
void arm_irq_init(void)
{
extern uint32_t _start_vect[];
uint32_t *vectors = (uint32_t *)NULL;
uint32_t *vectors_data = vectors + CPU_IRQ_NR;
int vec;
/*
* Loop through the vectors we're taking over, and copy the
* vector's insn and data word.
*/
for (vec = 0; vec < CPU_IRQ_NR; vec++) {
vectors[vec] = _start_vect[vec];
vectors_data[vec] = _start_vect[vec+CPU_IRQ_NR];
}
/*
* Check if verctors are set properly
*/
for (vec = 0; vec < CPU_IRQ_NR; vec++) {
if ((vectors[vec] != _start_vect[vec]) ||
(vectors_data[vec] != _start_vect[vec+CPU_IRQ_NR])) {
/* Hang */
while(1);
}
}
/*
* Reset irq handlers
*/
for (vec = 0; vec < NR_IRQS_PBA8; vec++) {
irq_hndls[vec] = NULL;
}
/*
* Initialize Generic Interrupt Controller
*/
vec = arm_pic_init();
if (vec) {
while(1);
}
}
void arm_irq_register(uint32_t irq, arm_irq_handler_t hndl)
{
int rc = 0;
if (irq < NR_IRQS_PBA8) {
irq_hndls[irq] = hndl;
if (irq_hndls[irq]) {
rc = arm_pic_unmask(irq);
if (rc) {
while (1);
}
}
}
}
void arm_irq_enable(void)
{
__asm( "cpsie if" );
}
void arm_irq_disable(void)
{
__asm( "cpsid if" );
}
irq_flags_t arm_irq_save(void)
{
unsigned long retval;
asm volatile (" mrs %0, cpsr\n\t" " cpsid i" /* Syntax CPSID <iflags> {, #<p_mode>}
* Note: This instruction is supported
* from ARM6 and above
*/
:"=r" (retval)::"memory", "cc");
return retval;
}
void arm_irq_restore(irq_flags_t flags)
{
asm volatile (" msr cpsr_c, %0"::"r" (flags)
:"memory", "cc");
}

57
ports/arm7a/arm_irq.h
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@@ -1,57 +0,0 @@
/*
* Copyright (c) 2011, Anup Patel. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARM_IRQ_H
#define __ARM_IRQ_H
#include <atomport.h>
#include <arm_defines.h>
typedef int (*arm_irq_handler_t) (uint32_t irq_no, pt_regs_t * regs);
#define CPU_IRQ_NR 8
/** IRQ Numbers */
#define ARM_RESET_IRQ 0
#define ARM_UNDEF_INST_IRQ 1
#define ARM_SOFT_IRQ 2
#define ARM_PREFETCH_ABORT_IRQ 3
#define ARM_DATA_ABORT_IRQ 4
#define ARM_NOT_USED_IRQ 5
#define ARM_EXTERNAL_IRQ 6
#define ARM_EXTERNAL_FIQ 7
void arm_irq_init(void);
void arm_irq_register(uint32_t irq_no, arm_irq_handler_t hndl);
void arm_irq_enable(void);
void arm_irq_disable(void);
irq_flags_t arm_irq_save(void);
void arm_irq_restore(irq_flags_t flags);
#endif /* __ARM_IRQ_H */

231
ports/arm7a/arm_main.c
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@@ -1,231 +0,0 @@
/*
* Copyright (c) 2011, Anup Patel. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <atom.h>
#include <atomport.h>
#include <atomtests.h>
#include <atomtimer.h>
#include "system.h"
#include <arm_irq.h>
#include <arm_timer.h>
#include <arm_uart.h>
/* Constants */
/*
* Idle thread stack size
*
* This needs to be large enough to handle any interrupt handlers
* and callbacks called by interrupt handlers (e.g. user-created
* timer callbacks) as well as the saving of all context when
* switching away from this thread.
*
* In this case, the idle stack is allocated on the BSS via the
* idle_thread_stack[] byte array.
*/
#define IDLE_STACK_SIZE_BYTES 8192
/*
* Main thread stack size
*
* Note that this is not a required OS kernel thread - you will replace
* this with your own application thread.
*
* In this case the Main thread is responsible for calling out to the
* test routines. Once a test routine has finished, the test status is
* printed out on the UART and the thread remains running in a loop
* flashing a LED.
*
* The Main thread stack generally needs to be larger than the idle
* thread stack, as not only does it need to store interrupt handler
* stack saves and context switch saves, but the application main thread
* will generally be carrying out more nested function calls and require
* stack for application code local variables etc.
*
* With all OS tests implemented to date on the AVR, the Main thread
* stack has not exceeded 198 bytes. To allow all tests to run we set
* a minimum main thread stack size of 204 bytes. This may increase in
* future as the codebase changes but for the time being is enough to
* cope with all of the automated tests.
*/
#define MAIN_STACK_SIZE_BYTES 8192
/*
* Startup code stack
*
* Some stack space is required at initial startup for running the main()
* routine. This stack space is only temporarily required at first bootup
* and is no longer required as soon as the OS is started. By default
* GCC sets this to the top of RAM (RAMEND) and it grows down from there.
* Because we only need this temporarily, though, it would be wasteful to
* set aside a region at the top of RAM which is not used during runtime.
*
* What we do here is to reuse part of the idle thread's stack during
* initial startup. As soon as we enter the main() routine we move the
* stack pointer to half-way down the idle thread's stack. This is used
* temporarily while calls are made to atomOSInit(), atomThreadCreate()
* and atomOSStart(). Once the OS is started this stack area is no
* longer required, and can be used for its original purpose (for the
* idle thread's stack).
*
* This does mean, however, that we cannot monitor the stack usage of the
* idle thread. Stack usage is monitored by prefilling the stack with a
* known value, and we are obliterating some of that prefilled area by
* using it as our startup stack, so we cannot use the stack-checking API
* to get a true picture of idle thread stack usage. If you wish to
* monitor idle thread stack usage for your applications then you are
* free to use a different region for the startup stack (e.g. set aside
* an area permanently, or place it somewhere you know you can reuse
* later in the application). For the time being, this method gives us a
* simple way of reducing the memory consumption without having to add
* any special AVR-specific considerations to the automated test
* applications.
*
* This optimisation was required to allow some of the larger automated
* test modules to run on devices with 1KB of RAM. You should avoid doing
* this if you can afford to set aside 64 bytes or so, or if you are
* writing your own applications in which you have further control over
* where data is located.
*/
/* Local data */
/* Application threads' TCBs */
static ATOM_TCB main_tcb;
/* Main thread's stack area */
static uint8_t main_thread_stack[MAIN_STACK_SIZE_BYTES];
/* Idle thread's stack area */
static uint8_t idle_thread_stack[IDLE_STACK_SIZE_BYTES];
/* Forward declarations */
static void main_thread_func (uint32_t data);
/**
* \b main
*
* Program entry point.
*
* Sets up the AVR hardware resources (system tick timer interrupt) necessary
* for the OS to be started. Creates an application thread and starts the OS.
*/
int main ( void )
{
int8_t status;
/**
* Note: to protect OS structures and data during initialisation,
* interrupts must remain disabled until the first thread
* has been restored. They are reenabled at the very end of
* the first thread restore, at which point it is safe for a
* reschedule to take place.
*/
/**
* Initialise the OS before creating our threads.
*
* Note that we tell the OS that the idle stack is half its actual
* size. This prevents it prefilling the bottom half with known
* values for stack-checkig purposes, which we cannot allow because
* we are temporarily using it for our own stack. The remainder will
* still be available once the OS is started, this only prevents the
* OS from prefilling it.
*
* If you are not reusing the idle thread's stack during startup then
* you should pass in the correct size here.
*/
status = atomOSInit(&idle_thread_stack[0],
IDLE_STACK_SIZE_BYTES, 0);
if (status == ATOM_OK)
{
arm_irq_init();
arm_timer_init(SYSTEM_TICKS_PER_SEC);
arm_uart_init();
/* Create an application thread */
status = atomThreadCreate(&main_tcb,
TEST_THREAD_PRIO, main_thread_func, 0,
&main_thread_stack[0],
MAIN_STACK_SIZE_BYTES, 0);
if (status == ATOM_OK)
{
arm_timer_enable();
/**
* First application thread successfully created. It is
* now possible to start the OS. Execution will not return
* from atomOSStart(), which will restore the context of
* our application thread and start executing it.
*
* Note that interrupts are still disabled at this point.
* They will be enabled as we restore and execute our first
* thread in archFirstThreadRestore().
*/
atomOSStart();
}
}
while (1);
/* There was an error starting the OS if we reach here */
return (0);
}
/**
* \b main_thread_func
*
* Entry point for main application thread.
*
* This is the first thread that will be executed when the OS is started.
*
* @param[in] data Unused (optional thread entry parameter)
*
* @return None
*/
static void main_thread_func (uint32_t data)
{
/* Put a message out on the UART */
printk("Test Started ... ");
if (test_start() != 0) {
printk("FAILED!\n");
} else {
printk("SUCCESS!\n");
}
printk("Reset your board !!!!!");
/* Test finished so just hang !!! */
while (1);
}

77
ports/arm7a/atomport-asm.S
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@@ -1,77 +0,0 @@
/*
* Copyright (c) 2011, Anup Patel for Atomthreads Project.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arm_asm_macro.h>
.section .text
/**
* int archSetJump(pt_regs_t *regs)
*/
.globl archSetJump
archSetJump:
add r0, r0, #(4 * 16)
str lr, [r0]
sub r0, r0, #(4 * 14)
stm r0, {r1-r14}
mov r0, r0 /* NOP */
str r2, [r1]
mov r2, #0
sub r0, r0, #4
str r2, [r0]
mrs r2, cpsr_all
sub r0, r0, #4
str r2, [r0]
ldr r2, [r1]
mov r0, #1
bx lr
/**
* void archLongJump(pt_regs_t *regs)
*/
.globl archLongJump
archLongJump:
mrs r1, cpsr_all
SET_CURRENT_MODE CPSR_MODE_UNDEFINED
mov sp, r0
SET_CURRENT_MODE CPSR_MODE_ABORT
mov sp, r0
SET_CURRENT_MODE CPSR_MODE_IRQ
mov sp, r0
SET_CURRENT_MODE CPSR_MODE_FIQ
mov sp, r0
msr cpsr_all, r1
ldr r1, [r0], #4 /* Get CPSR from stack */
msr spsr_all, r1
orr r1, r1, #(CPSR_IRQ_DISABLED | CPSR_FIQ_DISABLED)
msr cpsr_all, r1
ldm r0, {r0-r15}^
mov r0, r0 /* NOP */

48
ports/arm7a/atomport-tests.h
View File

@@ -1,48 +0,0 @@
/*
* Copyright (c) 2011, Anup Patel. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ATOM_PORT_TESTS_H
#define __ATOM_PORT_TESTS_H
/* Include Atomthreads kernel API */
#include "atom.h"
/* Logger macro for viewing test results */
/* FIXME: Add uart out routine once uart is supported */
#define ATOMLOG printk
#define _STR
/* Default thread stack size (in bytes) */
#define TEST_THREAD_STACK_SIZE 8192
/* Uncomment to enable logging of stack usage to UART */
/* #define TESTS_LOG_STACK_USAGE */
#endif /* __ATOM_PORT_TESTS_H */

113
ports/arm7a/atomport.c
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@@ -1,113 +0,0 @@
/*
* Copyright (c) 2011, Anup Patel for Atomthreads Project.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <atom.h>
#include <atomport.h>
#include <string.h>
#include <arm_defines.h>
/**
* This function initialises each thread's stack during creation, before the
* thread is first run. New threads are scheduled in using the same
* context-switch function used for threads which were previously scheduled
* out, therefore this function should set up a stack context which looks
* much like a thread which has been scheduled out and had its context saved.
* We fill part of the stack with those registers which are involved in the
* context switch, including appropriate stack or register contents to cause
* the thread to branch to its entry point function when it is scheduled in.
*
* Interrupts should also be enabled whenever a thread is restored, hence
* ports may wish to explicitly include the interrupt-enable register here
* which will be restored when the thread is scheduled in. Other methods
* can be used to enable interrupts, however, without explicitly storing
* it in the thread's context.
*/
void archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top,
void (*entry_point)(UINT32),
UINT32 entry_param)
{
int i;
pt_regs_t *regs = (pt_regs_t *)((uint32_t)stack_top - sizeof(pt_regs_t));
tcb_ptr->sp_save_ptr = stack_top;
regs->cpsr = CPSR_COND_ZERO_MASK |
CPSR_ASYNC_ABORT_DISABLED | CPSR_MODE_SUPERVISOR;
regs->gpr[0] = entry_param;
for (i = 1; i < 13; i++) {
regs->gpr[i] = 0x0;
}
regs->sp = (uint32_t)stack_top - sizeof(pt_regs_t) - 1024;
regs->lr = (uint32_t)entry_point;
regs->pc = (uint32_t)entry_point;
}
extern int archSetJump(pt_regs_t *regs, uint32_t *tmp);
extern void archLongJump(pt_regs_t *regs);
/**
* archFirstThreadRestore(ATOM_TCB *new_tcb)
*
* This function is responsible for restoring and starting the first
* thread the OS runs. It expects to find the thread context exactly
* as it would be if a context save had previously taken place on it.
* The only real difference between this and the archContextSwitch()
* routine is that there is no previous thread for which context must
* be saved.
*
* The final action this function must do is to restore interrupts.
*/
void archFirstThreadRestore(ATOM_TCB *new_tcb)
{
pt_regs_t *regs = (pt_regs_t *)((uint32_t)new_tcb->sp_save_ptr
- sizeof(pt_regs_t));
archLongJump(regs);
}
/**
* Function that performs the contextSwitch. Whether its a voluntary release
* of CPU by thread or a pre-emption, under both conditions this function is
* called. The signature is as follows:
*
* archContextSwitch(ATOM_TCB *old_tcb, ATOM_TCB *new_tcb)
*/
void archContextSwitch(ATOM_TCB *old_tcb, ATOM_TCB *new_tcb)
{
uint32_t tmp = 0x0, lr = 0x0;
pt_regs_t *old_regs = (pt_regs_t *)((uint32_t)old_tcb->sp_save_ptr
- sizeof(pt_regs_t));
pt_regs_t *new_regs = (pt_regs_t *)((uint32_t)new_tcb->sp_save_ptr
- sizeof(pt_regs_t));
asm volatile (" mov %0, lr\n\t" :"=r"(lr):);
if (archSetJump(old_regs, &tmp)) {
old_regs->lr = lr;
archLongJump(new_regs);
}
}

85
ports/arm7a/atomport.h
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@@ -1,85 +0,0 @@
/*
* Copyright (c) 2011, Anup Patel for Atomthreads Project.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ATOM_PORT_H
#define __ATOM_PORT_H
/* Required number of system ticks per second (normally 100 for 10ms tick) */
#define SYSTEM_TICKS_PER_SEC 1000
typedef signed int int32_t;
typedef signed short int16_t;
typedef signed char int8_t;
typedef unsigned int uint32_t;
typedef unsigned short uint16_t;
typedef unsigned char uint8_t;
typedef long long int64_t;
typedef unsigned long size_t;
typedef unsigned int irq_flags_t;
typedef unsigned int virtual_addr_t;
typedef unsigned int virtual_size_t;
typedef unsigned int physical_addr_t;
typedef unsigned int physical_size_t;
typedef unsigned int clock_freq_t;
typedef unsigned long long jiffies_t;
#define UINT32 uint32_t
#define STACK_ALIGN_SIZE sizeof(uint32_t)
#define NULL ((void *)(0))
/**
* Architecture-specific types.
* Most of these are available from stdint.h on this platform, which is
* included above.
*/
#define POINTER void *
struct pt_regs {
uint32_t cpsr; // Current Program Status
uint32_t gpr[13]; // R0 - R12
uint32_t sp;
uint32_t lr;
uint32_t pc;
} __attribute ((packed)) ;
typedef struct pt_regs pt_regs_t;
#include <printk.h>
#include <arm_irq.h>
/* Critical region protection */
#define CRITICAL_STORE irq_flags_t status_flags
#define CRITICAL_START() status_flags = arm_irq_save();
#define CRITICAL_END() arm_irq_restore(status_flags);
/* Uncomment to enable stack-checking */
/* #define ATOM_STACK_CHECKING */
#endif /* __ATOM_PORT_H */

74
ports/arm7a/linker.ld
View File

@@ -1,74 +0,0 @@
/*
* Copyright (c) 2011, Anup Patel. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH("arm")
ENTRY(_start_vect)
SECTIONS
{
. = 0x100000;
.text :
{
*(.expvect)
*(.text)
. = ALIGN(4);
_etext = .;
}
.data :
{
*(.data)
. = ALIGN(4);
_edata = .;
}
.bss :
{
*(.bss)
. = ALIGN(4);
_ebss = .;
}
.rodata :
{
*(.rodata .rodata.*)
. = ALIGN(4);
_erodata = .;
}
.initial_stack :
{
PROVIDE(_initial_stack_start = .);
. = . + 4096;
. = ALIGN(4);
PROVIDE(_initial_stack_end = .);
}
}

9
ports/arm7a/pb-a8/Makefile
View File

@@ -1,9 +0,0 @@
##########################
# Board specific objects #
##########################
# board object files
objs += pb-a8/arm_pic.o
objs += pb-a8/arm_timer.o
objs += pb-a8/arm_uart.o

147
ports/arm7a/pb-a8/arm_config.h
View File

@@ -1,147 +0,0 @@
/**
* Copyright (c) 2011 Anup Patel.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* @file arm_config.h
* @version 1.0
* @author Anup Patel (anup@brainfault.org)
* @brief ARM Platform Configuration Header
*/
#ifndef _ARM_CONFIG_H__
#define _ARM_CONFIG_H__
/*
* Peripheral addresses
*/
#define REALVIEW_PBA8_UART0_BASE 0x10009000 /* UART 0 */
#define REALVIEW_PBA8_UART1_BASE 0x1000A000 /* UART 1 */
#define REALVIEW_PBA8_UART2_BASE 0x1000B000 /* UART 2 */
#define REALVIEW_PBA8_UART3_BASE 0x1000C000 /* UART 3 */
#define REALVIEW_PBA8_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
#define REALVIEW_PBA8_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */
#define REALVIEW_PBA8_WATCHDOG_BASE 0x10010000 /* watchdog interface */
#define REALVIEW_PBA8_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
#define REALVIEW_PBA8_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
#define REALVIEW_PBA8_GPIO0_BASE 0x10013000 /* GPIO port 0 */
#define REALVIEW_PBA8_RTC_BASE 0x10017000 /* Real Time Clock */
#define REALVIEW_PBA8_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */
#define REALVIEW_PBA8_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */
#define REALVIEW_PBA8_SCTL_BASE 0x1001A000 /* System Controller */
#define REALVIEW_PBA8_CLCD_BASE 0x10020000 /* CLCD */
#define REALVIEW_PBA8_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */
#define REALVIEW_PBA8_DMC_BASE 0x100E0000 /* DMC configuration */
#define REALVIEW_PBA8_SMC_BASE 0x100E1000 /* SMC configuration */
#define REALVIEW_PBA8_CAN_BASE 0x100E2000 /* CAN bus */
#define REALVIEW_PBA8_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */
#define REALVIEW_PBA8_FLASH0_BASE 0x40000000
#define REALVIEW_PBA8_FLASH0_SIZE SZ_64M
#define REALVIEW_PBA8_FLASH1_BASE 0x44000000
#define REALVIEW_PBA8_FLASH1_SIZE SZ_64M
#define REALVIEW_PBA8_ETH_BASE 0x4E000000 /* Ethernet */
#define REALVIEW_PBA8_USB_BASE 0x4F000000 /* USB */
#define REALVIEW_PBA8_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */
#define REALVIEW_PBA8_LT_BASE 0xC0000000 /* Logic Tile expansion */
#define REALVIEW_PBA8_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */
#define REALVIEW_PBA8_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */
#define REALVIEW_PBA8_SYS_PLD_CTRL1 0x74
/*
* PBA8 PCI regions
*/
#define REALVIEW_PBA8_PCI_BASE 0x90040000 /* PCI-X Unit base */
#define REALVIEW_PBA8_PCI_IO_BASE 0x90050000 /* IO Region on AHB */
#define REALVIEW_PBA8_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */
#define REALVIEW_PBA8_PCI_BASE_SIZE 0x10000 /* 16 Kb */
#define REALVIEW_PBA8_PCI_IO_SIZE 0x1000 /* 4 Kb */
#define REALVIEW_PBA8_PCI_MEM_SIZE 0x20000000 /* 512 MB */
/*
* Irqs
*/
#define IRQ_PBA8_GIC_START 32
/* L220
#define IRQ_PBA8_L220_EVENT (IRQ_PBA8_GIC_START + 29)
#define IRQ_PBA8_L220_SLAVE (IRQ_PBA8_GIC_START + 30)
#define IRQ_PBA8_L220_DECODE (IRQ_PBA8_GIC_START + 31)
*/
/*
* PB-A8 on-board gic irq sources
*/
#define IRQ_PBA8_WATCHDOG (IRQ_PBA8_GIC_START + 0) /* Watchdog timer */
#define IRQ_PBA8_SOFT (IRQ_PBA8_GIC_START + 1) /* Software interrupt */
#define IRQ_PBA8_COMMRx (IRQ_PBA8_GIC_START + 2) /* Debug Comm Rx interrupt */
#define IRQ_PBA8_COMMTx (IRQ_PBA8_GIC_START + 3) /* Debug Comm Tx interrupt */
#define IRQ_PBA8_TIMER0_1 (IRQ_PBA8_GIC_START + 4) /* Timer 0/1 (default timer) */
#define IRQ_PBA8_TIMER2_3 (IRQ_PBA8_GIC_START + 5) /* Timer 2/3 */
#define IRQ_PBA8_GPIO0 (IRQ_PBA8_GIC_START + 6) /* GPIO 0 */
#define IRQ_PBA8_GPIO1 (IRQ_PBA8_GIC_START + 7) /* GPIO 1 */
#define IRQ_PBA8_GPIO2 (IRQ_PBA8_GIC_START + 8) /* GPIO 2 */
/* 9 reserved */
#define IRQ_PBA8_RTC (IRQ_PBA8_GIC_START + 10) /* Real Time Clock */
#define IRQ_PBA8_SSP (IRQ_PBA8_GIC_START + 11) /* Synchronous Serial Port */
#define IRQ_PBA8_UART0 (IRQ_PBA8_GIC_START + 12) /* UART 0 on development chip */
#define IRQ_PBA8_UART1 (IRQ_PBA8_GIC_START + 13) /* UART 1 on development chip */
#define IRQ_PBA8_UART2 (IRQ_PBA8_GIC_START + 14) /* UART 2 on development chip */
#define IRQ_PBA8_UART3 (IRQ_PBA8_GIC_START + 15) /* UART 3 on development chip */
#define IRQ_PBA8_SCI (IRQ_PBA8_GIC_START + 16) /* Smart Card Interface */
#define IRQ_PBA8_MMCI0A (IRQ_PBA8_GIC_START + 17) /* Multimedia Card 0A */
#define IRQ_PBA8_MMCI0B (IRQ_PBA8_GIC_START + 18) /* Multimedia Card 0B */
#define IRQ_PBA8_AACI (IRQ_PBA8_GIC_START + 19) /* Audio Codec */
#define IRQ_PBA8_KMI0 (IRQ_PBA8_GIC_START + 20) /* Keyboard/Mouse port 0 */
#define IRQ_PBA8_KMI1 (IRQ_PBA8_GIC_START + 21) /* Keyboard/Mouse port 1 */
#define IRQ_PBA8_CHARLCD (IRQ_PBA8_GIC_START + 22) /* Character LCD */
#define IRQ_PBA8_CLCD (IRQ_PBA8_GIC_START + 23) /* CLCD controller */
#define IRQ_PBA8_DMAC (IRQ_PBA8_GIC_START + 24) /* DMA controller */
#define IRQ_PBA8_PWRFAIL (IRQ_PBA8_GIC_START + 25) /* Power failure */
#define IRQ_PBA8_PISMO (IRQ_PBA8_GIC_START + 26) /* PISMO interface */
#define IRQ_PBA8_DoC (IRQ_PBA8_GIC_START + 27) /* Disk on Chip memory controller */
#define IRQ_PBA8_ETH (IRQ_PBA8_GIC_START + 28) /* Ethernet controller */
#define IRQ_PBA8_USB (IRQ_PBA8_GIC_START + 29) /* USB controller */
#define IRQ_PBA8_TSPEN (IRQ_PBA8_GIC_START + 30) /* Touchscreen pen */
#define IRQ_PBA8_TSKPAD (IRQ_PBA8_GIC_START + 31) /* Touchscreen keypad */
/* ... */
#define IRQ_PBA8_PCI0 (IRQ_PBA8_GIC_START + 50)
#define IRQ_PBA8_PCI1 (IRQ_PBA8_GIC_START + 51)
#define IRQ_PBA8_PCI2 (IRQ_PBA8_GIC_START + 52)
#define IRQ_PBA8_PCI3 (IRQ_PBA8_GIC_START + 53)
#define IRQ_PBA8_SMC -1
#define IRQ_PBA8_SCTL -1
#define NR_GIC_PBA8 1
/*
* Only define NR_IRQS if less than NR_IRQS_PBA8
*/
#define NR_IRQS_PBA8 (IRQ_PBA8_GIC_START + 64)
#if !defined(ARM_GIC_NR_IRQS) || (ARM_GIC_NR_IRQS < NR_IRQS_PBA8)
#undef ARM_GIC_NR_IRQS
#define ARM_GIC_NR_IRQS NR_IRQS_PBA8
#endif
#if !defined(ARM_GIC_MAX_NR) || (REALVIEW_GIC_MAX_NR < NR_GIC_PBA8)
#undef ARM_GIC_MAX_NR
#define ARM_GIC_MAX_NR NR_GIC_PBA8
#endif
#endif

247
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@@ -1,247 +0,0 @@
/*
* Copyright (c) 2011, Anup Patel. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arm_config.h>
#include <arm_io.h>
#include <arm_pic.h>
#define max(a,b) ((a) < (b) ? (b) : (a))
struct gic_chip_data {
uint32_t irq_offset;
virtual_addr_t dist_base;
virtual_addr_t cpu_base;
};
static struct gic_chip_data gic_data[ARM_GIC_MAX_NR];
static inline void arm_gic_write(uint32_t val, virtual_addr_t addr)
{
arm_writel(val, (void *)(addr));
}
static inline uint32_t arm_gic_read(virtual_addr_t addr)
{
return arm_readl((void *)(addr));
}
int arm_gic_active_irq(uint32_t gic_nr)
{
int ret = -1;
if (ARM_GIC_MAX_NR <= gic_nr) {
return -1;
}
ret = arm_gic_read(gic_data[gic_nr].cpu_base +
GIC_CPU_INTACK) & 0x3FF;
ret += gic_data[gic_nr].irq_offset;
return ret;
}
int arm_gic_ack_irq(uint32_t gic_nr, uint32_t irq)
{
uint32_t mask = 1 << (irq % 32);
uint32_t gic_irq;
if (ARM_GIC_MAX_NR <= gic_nr) {
return -1;
}
if (irq < gic_data[gic_nr].irq_offset) {
return -1;
}
gic_irq = irq - gic_data[gic_nr].irq_offset;
arm_gic_write(mask, gic_data[gic_nr].dist_base +
GIC_DIST_ENABLE_CLEAR + (gic_irq / 32) * 4);
arm_gic_write(gic_irq, gic_data[gic_nr].cpu_base + GIC_CPU_EOI);
arm_gic_write(mask, gic_data[gic_nr].dist_base +
GIC_DIST_ENABLE_SET + (gic_irq / 32) * 4);
return 0;
}
int arm_gic_mask(uint32_t gic_nr, uint32_t irq)
{
uint32_t mask = 1 << (irq % 32);
uint32_t gic_irq;
if (ARM_GIC_MAX_NR <= gic_nr) {
return -1;
}
if (irq < gic_data[gic_nr].irq_offset) {
return -1;
}
gic_irq = irq - gic_data[gic_nr].irq_offset;
arm_gic_write(mask, gic_data[gic_nr].dist_base +
GIC_DIST_ENABLE_CLEAR + (gic_irq / 32) * 4);
return 0;
}
int arm_gic_unmask(uint32_t gic_nr, uint32_t irq)
{
uint32_t mask = 1 << (irq % 32);
uint32_t gic_irq;
if (ARM_GIC_MAX_NR <= gic_nr) {
return -1;
}
if (irq < gic_data[gic_nr].irq_offset) {
return -1;
}
gic_irq = irq - gic_data[gic_nr].irq_offset;
arm_gic_write(mask, gic_data[gic_nr].dist_base +
GIC_DIST_ENABLE_SET + (gic_irq / 32) * 4);
return 0;
}
int arm_gic_dist_init(uint32_t gic_nr, virtual_addr_t base, uint32_t irq_start)
{
unsigned int max_irq, i;
uint32_t cpumask = 1 << 0; /*smp_processor_id(); */
if (ARM_GIC_MAX_NR <= gic_nr) {
return -1;
}
cpumask |= cpumask << 8;
cpumask |= cpumask << 16;
gic_data[gic_nr].dist_base = base;
gic_data[gic_nr].irq_offset = (irq_start - 1) & ~31;
arm_gic_write(0, base + GIC_DIST_CTRL);
/*
* Find out how many interrupts are supported.
*/
max_irq = arm_gic_read(base + GIC_DIST_CTR) & 0x1f;
max_irq = (max_irq + 1) * 32;
/*
* The GIC only supports up to 1020 interrupt sources.
* Limit this to either the architected maximum, or the
* platform maximum.
*/
if (max_irq > max(1020, ARM_GIC_NR_IRQS))
max_irq = max(1020, ARM_GIC_NR_IRQS);
/*
* Set all global interrupts to be level triggered, active low.
*/
for (i = 32; i < max_irq; i += 16)
arm_gic_write(0, base + GIC_DIST_CONFIG + i * 4 / 16);
/*
* Set all global interrupts to this CPU only.
*/
for (i = 32; i < max_irq; i += 4)
arm_gic_write(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
/*
* Set priority on all interrupts.
*/
for (i = 0; i < max_irq; i += 4)
arm_gic_write(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
/*
* Disable all interrupts.
*/
for (i = 0; i < max_irq; i += 32)
arm_gic_write(0xffffffff,
base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
arm_gic_write(1, base + GIC_DIST_CTRL);
return 0;
}
int arm_gic_cpu_init(uint32_t gic_nr, virtual_addr_t base)
{
if (ARM_GIC_MAX_NR <= gic_nr) {
return -1;
}
gic_data[gic_nr].cpu_base = base;
arm_gic_write(0xf0, base + GIC_CPU_PRIMASK);
arm_gic_write(1, base + GIC_CPU_CTRL);
return 0;
}
int arm_pic_active_irq(void)
{
return arm_gic_active_irq(0);
}
int arm_pic_ack_irq(uint32_t irq)
{
return arm_gic_ack_irq(0, irq);
}
int arm_pic_mask(uint32_t irq)
{
return arm_gic_mask(0, irq);
}
int arm_pic_unmask(uint32_t irq)
{
return arm_gic_unmask(0, irq);
}
int arm_pic_init(void)
{
int rc = 0;
rc = arm_gic_dist_init(0, REALVIEW_PBA8_GIC_DIST_BASE,
IRQ_PBA8_GIC_START);
if (rc) {
return rc;
}
rc = arm_gic_cpu_init(0, REALVIEW_PBA8_GIC_CPU_BASE);
if (rc) {
while(1);
}
return rc;
}

61
ports/arm7a/pb-a8/arm_pic.h
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/*
* Copyright (c) 2011, Anup Patel. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_GIC_H__
#define _ARM_GIC_H__
#include <atomport.h>
#include <arm_plat.h>
#define GIC_CPU_CTRL 0x00
#define GIC_CPU_PRIMASK 0x04
#define GIC_CPU_BINPOINT 0x08
#define GIC_CPU_INTACK 0x0c
#define GIC_CPU_EOI 0x10
#define GIC_CPU_RUNNINGPRI 0x14
#define GIC_CPU_HIGHPRI 0x18
#define GIC_DIST_CTRL 0x000
#define GIC_DIST_CTR 0x004
#define GIC_DIST_ENABLE_SET 0x100
#define GIC_DIST_ENABLE_CLEAR 0x180
#define GIC_DIST_PENDING_SET 0x200
#define GIC_DIST_PENDING_CLEAR 0x280
#define GIC_DIST_ACTIVE_BIT 0x300
#define GIC_DIST_PRI 0x400
#define GIC_DIST_TARGET 0x800
#define GIC_DIST_CONFIG 0xc00
#define GIC_DIST_SOFTINT 0xf00
int arm_pic_active_irq(void);
int arm_pic_ack_irq(uint32_t irq);
int arm_pic_mask(uint32_t irq);
int arm_pic_unmask(uint32_t irq);
int arm_pic_init(void);
#endif

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ports/arm7a/pb-a8/arm_plat.h
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/*
* Copyright (c) 2011, Anup Patel. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_PLAT_H__
#define _ARM_PLAT_H__
/*
* Memory definitions
*/
#define REALVIEW_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)... */
#define REALVIEW_BOOT_ROM_HI 0x30000000
#define REALVIEW_BOOT_ROM_BASE REALVIEW_BOOT_ROM_HI /* Normal position */
#define REALVIEW_BOOT_ROM_SIZE SZ_64M
#define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */
#define REALVIEW_SSRAM_SIZE SZ_2M
/*
* SDRAM
*/
#define REALVIEW_SDRAM_BASE 0x00000000
/*
* Logic expansion modules
*
*/
/* ------------------------------------------------------------------------
* RealView Registers
* ------------------------------------------------------------------------
*
*/
#define REALVIEW_SYS_ID_OFFSET 0x00
#define REALVIEW_SYS_SW_OFFSET 0x04
#define REALVIEW_SYS_LED_OFFSET 0x08
#define REALVIEW_SYS_OSC0_OFFSET 0x0C
#define REALVIEW_SYS_OSC1_OFFSET 0x10
#define REALVIEW_SYS_OSC2_OFFSET 0x14
#define REALVIEW_SYS_OSC3_OFFSET 0x18
#define REALVIEW_SYS_OSC4_OFFSET 0x1C /* OSC1 for RealView/AB */
#define REALVIEW_SYS_LOCK_OFFSET 0x20
#define REALVIEW_SYS_100HZ_OFFSET 0x24
#define REALVIEW_SYS_CFGDATA1_OFFSET 0x28
#define REALVIEW_SYS_CFGDATA2_OFFSET 0x2C
#define REALVIEW_SYS_FLAGS_OFFSET 0x30
#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30
#define REALVIEW_SYS_FLAGSCLR_OFFSET 0x34
#define REALVIEW_SYS_NVFLAGS_OFFSET 0x38
#define REALVIEW_SYS_NVFLAGSSET_OFFSET 0x38
#define REALVIEW_SYS_NVFLAGSCLR_OFFSET 0x3C
#define REALVIEW_SYS_RESETCTL_OFFSET 0x40
#define REALVIEW_SYS_PCICTL_OFFSET 0x44
#define REALVIEW_SYS_MCI_OFFSET 0x48
#define REALVIEW_SYS_FLASH_OFFSET 0x4C
#define REALVIEW_SYS_CLCD_OFFSET 0x50
#define REALVIEW_SYS_CLCDSER_OFFSET 0x54
#define REALVIEW_SYS_BOOTCS_OFFSET 0x58
#define REALVIEW_SYS_24MHz_OFFSET 0x5C
#define REALVIEW_SYS_MISC_OFFSET 0x60
#define REALVIEW_SYS_IOSEL_OFFSET 0x70
#define REALVIEW_SYS_PROCID_OFFSET 0x84
#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0
#define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4
#define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8
#define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC
#define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0
#define REALVIEW_SYS_BASE 0x10000000
#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
#define REALVIEW_SYS_SW (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET)
#define REALVIEW_SYS_LED (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET)
#define REALVIEW_SYS_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET)
#define REALVIEW_SYS_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET)
#define REALVIEW_SYS_LOCK (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET)
#define REALVIEW_SYS_100HZ (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET)
#define REALVIEW_SYS_CFGDATA1 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET)
#define REALVIEW_SYS_CFGDATA2 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET)
#define REALVIEW_SYS_FLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET)
#define REALVIEW_SYS_FLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET)
#define REALVIEW_SYS_FLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET)
#define REALVIEW_SYS_NVFLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET)
#define REALVIEW_SYS_NVFLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET)
#define REALVIEW_SYS_NVFLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET)
#define REALVIEW_SYS_RESETCTL (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET)
#define REALVIEW_SYS_PCICTL (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET)
#define REALVIEW_SYS_MCI (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET)
#define REALVIEW_SYS_FLASH (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET)
#define REALVIEW_SYS_CLCD (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET)
#define REALVIEW_SYS_CLCDSER (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET)
#define REALVIEW_SYS_BOOTCS (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET)
#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
#define REALVIEW_SYS_TEST_OSC3 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET)
#define REALVIEW_SYS_TEST_OSC4 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET)
/*
* Values for REALVIEW_SYS_RESET_CTRL
*/
#define REALVIEW_SYS_CTRL_RESET_CONFIGCLR 0x01
#define REALVIEW_SYS_CTRL_RESET_CONFIGINIT 0x02
#define REALVIEW_SYS_CTRL_RESET_DLLRESET 0x03
#define REALVIEW_SYS_CTRL_RESET_PLLRESET 0x04
#define REALVIEW_SYS_CTRL_RESET_POR 0x05
#define REALVIEW_SYS_CTRL_RESET_DoC 0x06
#define REALVIEW_SYS_CTRL_LED (1 << 0)
/* ------------------------------------------------------------------------
* RealView control registers
* ------------------------------------------------------------------------
*/
/*
* REALVIEW_IDFIELD
*
* 31:24 = manufacturer (0x41 = ARM)
* 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
* 15:12 = FPGA (0x3 = XVC600 or XVC600E)
* 11:4 = build value
* 3:0 = revision number (0x1 = rev B (AHB))
*/
/*
* REALVIEW_SYS_LOCK
* control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
* SYS_CLD, SYS_BOOTCS
*/
#define REALVIEW_SYS_LOCK_LOCKED (1 << 16)
#define REALVIEW_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */
/*
* REALVIEW_SYS_FLASH
*/
#define REALVIEW_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
/*
* REALVIEW_INTREG
* - used to acknowledge and control MMCI and UART interrupts
*/
#define REALVIEW_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */
#define REALVIEW_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */
#define REALVIEW_INTREG_CARDIN 0x08 /* MMCI card in detect */
/* write 1 to acknowledge and clear */
#define REALVIEW_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */
#define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */
/*
* RealView common peripheral addresses
*/
#define REALVIEW_SCTL_BASE 0x10001000 /* System controller */
#define REALVIEW_I2C_BASE 0x10002000 /* I2C control */
#define REALVIEW_AACI_BASE 0x10004000 /* Audio */
#define REALVIEW_MMCI0_BASE 0x10005000 /* MMC interface */
#define REALVIEW_KMI0_BASE 0x10006000 /* KMI interface */
#define REALVIEW_KMI1_BASE 0x10007000 /* KMI 2nd interface */
#define REALVIEW_CHAR_LCD_BASE 0x10008000 /* Character LCD */
#define REALVIEW_SCI_BASE 0x1000E000 /* Smart card controller */
#define REALVIEW_GPIO1_BASE 0x10014000 /* GPIO port 1 */
#define REALVIEW_GPIO2_BASE 0x10015000 /* GPIO port 2 */
#define REALVIEW_DMC_BASE 0x10018000 /* DMC configuration */
#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */
/* PCI space */
#define REALVIEW_PCI_BASE 0x41000000 /* PCI Interface */
#define REALVIEW_PCI_CFG_BASE 0x42000000
#define REALVIEW_PCI_MEM_BASE0 0x44000000
#define REALVIEW_PCI_MEM_BASE1 0x50000000
#define REALVIEW_PCI_MEM_BASE2 0x60000000
/* Sizes of above maps */
#define REALVIEW_PCI_BASE_SIZE 0x01000000
#define REALVIEW_PCI_CFG_BASE_SIZE 0x02000000
#define REALVIEW_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */
#define REALVIEW_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */
#define REALVIEW_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */
#define REALVIEW_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
#define REALVIEW_LT_BASE 0x80000000 /* Logic Tile expansion */
/*
* CompactFlash
*/
#define REALVIEW_CF_BASE 0x18000000 /* CompactFlash */
#define REALVIEW_CF_MEM_BASE 0x18003000 /* SMC for CompactFlash */
/*
* Disk on Chip
*/
#define REALVIEW_DOC_BASE 0x2C000000
#define REALVIEW_DOC_SIZE (16 << 20)
#define REALVIEW_DOC_PAGE_SIZE 512
#define REALVIEW_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE)
#define ERASE_UNIT_PAGES 32
#define START_PAGE 0x80
/*
* LED settings, bits [7:0]
*/
#define REALVIEW_SYS_LED0 (1 << 0)
#define REALVIEW_SYS_LED1 (1 << 1)
#define REALVIEW_SYS_LED2 (1 << 2)
#define REALVIEW_SYS_LED3 (1 << 3)
#define REALVIEW_SYS_LED4 (1 << 4)
#define REALVIEW_SYS_LED5 (1 << 5)
#define REALVIEW_SYS_LED6 (1 << 6)
#define REALVIEW_SYS_LED7 (1 << 7)
#define ALL_LEDS 0xFF
#define LED_BANK REALVIEW_SYS_LED
/*
* Control registers
*/
#define REALVIEW_IDFIELD_OFFSET 0x0 /* RealView build information */
#define REALVIEW_FLASHPROG_OFFSET 0x4 /* Flash devices */
#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */
#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */
/*
* Clean base - dummy
*
*/
#define CLEAN_BASE REALVIEW_BOOT_ROM_HI
/*
* System controller bit assignment
*/
#define REALVIEW_REFCLK 0
#define REALVIEW_TIMCLK 1
#define REALVIEW_TIMER1_EnSel 15
#define REALVIEW_TIMER2_EnSel 17
#define REALVIEW_TIMER3_EnSel 19
#define REALVIEW_TIMER4_EnSel 21
#define MAX_TIMER 2
#define MAX_PERIOD 699050
#define TICKS_PER_uSEC 1
/*
* These are useconds NOT ticks.
*
*/
#define mSEC_1 1000
#define mSEC_5 (mSEC_1 * 5)
#define mSEC_10 (mSEC_1 * 10)
#define mSEC_25 (mSEC_1 * 25)
#define SEC_1 (mSEC_1 * 1000)
#define REALVIEW_CSR_BASE 0x10000000
#define REALVIEW_CSR_SIZE 0x10000000
#endif

97
ports/arm7a/pb-a8/arm_timer.c
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@@ -1,97 +0,0 @@
/*
* Copyright (c) 2011, Anup Patel. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <atom.h>
#include <atomport.h>
#include <arm_io.h>
#include <arm_irq.h>
#include <arm_config.h>
#include <arm_plat.h>
#include <arm_timer.h>
unsigned long long jiffies;
void arm_timer_enable(void)
{
uint32_t ctrl;
ctrl = arm_readl((void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_CTRL));
ctrl |= TIMER_CTRL_ENABLE;
arm_writel(ctrl, (void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_CTRL));
}
void arm_timer_disable(void)
{
uint32_t ctrl;
ctrl = arm_readl((void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_CTRL));
ctrl &= ~TIMER_CTRL_ENABLE;
arm_writel(ctrl, (void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_CTRL));
}
void arm_timer_clearirq(void)
{
arm_writel(1, (void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_INTCLR));
}
int arm_timer_irqhndl(uint32_t irq_no, pt_regs_t * regs)
{
/* Call the OS system tick handler */
atomTimerTick();
arm_timer_clearirq();
return 0;
}
int arm_timer_init(uint32_t ticks_per_sec)
{
uint32_t val;
/*
* set clock frequency:
* REALVIEW_TIMCLK is 1MHz
*/
val = arm_readl((void *)REALVIEW_SCTL_BASE) | (REALVIEW_TIMCLK << 0x1);
arm_writel(val, (void *)REALVIEW_SCTL_BASE);
/* Register interrupt handler */
arm_irq_register(IRQ_PBA8_TIMER0_1, &arm_timer_irqhndl);
val = arm_readl((void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_CTRL));
val &= ~TIMER_CTRL_ENABLE;
val |= (TIMER_CTRL_32BIT | TIMER_CTRL_PERIODIC | TIMER_CTRL_IE);
arm_writel(val, (void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_CTRL));
arm_writel((1000000 / ticks_per_sec),
(void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_LOAD));
arm_writel((1000000 / ticks_per_sec),
(void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_VALUE));
return 0;
}

56
ports/arm7a/pb-a8/arm_timer.h
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@@ -1,56 +0,0 @@
/*
* Copyright (c) 2011, Anup Patel. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARM_TIMER_H
#define __ARM_TIMER_H
#include <atomport.h>
#define TIMER_LOAD 0x00
#define TIMER_VALUE 0x04
#define TIMER_CTRL 0x08
#define TIMER_CTRL_ONESHOT (1 << 0)
#define TIMER_CTRL_32BIT (1 << 1)
#define TIMER_CTRL_DIV1 (0 << 2)
#define TIMER_CTRL_DIV16 (1 << 2)
#define TIMER_CTRL_DIV256 (2 << 2)
#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */
#define TIMER_CTRL_PERIODIC (1 << 6)
#define TIMER_CTRL_ENABLE (1 << 7)
#define TIMER_INTCLR 0x0c
#define TIMER_RIS 0x10
#define TIMER_MIS 0x14
#define TIMER_BGLOAD 0x18
void arm_timer_enable(void);
void arm_timer_disable(void);
void arm_timer_clearirq(void);
int arm_timer_init(uint32_t ticks_per_sec);
#endif /* __ARM_TIMER_H */

112
ports/arm7a/pb-a8/arm_uart.c
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@@ -1,112 +0,0 @@
/*
* Copyright (c) 2011, Anup Patel. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arm_io.h>
#include <arm_uart.h>
void arm_uart_putc(uint8_t ch)
{
unsigned int base = 0x10009000;
if(ch=='\n') {
/* Wait until there is space in the FIFO */
while (arm_readl((void*)(base + UART_PL01x_FR)) & UART_PL01x_FR_TXFF);
/* Send the character */
arm_writel('\r', (void*)(base + UART_PL01x_DR));
}
/* Wait until there is space in the FIFO */
while (arm_readl((void*)(base + UART_PL01x_FR)) & UART_PL01x_FR_TXFF);
/* Send the character */
arm_writel(ch, (void*)(base + UART_PL01x_DR));
}
uint8_t arm_uart_getc(void)
{
unsigned int base = 0x10009000;
uint8_t data;
/* Wait until there is data in the FIFO */
while (arm_readl((void*)(base + UART_PL01x_FR)) & UART_PL01x_FR_RXFE);
data = arm_readl((void*)(base + UART_PL01x_DR));
/* Check for an error flag */
if (data & 0xFFFFFF00) {
/* Clear the error */
arm_writel(0xFFFFFFFF, (void*)(base + UART_PL01x_ECR));
return -1;
}
return data;
}
void arm_uart_init(void)
{
unsigned int base = 0x10009000;
unsigned int baudrate = 115200;
unsigned int input_clock = 24000000;
unsigned int divider;
unsigned int temp;
unsigned int remainder;
unsigned int fraction;
/* First, disable everything */
arm_writel(0x0, (void*)(base + UART_PL011_CR));
/*
* Set baud rate
*
* IBRD = UART_CLK / (16 * BAUD_RATE)
* FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
* / (16 * BAUD_RATE))
*/
temp = 16 * baudrate;
divider = input_clock / temp;
remainder = input_clock % temp;
temp = (8 * remainder) / baudrate;
fraction = (temp >> 1) + (temp & 1);
arm_writel(divider, (void*)(base + UART_PL011_IBRD));
arm_writel(fraction, (void*)(base + UART_PL011_FBRD));
/* Set the UART to be 8 bits, 1 stop bit,
* no parity, fifo enabled
*/
arm_writel((UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN),
(void*)(base + UART_PL011_LCRH));
/* Finally, enable the UART */
arm_writel((UART_PL011_CR_UARTEN |
UART_PL011_CR_TXE |
UART_PL011_CR_RXE),
(void*)(base + UART_PL011_CR));
}

110
ports/arm7a/pb-a8/arm_uart.h
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@@ -1,110 +0,0 @@
/*
* Copyright (c) 2011, Anup Patel. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARM_UART_H_
#define __ARM_UART_H_
#include <atomport.h>
/*
* ARM PrimeCell UART's (PL010 & PL011)
* ------------------------------------
*
* Definitions common to both PL010 & PL011
*
*/
#define UART_PL01x_DR 0x00 /* Data read or written from the interface. */
#define UART_PL01x_RSR 0x04 /* Receive status register (Read). */
#define UART_PL01x_ECR 0x04 /* Error clear register (Write). */
#define UART_PL01x_FR 0x18 /* Flag register (Read only). */
#define UART_PL01x_RSR_OE 0x08
#define UART_PL01x_RSR_BE 0x04
#define UART_PL01x_RSR_PE 0x02
#define UART_PL01x_RSR_FE 0x01
#define UART_PL01x_FR_TXFE 0x80
#define UART_PL01x_FR_RXFF 0x40
#define UART_PL01x_FR_TXFF 0x20
#define UART_PL01x_FR_RXFE 0x10
#define UART_PL01x_FR_BUSY 0x08
#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY)
/*
* PL011 definitions
*
*/
#define UART_PL011_IBRD 0x24
#define UART_PL011_FBRD 0x28
#define UART_PL011_LCRH 0x2C
#define UART_PL011_CR 0x30
#define UART_PL011_IMSC 0x38
#define UART_PL011_PERIPH_ID0 0xFE0
#define UART_PL011_LCRH_SPS (1 << 7)
#define UART_PL011_LCRH_WLEN_8 (3 << 5)
#define UART_PL011_LCRH_WLEN_7 (2 << 5)
#define UART_PL011_LCRH_WLEN_6 (1 << 5)
#define UART_PL011_LCRH_WLEN_5 (0 << 5)
#define UART_PL011_LCRH_FEN (1 << 4)
#define UART_PL011_LCRH_STP2 (1 << 3)
#define UART_PL011_LCRH_EPS (1 << 2)
#define UART_PL011_LCRH_PEN (1 << 1)
#define UART_PL011_LCRH_BRK (1 << 0)
#define UART_PL011_CR_CTSEN (1 << 15)
#define UART_PL011_CR_RTSEN (1 << 14)
#define UART_PL011_CR_OUT2 (1 << 13)
#define UART_PL011_CR_OUT1 (1 << 12)
#define UART_PL011_CR_RTS (1 << 11)
#define UART_PL011_CR_DTR (1 << 10)
#define UART_PL011_CR_RXE (1 << 9)
#define UART_PL011_CR_TXE (1 << 8)
#define UART_PL011_CR_LPE (1 << 7)
#define UART_PL011_CR_IIRLP (1 << 2)
#define UART_PL011_CR_SIREN (1 << 1)
#define UART_PL011_CR_UARTEN (1 << 0)
#define UART_PL011_IMSC_OEIM (1 << 10)
#define UART_PL011_IMSC_BEIM (1 << 9)
#define UART_PL011_IMSC_PEIM (1 << 8)
#define UART_PL011_IMSC_FEIM (1 << 7)
#define UART_PL011_IMSC_RTIM (1 << 6)
#define UART_PL011_IMSC_TXIM (1 << 5)
#define UART_PL011_IMSC_RXIM (1 << 4)
#define UART_PL011_IMSC_DSRMIM (1 << 3)
#define UART_PL011_IMSC_DCDMIM (1 << 2)
#define UART_PL011_IMSC_CTSMIM (1 << 1)
#define UART_PL011_IMSC_RIMIM (1 << 0)
uint8_t arm_uart_getc(void);
void arm_uart_putc(uint8_t ch);
void arm_uart_init(void);
#endif /* __ARM_UART_H_ */

59
ports/arm7a/printk.c
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@@ -1,59 +0,0 @@
/*
* Copyright (c) Himanshu Chauhan 2009-11.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Himanshu Chauhan nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <system.h>
#include <atomport.h>
#include <stdarg.h>
#include <arm_uart.h>
static int8_t buf[2048];
/* Uses the above routine to output a string... */
void puts(const uint8_t *text)
{
int32_t i;
for (i = 0; i < strlen((const int8_t *)text); i++) {
arm_uart_putc(text[i]);
}
}
void printk(const char *format, ...)
{
va_list args;
int i;
va_start(args, format);
i = vsprintf(buf, (const int8_t *)format, args);
va_end(args);
puts((const uint8_t *)buf);
}

42
ports/arm7a/printk.h
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@@ -1,42 +0,0 @@
/*
* This file is part of Freax kernel.
*
* Copyright (c) Himanshu Chauhan 2009-10.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Himanshu Chauhan nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _PRINTK_H
#define _PRINTK_H
#include "atomport.h"
extern void putch (uint8_t ch);
extern void puts (const uint8_t *text);
extern void printk (const char*format, ...);
#endif

28
ports/arm7a/stdarg.h
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@@ -1,28 +0,0 @@
#ifndef _STDARG_H
#define _STDARG_H
typedef char *va_list;
/* Amount of space required in an argument list for an arg of type TYPE.
TYPE may alternatively be an expression whose type is used. */
#define __va_rounded_size(TYPE) \
(((sizeof (TYPE) + sizeof (int) - 1) / sizeof (int)) * sizeof (int))
#ifndef __sparc__
#define va_start(AP, LASTARG) \
(AP = ((char *) &(LASTARG) + __va_rounded_size (LASTARG)))
#else
#define va_start(AP, LASTARG) \
(__builtin_saveregs (), \
AP = ((char *) &(LASTARG) + __va_rounded_size (LASTARG)))
#endif
void va_end (va_list); /* Defined in gnulib */
#define va_end(AP)
#define va_arg(AP, TYPE) \
(AP += __va_rounded_size (TYPE), \
*((TYPE *) (AP - __va_rounded_size (TYPE))))
#endif /* _STDARG_H */

61
ports/arm7a/string.c
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@@ -1,61 +0,0 @@
/*
* Copyright (c) Himanshu Chauhan 2009-11.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Himanshu Chauhan nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <atomport.h>
#include <system.h>
void *memcpy(void *dest, const void *src, size_t count)
{
const int8_t *sp = (const int8_t *)src;
int8_t *dp = (int8_t *)dest;
for(; count != 0; count--) *dp++ = *sp++;
return dest;
}
void *memset(void *dest, int8_t val, size_t count)
{
int8_t *temp = (int8_t *)dest;
for( ; count != 0; count--) *temp++ = val;
return dest;
}
uint16_t *memsetw(uint16_t *dest, uint16_t val, size_t count)
{
uint16_t *temp = (uint16_t *)dest;
for( ; count != 0; count--) *temp++ = val;
return dest;
}
size_t strlen(const int8_t *str)
{
size_t retval;
for(retval = 0; *str != '\0'; str++) retval++;
return retval;
}

42
ports/arm7a/string.h
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@@ -1,42 +0,0 @@
/*
* Copyright (c) Himanshu Chauhan 2009-11.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Himanshu Chauhan nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __STRING_H
#define __STRING_H
#include <atomport.h>
void *memcpy(void *dest, const void *src, size_t count);
void *memset(void *dest, int8_t val, size_t count);
uint16_t *memsetw(uint16_t *dest, uint16_t val, size_t count);
size_t strlen(const int8_t *str);
#endif /* __STRING_H */

52
ports/arm7a/system.h
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@@ -1,52 +0,0 @@
/*
* Copyright (c) Himanshu Chauhan 2009-11.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Himanshu Chauhan nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _SYSTEM_H
#define _SYSTEM_H
#include <atomport.h>
#include <stdarg.h>
extern const uint8_t *kernel_name;
extern const uint8_t *kernel_version;
extern const uint8_t *kernel_bdate;
extern const uint8_t *kernel_btime;
extern void *memcpy (void *dest, const void *src, size_t count);
extern void *memset (void *dest, int8_t val, size_t count);
extern uint16_t *memsetw (uint16_t *dest, uint16_t val, size_t count);
extern size_t strlen (const int8_t *str);
extern int vsprintf (int8_t *buf, const int8_t *fmt, va_list args);
extern void init_console (void);
extern int32_t arch_init (void);
extern uint8_t ioreadb (void *addr);
extern void iowriteb (void *addr, uint8_t data);
#endif /* _SYSTEM_H */

244
ports/arm7a/vsprintf.c
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@@ -1,244 +0,0 @@
/* vsprintf.c -- Lars Wirzenius & Linus Torvalds. */
/*
* Wirzenius wrote this portably, Torvalds fucked it up :-)
* and Himanshu Fucked it up further :))
*/
#include <stdarg.h>
#include <system.h>
#include <atomport.h>
/* we use this so that we can do without the ctype library */
#define is_digit(c) ((c) >= '0' && (c) <= '9')
static int skip_atoi(const int8_t **s)
{
int i=0;
while (is_digit(**s))
i = i*10 + *((*s)++) - '0';
return i;
}
#define ZEROPAD 1 /* pad with zero */
#define SIGN 2 /* unsigned/signed long */
#define PLUS 4 /* show plus */
#define SPACE 8 /* space if plus */
#define LEFT 16 /* left justified */
#define SPECIAL 32 /* 0x */
#define SMALL 64 /* use 'abcdef' instead of 'ABCDEF' */
/*#define do_div(n,base) ({ \
int __res; \
__asm__("divl %4":"=a" (n),"=d" (__res):"0" (n),"1" (0),"r" (base)); \
__res; })*/
static uint32_t do_div (int32_t *n, int32_t base)
{
uint32_t remainder = *n % base;
*n /= base;
return remainder;
}
static int8_t * number(int8_t * str, int num, int32_t base,
int32_t size, int32_t precision, int32_t type)
{
int8_t c,sign,tmp[36];
const int8_t *digits=(const int8_t *)"0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ";
int32_t i;
if (type & SMALL) digits = (const int8_t *)"0123456789abcdefghijklmnopqrstuvwxyz";
if (type & LEFT) type &= ~ZEROPAD;
if (base < 2 || base > 36)
return 0;
c = (type & ZEROPAD) ? '0' : ' ' ;
if (type & SIGN && num < 0) {
sign = '-';
num = -num;
} else
sign = (type & PLUS) ? '+' : ((type & SPACE) ? ' ' : 0);
if (sign) size--;
if (type & SPECIAL) {
if (base == 16) {
size -= 2;
} else if (base == 8) {
size--;
}
}
i = 0;
if (num == 0)
tmp[i++] = '0';
else while (num != 0)
tmp[i++] = digits[do_div(&num,base)];
if (i > precision) precision = i;
size -= precision;
if (!(type & (ZEROPAD + LEFT)))
while(size-- > 0)
*str++ = ' ';
if (sign)
*str++ = sign;
if (type & SPECIAL) {
if (base == 8) {
*str++ = '0';
} else if (base == 16) {
*str++ = '0';
*str++ = digits[33];
}
}
if (!(type & LEFT))
while(size-- > 0)
*str++ = c;
while(i < precision--)
*str++ = '0';
while(i-- > 0)
*str++ = tmp[i];
while(size-- > 0)
*str++ = ' ';
return str;
}
int32_t vsprintf (int8_t *buf, const int8_t *fmt, va_list args)
{
int32_t len;
int32_t i;
int8_t * str;
int8_t *s;
int32_t *ip;
int32_t flags; /* flags to number() */
int32_t field_width; /* width of output field */
int32_t precision; /* min. # of digits for integers; max
number of chars for from string */
int32_t qualifier; /* 'h', 'l', or 'L' for integer fields */
for (str=buf ; *fmt ; ++fmt) {
if (*fmt != '%') {
*str++ = *fmt;
continue;
}
/* process flags */
flags = 0;
repeat:
++fmt; /* this also skips first '%' */
switch (*fmt) {
case '-': flags |= LEFT; goto repeat;
case '+': flags |= PLUS; goto repeat;
case ' ': flags |= SPACE; goto repeat;
case '#': flags |= SPECIAL; goto repeat;
case '0': flags |= ZEROPAD; goto repeat;
}
/* get field width */
field_width = -1;
if (is_digit(*fmt))
field_width = skip_atoi(&fmt);
else if (*fmt == '*') {
/* it's the next argument */
field_width = va_arg(args, int);
if (field_width < 0) {
field_width = -field_width;
flags |= LEFT;
}
}
/* get the precision */
precision = -1;
if (*fmt == '.') {
++fmt;
if (is_digit(*fmt))
precision = skip_atoi(&fmt);
else if (*fmt == '*') {
/* it's the next argument */
precision = va_arg(args, int);
}
if (precision < 0)
precision = 0;
}
/* get the conversion qualifier */
qualifier = -1;
if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L') {
qualifier = *fmt;
++fmt;
}
switch (*fmt) {
case 'c':
if (!(flags & LEFT))
while (--field_width > 0)
*str++ = ' ';
*str++ = (unsigned char) va_arg(args, int);
while (--field_width > 0)
*str++ = ' ';
break;
case 's':
s = va_arg(args, int8_t *);
len = strlen(s);
if (precision < 0)
precision = len;
else if (len > precision)
len = precision;
if (!(flags & LEFT))
while (len < field_width--)
*str++ = ' ';
for (i = 0; i < len; ++i)
*str++ = *s++;
while (len < field_width--)
*str++ = ' ';
break;
case 'o':
str = number(str, va_arg(args, unsigned long), 8,
field_width, precision, flags);
break;
case 'p':
if (field_width == -1) {
field_width = 8;
flags |= ZEROPAD;
}
str = number(str,
(unsigned long) va_arg(args, void *), 16,
field_width, precision, flags);
break;
case 'x':
flags |= SMALL;
case 'X':
str = number(str, va_arg(args, unsigned long), 16,
field_width, precision, flags);
break;
case 'd':
case 'i':
flags |= SIGN;
case 'u':
str = number(str, va_arg(args, unsigned long), 10,
field_width, precision, flags);
break;
case 'n':
ip = va_arg(args, int32_t *);
*ip = (str - buf);
break;
default:
if (*fmt != '%')
*str++ = '%';
if (*fmt)
*str++ = *fmt;
else
--fmt;
break;
}
}
*str = '\0';
return str-buf;
}