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Updated CortexM port

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This commit is contained in:
Natie van Rooyen
2012-09-18 15:24:59 +02:00
parent dfb831fa63
commit 28e7382732
10 changed files with 288 additions and 231 deletions
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2
ports/arm/atomport.c
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@@ -33,7 +33,7 @@
/* *
*
* Functions defined in atomport_s.asm
* Functions defined in atomport_s.S
*
*/
typedef void * SYSCONTEXT ;

10
ports/cortex_m3/Makefile → ports/cortex_m/Makefile
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@@ -1,5 +1,5 @@
ATOMTHREADS_PORT = ..... /libraries/atomthreads/ports/cortex_m3
ATOMTHREADS_KERNEL = ..... /libraries/atomthreads/kernel
ATOMTHREADS_PORT = $(ATOMTHREADS)/ports/cortex_m
ATOMTHREADS_KERNEL = $(ATOMTHREADS)/kernel
INCLUDES := $(INCLUDES) \
-I$(ATOMTHREADS_KERNEL) \
@@ -14,6 +14,6 @@ SRCS := $(SRCS) \
$(ATOMTHREADS_PORT)/atomport.c
ASMS := $(ASMS) \
$(ATOMTHREADS_PORT)/atomport_arm.asm
$(ATOMTHREADS_PORT)/atomport_s.S

0
ports/cortex_m3/README → ports/cortex_m/README
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50
ports/cortex_m/atomport-tests.h Normal file
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@@ -0,0 +1,50 @@
/*
* Copyright (c) 2012, Natie van Rooyen. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. No personal names or organizations' names associated with the
* Atomthreads project may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ATOMPORT_TEST_H__
#define __ATOMPORT_TEST_H__
/* Include Atomthreads kernel API */
#include "atom.h"
extern void dbg_format_msg (char *format, ...) ;
#define TEST_THREAD_STACK_SIZE 1024
#define ATOMLOG dbg_format_msg
#define _STR(x) x
/* API for starting each test */
extern uint32_t test_start (void);
#endif /* __ATOMPORT_TEST_H__ */

7
ports/cortex_m3/atomport.c → ports/cortex_m/atomport.c
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@@ -33,15 +33,14 @@
/* *
*
* Functions defined in atomport_arm.asm
* Functions defined in atomport_s.S
*
*/
typedef void * SYSCONTEXT ;
extern void contextInit (void) ;
extern void contextSwitch (SYSCONTEXT* save_context, SYSCONTEXT* new_context) ;
extern void contextStart (SYSCONTEXT* context) ;
extern uint32_t contextCreate (SYSCONTEXT* context, uint32_t stack_top, uint32_t entry) ;
extern uint32_t contextEnterCritical (void) ;
extern void contextExitCritical (uint32_t posture) ;
extern void contextEnableInterrupts (void) ;
/**

13
ports/cortex_m3/atomport.h → ports/cortex_m/atomport.h
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@@ -30,10 +30,9 @@
#ifndef __ATOM_PORT_H__
#define __ATOM_PORT_H__
#include "arch/context.h"
#include "types.h"
#define SYSTEM_TICKS_PER_SEC 1000
#define SYSTEM_TICKS_PER_SEC 100
/**
@@ -43,12 +42,18 @@
*/
#define POINTER void *
/* *
*
* Functions defined in atomport_arm.asm
*
*/
extern uint32_t contextEnterCritical (void) ;
extern void contextExitCritical (uint32_t posture) ;
/* Critical region protection */
#define CRITICAL_STORE uint32_t __atom_critical
#define CRITICAL_START() __atom_critical = contextEnterCritical()
#define CRITICAL_END() contextExitCritical(__atom_critical)
#endif /* __ATOM_PORT_H__ */

0
ports/cortex_m3/atomport_private.h → ports/cortex_m/atomport_private.h
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220
ports/cortex_m/atomport_s.S Normal file
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@@ -0,0 +1,220 @@
/*
Copyright (c) 2012, Natie van Rooyen. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. No personal names or organizations' names associated with the
Atomthreads project may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
.global contextInit
.global contextSwitch
.global contextStart
.global contextEnableInterrupts
.global contextEnterCritical
.global contextExitCritical
.global pendSV_Handler
.global tick_Handler
.global archTickHandler
/**/
.equ NVIC_INT_CTRL, 0xE000ED04 // Interrupt control state register
.equ NVIC_PENDSVSET, 0x10000000 // Value to trigger PendSV exception
.equ NVIC_PR_12_15_ADDR, 0xE000ED20 // System Handlers 12-15 Priority Register Address
.equ NVIC_PENDS_VPRIORITY, 0x00FF0000 // PendSV priority is minimal (0xFF)
.syntax unified
.text
.thumb
/**
* \b contextInit
*
* Architecture-specific one time initialization.
*
* Configures PendSV priority to lowest.
*
* @return None
*/
contextInit:
LDR r1, =NVIC_PR_12_15_ADDR // Load the System 12-15 Priority Register
LDR r0, [r1]
ORR r0, r0, #NVIC_PENDS_VPRIORITY // set PRI_14 (PendSV) to 0xFF - minimal
STR r0, [r1]
BX lr
/**
* \b contextSwitch
*
* Architecture-specific context switch routine.
*
* Note that interrupts are always locked out when this routine is
* called. For cooperative switches, the scheduler will have entered
* a critical region. For preemptions (called from an ISR), the
* interrupts will have disabled in the tick_Handler.
*
* @param[in] [r0] -> Address to save old stack pointer
* @param[in] [r1] -> Address where new stack pointer is stored
*
* @return None
*/
contextSwitch:
LDR r2, =context_new_stack_ptr
STR r1, [r2]
LDR r2, =context_save_stack_ptr
LDR r1, [r2]
CMP r1, #0 // if contextSwitch is going to be called again before pend_sv
IT EQ
STREQ r0, [r2]
LDR R0, =NVIC_INT_CTRL // Trigger the PendSV exception (causes context switch)
LDR R1, =NVIC_PENDSVSET
STR R1, [R0]
BX lr
/**
* \b contextStart
*
* Architecture-specific context start routine.
*
* @param[in] [r0] -> Address where stack pointer is stored
*
* @return Does not return
*/
contextStart:
LDR r1, =context_new_stack_ptr
STR r0, [r1]
LDR r1, =context_save_stack_ptr
MOV r0, #0
STR r0, [r1]
LDR r0, =NVIC_INT_CTRL // Trigger the PendSV exception (causes context switch)
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
BX lr
/**
* \b contextEnableInterrupts
*
* Enables interrupts on the processor
*
* @return None
*/
contextEnableInterrupts:
CPSIE i
BX lr
/**
* \b contextExitCritical
*
* Exit critical section (restores interrupt posture)
*
* @param[in] r0 Interrupt Posture
*
* @return None
*/
contextExitCritical:
MSR PRIMASK, r0
BX lr
/**
* \b contextEnterCritical
*
* Enter critical section (disables interrupts)
*
* @return Current interrupt posture
*/
contextEnterCritical:
MRS r0, PRIMASK
CPSID i
BX lr
/**
* \b PendSV_Handler
*
* CortexM3 PendSV_Handler. Switch context to a new stack.
*
* @return None
*/
pendSV_Handler:
CPSID i // Disable core int
LDR r1, =context_save_stack_ptr
LDR r0, [r1] // Load old (current) stack pointer address
LDR r2, =context_new_stack_ptr
LDR r2, [r2] // Load new stack pointer address
CMP r0, r2
BEQ pendsv_handler_exit
CMP r0, #0
BEQ pendsv_handler_new_stack
// Save context
MRS r3, PSP // Get PSP point
STMDB r3!, {R4-R11} // Store r4-r11
STR r3, [r0] // Save old stack pointer
MOV r3, #0
STR r3, [r1]
pendsv_handler_new_stack:
// Restore context
LDR r2, [r2] // Load new stack pointer
LDMIA r2!, {r4-r11} // Restore context
MSR PSP, r2 // Mov new stack point to PSP
pendsv_handler_exit:
CPSIE i // Enable core int
ORR lr, lr, #0x04 // Ensure exception return uses process stack
BX lr // Exit interrupt
/**
* \b Tick_Handler
*
* System timer tick interrupt handler.
*
* @return None
*/
tick_Handler:
PUSH {r4-r11, lr}
cpsid I // Disable core int
BL archTickHandler
cpsie I // Enable core int
POP {r4-r11, pc}
/**/
context_new_stack_ptr: .long 0x00000000
context_save_stack_ptr: .long 0x00000000

0
ports/cortex_m3/types.h → ports/cortex_m/types.h
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217
ports/cortex_m3/atomport_arm.asm
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@@ -1,217 +0,0 @@
;
; Copyright (c) 2012, Natie van Rooyen. All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions
; are met:
;
; 1. Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; 3. No personal names or organizations' names associated with the
; Atomthreads project may be used to endorse or promote products
; derived from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
PRESERVE8 {TRUE}
AREA UTILS, CODE, READONLY
;--
EXPORT contextInit
EXPORT contextSwitch
EXPORT contextStart
EXPORT contextEnableInterrupts
EXPORT contextEnterCritical
EXPORT contextExitCritical
EXPORT pendSV_Handler
EXPORT tick_Handler
EXTERN archTickHandler
;--
NVIC_INT_CTRL EQU 0xE000ED04 ; Interrupt control state register
NVIC_PENDSVSET EQU 0x10000000 ; Value to trigger PendSV exception
NVIC_PR_12_15_ADDR EQU 0xE000ED20 ; System Handlers 12-15 Priority Register Address
NVIC_PENDS_VPRIORITY EQU 0x00FF0000 ; PendSV priority is minimal (0xFF)
;--
; \b contextInit
;
; Architecture-specific one time initialization.
;
; Configures PendSV priority to lowest.
;
; @return None
;
contextInit
LDR r1, =NVIC_PR_12_15_ADDR ;-- Load the System 12-15 Priority Register
LDR r0, [r1]
ORR r0, r0, #NVIC_PENDS_VPRIORITY ;-- set PRI_14 (PendSV) to 0xFF - minimal
STR r0, [r1]
BX lr
;--
; \b contextSwitch
;
; Architecture-specific context switch routine.
;
; Note that interrupts are always locked out when this routine is
; called. For cooperative switches, the scheduler will have entered
; a critical region. For preemptions (called from an ISR), the
; interrupts will have disabled in the tick_Handler.
;
; @param[in] [r0] -> Address to save old stack pointer
; @param[in] [r1] -> Address where new stack pointer is stored
;
; @return None
;
contextSwitch
LDR r2, =context_new_stack_ptr
STR r1, [r2]
LDR r2, =context_save_stack_ptr
LDR r1, [r2]
TEQ r1, #0 ; if contextSwitch is going to be called again before pend_sv
STREQ r0, [r2]
LDR R0, =NVIC_INT_CTRL ; Trigger the PendSV exception (causes context switch)
LDR R1, =NVIC_PENDSVSET
STR R1, [R0]
BX lr
;--
; \b contextStart
;
; Architecture-specific context start routine.
;
; @param[in] [r0] -> Address where stack pointer is stored
;
; @return Does not return
;
contextStart
LDR r1, =context_new_stack_ptr
STR r0, [r1]
LDR r1, =context_save_stack_ptr
MOV r0, #0
STR r0, [r1]
LDR r0, =NVIC_INT_CTRL ; Trigger the PendSV exception (causes context switch)
LDR r1, =NVIC_PENDSVSET
STR r1, [r0]
BX lr
;--
; \b contextEnableInterrupts
;
; Enables interrupts on the processor
;
; @return None
;
contextEnableInterrupts
CPSIE i
BX lr
;--
; \b contextExitCritical
;
; Exit critical section (restores interrupt posture)
;
; @param[in] r0 Interrupt Posture
;
; @return None
;
contextExitCritical
MSR PRIMASK, r0
BX lr
;--
; \b contextEnterCritical
;
; Enter critical section (disables interrupts)
;
; @return Current interrupt posture
;
contextEnterCritical
MRS r0, PRIMASK
CPSID i
BX lr
;--
; \b PendSV_Handler
;
; CortexM3 PendSV_Handler. Switch context to a new stack.
;
; @return None
;
pendSV_Handler
CPSID i ; Disable core int
LDR r1, =context_save_stack_ptr
LDR r0, [r1] ; Load old (current) stack pointer address
LDR r2, =context_new_stack_ptr
LDR r2, [r2] ; Load new stack pointer address
TEQ r0, r2
BEQ pendsv_handler_exit
TEQ r0, #0
BEQ pendsv_handler_new_stack
; Save context
MRS r3, PSP ; Get PSP point
STMDB r3!, {R4-R11} ; Store r4-r11
STR r3, [r0] ; Save old stack pointer
MOV r3, #0
STR r3, [r1]
pendsv_handler_new_stack
; Restore context
LDR r2, [r2] ; Load new stack pointer
LDMIA r2!, {r4-r11} ; Restore context
MSR PSP, r2 ; Mov new stack point to PSP
pendsv_handler_exit
CPSIE i ; Enable core int
ORR lr, lr, #0x04 ; Ensure exception return uses process stack
BX lr ; Exit interrupt
;--
; \b Tick_Handler
;
; System timer tick interrupt handler.
;
; @return None
;
tick_Handler
PUSH {r4-r11, lr}
cpsid I ; Disable core int
BL archTickHandler
cpsie I ; Enable core int
POP {r4-r11, pc}
;--
context_new_stack_ptr DCD 0x00000000
context_save_stack_ptr DCD 0x00000000
;--
END