mirror of
https://github.com/kelvinlawson/atomthreads.git
synced 2026-01-11 18:33:16 +01:00
Fixed Context switch and timer-delay problem with MIPS.
Signed-off-by: Himanshu Chauhan <hschauhan@nulltrace.org>
This commit is contained in:
Himanshu Chauhan
@@ -47,7 +47,7 @@ fn:
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nop; \
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nop;
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#define enable_global_interrupts ei $0
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#define enable_global_interrupts ei
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#define disable_global_interrupts di $0
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#define EXCEPTION_VECTOR(_name, _offset, _where)\
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@@ -63,70 +63,69 @@ _name: \
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#define LOAD_REG(reg, treg) \
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lw reg, ((reg ## _IDX) * 4)(treg)
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#define SAVE_INT_CONTEXT \
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addiu sp, sp, -((NUM_REGISTERS + 1)* 4); \
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#define SAVE_INT_CONTEXT(treg) \
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mfc0 k1, CP0_EPC; \
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SAVE_REG(t0,sp); \
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SAVE_REG(t1,sp); \
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SAVE_REG(t2,sp); \
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SAVE_REG(t3,sp); \
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SAVE_REG(t4,sp); \
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SAVE_REG(t5,sp); \
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SAVE_REG(t6,sp); \
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SAVE_REG(t7,sp); \
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SAVE_REG(t8,sp); \
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SAVE_REG(t9,sp); \
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SAVE_REG(v0,sp); \
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SAVE_REG(v1,sp); \
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SAVE_REG(a0,sp); \
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SAVE_REG(a1,sp); \
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SAVE_REG(a2,sp); \
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SAVE_REG(a3,sp); \
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SAVE_REG(s0,sp); \
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SAVE_REG(s1,sp); \
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SAVE_REG(s2,sp); \
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SAVE_REG(s3,sp); \
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SAVE_REG(s4,sp); \
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SAVE_REG(s5,sp); \
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SAVE_REG(s6,sp); \
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SAVE_REG(s7,sp); \
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SAVE_REG(gp,sp); \
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SAVE_REG(s8,sp); \
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SAVE_REG(ra,sp); \
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sw k0, (sp_IDX * 4)(sp); \
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sw k1, (NUM_REGISTERS * 4)(sp);
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SAVE_REG(t0,treg); \
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SAVE_REG(t1,treg); \
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SAVE_REG(t2,treg); \
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SAVE_REG(t3,treg); \
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SAVE_REG(t4,treg); \
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SAVE_REG(t5,treg); \
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SAVE_REG(t6,treg); \
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SAVE_REG(t7,treg); \
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SAVE_REG(t8,treg); \
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SAVE_REG(t9,treg); \
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SAVE_REG(v0,treg); \
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SAVE_REG(v1,treg); \
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SAVE_REG(a0,treg); \
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SAVE_REG(a1,treg); \
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SAVE_REG(a2,treg); \
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SAVE_REG(a3,treg); \
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SAVE_REG(s0,treg); \
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SAVE_REG(s1,treg); \
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SAVE_REG(s2,treg); \
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SAVE_REG(s3,treg); \
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SAVE_REG(s4,treg); \
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SAVE_REG(s5,treg); \
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SAVE_REG(s6,treg); \
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SAVE_REG(s7,treg); \
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SAVE_REG(gp,treg); \
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SAVE_REG(s8,treg); \
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SAVE_REG(ra,treg); \
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sw k0, (sp_IDX * 4)(treg); \
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sw k1, (cp0_epc_IDX * 4)(treg);
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#define RESTORE_INT_CONTEXT \
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lw k1, (NUM_REGISTERS * 4)(sp); \
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#define RESTORE_INT_CONTEXT(treg) \
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lw k1, (cp0_epc_IDX * 4)(treg); \
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mtc0 k1, CP0_EPC; \
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LOAD_REG(s0,sp); \
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LOAD_REG(s1,sp); \
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LOAD_REG(s2,sp); \
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LOAD_REG(s3,sp); \
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LOAD_REG(s4,sp); \
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LOAD_REG(s5,sp); \
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LOAD_REG(s6,sp); \
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LOAD_REG(s7,sp); \
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LOAD_REG(v0,sp); \
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LOAD_REG(v1,sp); \
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LOAD_REG(a0,sp); \
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LOAD_REG(a1,sp); \
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LOAD_REG(a2,sp); \
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LOAD_REG(a3,sp); \
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LOAD_REG(t0,sp); \
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LOAD_REG(t1,sp); \
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LOAD_REG(t2,sp); \
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LOAD_REG(t3,sp); \
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LOAD_REG(t4,sp); \
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LOAD_REG(t5,sp); \
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LOAD_REG(t6,sp); \
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LOAD_REG(t7,sp); \
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LOAD_REG(t8,sp); \
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LOAD_REG(t9,sp); \
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LOAD_REG(gp,sp); \
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LOAD_REG(ra,sp); \
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LOAD_REG(s8,sp); \
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lw sp, (sp_IDX * 4)(sp);
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LOAD_REG(s0,treg); \
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LOAD_REG(s1,treg); \
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LOAD_REG(s2,treg); \
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LOAD_REG(s3,treg); \
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LOAD_REG(s4,treg); \
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LOAD_REG(s5,treg); \
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LOAD_REG(s6,treg); \
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LOAD_REG(s7,treg); \
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LOAD_REG(v0,treg); \
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LOAD_REG(v1,treg); \
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LOAD_REG(a0,treg); \
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LOAD_REG(a1,treg); \
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LOAD_REG(a2,treg); \
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LOAD_REG(a3,treg); \
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LOAD_REG(t0,treg); \
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LOAD_REG(t1,treg); \
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LOAD_REG(t2,treg); \
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LOAD_REG(t3,treg); \
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LOAD_REG(t4,treg); \
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LOAD_REG(t5,treg); \
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LOAD_REG(t6,treg); \
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LOAD_REG(t7,treg); \
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LOAD_REG(t8,treg); \
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LOAD_REG(t9,treg); \
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LOAD_REG(gp,treg); \
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LOAD_REG(ra,treg); \
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LOAD_REG(s8,treg); \
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lw sp, (sp_IDX * 4)(treg);
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#endif /* __ASSEMBLY__ */
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@@ -31,9 +31,6 @@
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.section .text
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.extern atomCurrentContext
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.extern at_preempt_count
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/**
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* Function that performs the contextSwitch. Whether its a voluntary release
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* of CPU by thread or a pre-emption, under both conditions this function is
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@@ -43,121 +40,49 @@
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*/
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.globl archContextSwitch
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archContextSwitch:
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/*
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* Check if we are being called in interrupt
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* context. If yes, we need to restore complete
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* context and return directly from here.
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*/
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move k0, ra
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bal atomCurrentContext
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nop
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beq v0, zero, __in_int_context
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nop
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move ra, k0
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move v0, a0 /* return old tcb when we return from here */
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lw k0, 0(a0) /* assume that sp_save_ptr is always at base of ATOM_TCB */
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sw s0, (s0_IDX * 4)(k0)
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sw s1, (s1_IDX * 4)(k0)
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sw s2, (s2_IDX * 4)(k0)
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sw s3, (s3_IDX * 4)(k0)
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sw s4, (s4_IDX * 4)(k0)
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sw s5, (s5_IDX * 4)(k0)
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sw s6, (s6_IDX * 4)(k0)
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sw s7, (s7_IDX * 4)(k0)
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sw s8, (s8_IDX * 4)(k0)
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sw sp, (sp_IDX * 4)(k0)
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sw gp, (gp_IDX * 4)(k0)
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sw ra, (ra_IDX * 4)(k0)
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/*
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* We are saving registers in non-interrupt context because
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* a thread probably is trying to yield CPU. Storing zero
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* in EPC offset differentiates this. When restoring the
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* context, if EPC offset has zero we will restore only
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* the partial context. Rest will be done by GCC while
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* unwinding the call.
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*/
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sw zero, (cp0_epc_IDX * 4)(k0)
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SAVE_REG(s0, k0)
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SAVE_REG(s1, k0)
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SAVE_REG(s2, k0)
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SAVE_REG(s3, k0)
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SAVE_REG(s4, k0)
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SAVE_REG(s5, k0)
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SAVE_REG(s6, k0)
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SAVE_REG(s7, k0)
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SAVE_REG(s8, k0)
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SAVE_REG(sp, k0)
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SAVE_REG(gp, k0)
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SAVE_REG(ra, k0)
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lw k1, 0(a1)
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LOAD_REG(s0, k1)
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LOAD_REG(s1, k1)
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LOAD_REG(s2, k1)
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LOAD_REG(s3, k1)
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LOAD_REG(s4, k1)
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LOAD_REG(s5, k1)
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LOAD_REG(s6, k1)
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LOAD_REG(s7, k1)
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LOAD_REG(s8, k1)
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LOAD_REG(sp, k1)
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LOAD_REG(gp, k1)
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LOAD_REG(ra, k1)
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lw k0, (cp0_epc_IDX * 4)(k1)
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bnez k0, __unwind_int_context
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bnez k0, 1f
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nop
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lw s0, (s0_IDX * 4)(k1)
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lw s1, (s1_IDX * 4)(k1)
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lw s2, (s2_IDX * 4)(k1)
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lw s3, (s3_IDX * 4)(k1)
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lw s4, (s4_IDX * 4)(k1)
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lw s5, (s5_IDX * 4)(k1)
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lw s6, (s6_IDX * 4)(k1)
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lw s7, (s7_IDX * 4)(k1)
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lw s8, (s8_IDX * 4)(k1)
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lw sp, (sp_IDX * 4)(k1)
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lw gp, (gp_IDX * 4)(k1)
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lw ra, (ra_IDX * 4)(k1)
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li k0, 0x00000001
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sw k0, (cp0_epc_IDX * 4)(k1)
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LOAD_REG(a0, k1)
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LOAD_REG(a1, k1)
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LOAD_REG(a2, k1)
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LOAD_REG(a3, k1)
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enable_global_interrupts
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1:
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jr ra
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nop
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__in_int_context:
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move ra, k0
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/*
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* In interrupt context, the interrupt handler
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* saves the context for us. Its very well there
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* and we don't need to do it again.
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*
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* We will figure out of the task that we are
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* switching in was saved in interrupt context
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* or otherwise.
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*/
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lw k0, (cp0_epc_IDX * 4)(k1)
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bnez k0, __unwind_int_context
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nop
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/*
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* Unwinding a task switched in non-interrupt context.
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* So, restore only the partials. But since we are in
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* interrupt mode, we will put ra in epc and do a eret
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* so that we get out of interrupt mode and switch to
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* the new task.
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*/
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__unwind_non_int_context:
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lw s0, (s0_IDX * 4)(k1)
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lw s1, (s1_IDX * 4)(k1)
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lw s2, (s2_IDX * 4)(k1)
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lw s3, (s3_IDX * 4)(k1)
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lw s4, (s4_IDX * 4)(k1)
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lw s5, (s5_IDX * 4)(k1)
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lw s6, (s6_IDX * 4)(k1)
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lw s7, (s7_IDX * 4)(k1)
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lw s8, (s8_IDX * 4)(k1)
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lw sp, (sp_IDX * 4)(k1)
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lw gp, (gp_IDX * 4)(k1)
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lw ra, (ra_IDX * 4)(k1)
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mtc0 ra, CP0_EPC
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nop
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nop
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nop
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j __ret_from_switch
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nop
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__unwind_int_context:
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move sp, k1
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RESTORE_INT_CONTEXT
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__ret_from_switch:
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la k0, at_preempt_count
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lw k1, (k0)
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addi k1, k1, -1
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sw k1, (k0)
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bnez k1, __return_from_int
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nop
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enable_global_interrupts
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ehb
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__return_from_int:
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eret
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/**
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* archFirstThreadRestore(ATOM_TCB *new_tcb)
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*
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@@ -182,5 +107,13 @@ archFirstThreadRestore:
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nop
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nop
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nop
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ehb
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li k0, 0x00000001
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sw k0, (cp0_epc_IDX * 4)(k1)
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nop
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ehb
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enable_global_interrupts
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ehb
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nop
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nop
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eret
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@@ -90,32 +90,16 @@ LEAF(_handle_interrupt)
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beq k0, zero, 1f
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nop
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move k0, ra
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move k1, v0
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bal atomCurrentContext
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nop
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beq v0, zero, 2f /* v0 should be current context */
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nop
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move ra, k0
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lw k0, 0(v0)
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move v0, k1
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move k1, k0
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/*
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* Note that we aren't loading any new SP. Context
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* will be save on the interrupted threads' stack.
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*/
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move k0, sp
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move sp, k1
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SAVE_INT_CONTEXT
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/* Calculate interrupt context base */
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addi sp, sp, -(NUM_CTX_REGS * WORD_SIZE)
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SAVE_INT_CONTEXT(sp)
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bal handle_mips_systick
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nop
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RESTORE_INT_CONTEXT
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1:
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RESTORE_INT_CONTEXT(sp)
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1:
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enable_global_interrupts
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eret
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2: b 2b
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END(_handle_interrupt)
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LEAF(_handle_cache_error)
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@@ -54,14 +54,19 @@ void mips_cpu_timer_enable(void)
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void handle_mips_systick(void)
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{
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/* clear EXL from status */
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uint32_t sr = read_c0_status();
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sr &= ~0x00000002;
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write_c0_status(sr);
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/* Call the interrupt entry routine */
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atomIntEnter();
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/* Call the OS system tick handler */
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atomTimerTick();
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write_c0_compare(read_c0_count() + COUNTER_TICK_COUNT);
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/* Call the interrupt exit routine */
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atomIntExit(TRUE);
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write_c0_compare(read_c0_count() + COUNTER_TICK_COUNT);
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}
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@@ -31,7 +31,7 @@
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#include <atom.h>
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#include <atomport-private.h>
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#include <atomport.h>
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#include "regs.h"
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#include <atomport-asm-macros.h>
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#include <string.h>
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@@ -58,11 +58,11 @@ void archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top,
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void (*entry_point)(UINT32),
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UINT32 entry_param)
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{
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#define STORE_VAL(base, reg, val) \
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*((uint32_t *)(base + ((reg ## _IDX) * WORD_SIZE))) = (uint32_t)val
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uint32_t stack_start = (uint32_t)(stack_top - (WORD_SIZE * (NUM_REGISTERS + 1)));
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/* Make space for context saving */
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uint32_t stack_start = (uint32_t)(stack_top - (WORD_SIZE * NUM_CTX_REGS));
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tcb_ptr->sp_save_ptr = (void *)stack_start;
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@@ -75,7 +75,7 @@ void archThreadContextInit (ATOM_TCB *tcb_ptr, void *stack_top,
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STORE_VAL(stack_start, s5, 0);
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STORE_VAL(stack_start, s6, 0);
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STORE_VAL(stack_start, s7, 0);
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STORE_VAL(stack_start, cp0_epc, entry_point);
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STORE_VAL(stack_start, cp0_epc, 0);
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STORE_VAL(stack_start, ra, entry_point);
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STORE_VAL(stack_start, a0, entry_param);
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}
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@@ -72,21 +72,14 @@ extern uint32_t at_preempt_count;
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__asm__ __volatile__("di %0\t\n" \
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"ehb\t\n" \
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:"=r"(status_reg)); \
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at_preempt_count++; \
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}while(0);
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#define CRITICAL_END() \
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do { \
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at_preempt_count--; \
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\
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if (at_preempt_count == 0) { \
|
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if (atomCurrentContext()) { \
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__asm__ __volatile__("ei %0\t\n" \
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"ehb\t\n" \
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::"r"(status_reg));\
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} \
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} \
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||||
\
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__asm__ __volatile__("mtc0 %0, $12\t\n" \
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"nop\t\n" \
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||||
"ehb\t\n" \
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||||
::"r"(status_reg)); \
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||||
}while(0);
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||||
|
||||
/* Uncomment to enable stack-checking */
|
||||
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||||
@@ -101,6 +101,10 @@
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||||
#define at_IDX 30
|
||||
#define zero_IDX 31
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||||
#define cp0_epc_IDX 32
|
||||
#define cp0_status_IDX 33
|
||||
#define cp_cause_IDX 34
|
||||
|
||||
#define NUM_CTX_REGS 35
|
||||
|
||||
#define CP0_INDEX $0
|
||||
#define CP0_RANDOM $1
|
||||
|
||||
Reference in New Issue
Block a user