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Cortex M port added

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qemu_lm3s platform added
This commit is contained in:
Natie van Rooyen
2012-09-27 10:49:09 +02:00
parent daa748332b
commit 650f5e2ac3
19 changed files with 109 additions and 201 deletions
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12
platforms/qemu_integratorcp/README Normal file
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@@ -0,0 +1,12 @@
---------------------------------------------------------------------------
Library: Atomthreads QEMU ARM Integrator/CP (ARM926EJ-S) Platform.
Author: Natie van Rooyen <natie@navaro.nl>
License: BSD Revised
---------------------------------------------------------------------------
QEMU ARM Integrator/CP (ARM926EJ-S) Platform
The "qemu_integratorcp" platform contains sources for building a sample
Atomthreads application for the ARM Integrator/CP (ARM926EJ-S) platform.

18
platforms/qemu_integratorcp/modules.h
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@@ -29,14 +29,14 @@
#ifndef __MODULES_H__
#define __MODULES_H__
/*
* Module definitions to use with the ARM Integrator/CP (ARM926EJ-S)
*/
#include "atomport.h"
extern void dbg_format_msg (char *format, ...) ;
#define DBG_MESSAGE(fmt_str) { dbg_format_msg fmt_str ; }
typedef volatile unsigned int REG_DWORD ;// Hardware register definition
typedef volatile unsigned int REG_DWORD ;
typedef volatile unsigned short REG_WORD ;
typedef volatile unsigned char REG_BYTE ;
@@ -110,7 +110,7 @@ typedef struct ICP_PIC_S {
/* module definitions */
#define BOARD_BASE_ADDRESS_TIMER_0 0x13000000
#define BOARD_BASE_ADDRESS_PIC 0x14000000
@@ -118,7 +118,11 @@ extern ICP_TIMER_T* const board_timer_0 ;
extern ICP_PIC_T* const board_pic ;
/* Function prototypes */
extern int low_level_init (void) ;
extern void dbg_format_msg (char *format, ...) ;
#define DBG_MESSAGE(fmt_str) { dbg_format_msg fmt_str ; }
#endif /* __MODULES_H__ */

6
platforms/qemu_integratorcp/startup.s
View File

@@ -1,9 +1,9 @@
.section .vectors, "x"
.global __interrupt_vector_table
.global __irq_stack_top__
.global __fiq_stack_top__
.global __svc_stack_top__
.extern __irq_stack_top__
.extern __fiq_stack_top__
.extern __svc_stack_top__
.global bsp_ints_enable
.global bsp_ints_disable

3
platforms/qemu_lm3s/Makefile
View File

@@ -5,7 +5,7 @@ ifeq ($(ATOMTHREADS),)
ATOMTHREADS = $(shell pwd)/../../
endif
ifeq ($(TEST_NAME),)
TEST_NAME = mutex1
TEST_NAME = kern1
endif
@@ -29,7 +29,6 @@ SRCS := $(SRCS) \
main.c \
$(ATOMTHREADS)/tests/$(TEST_NAME).c \
# startup_c.c \
ASMS := $(ASMS) \
startup.S \

33
platforms/qemu_lm3s/README Normal file
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@@ -0,0 +1,33 @@
---------------------------------------------------------------------------
Library: Atomthreads QEMU Stellaris LM3S6965 Platform.
Author: Natie van Rooyen <natie@navaro.nl>
License: BSD Revised
---------------------------------------------------------------------------
QEMU Stellaris LM3S6965 Platform
The "qemu_lm3s" platform contains sources for building a sample Atomthreads
application for the Stellaris LM3S6965 platform.
ISSUES:
There seems to be several problems for the QEMU Cortex M3 processor. The
platform and port contains specific hacks to make it work on the QEMU 1.2.0
release it was tested on. Also see the latest patches for QEMU.
Fixes implemented for the QEMU 1.2.0 release:
1. Install the patch http://patchwork.ozlabs.org/patch/180315/
2. Use the PLATFORM_QEMU_LM3S_HACK define in the Makefile:
- Disabling interrupts on the processor does not work (verified).
- Disabling interrupts of the Cortex M Sys Tick Interrupt does not
work (verified).
- NVIC Interrupt priorities not implemented correctly (not verified).
Because of the problems with the Sys Tick Interrupt the The Stellaris
General-Purpose Timer Module (GPTM) was used to generate the system timer
tick.

3
platforms/qemu_lm3s/main.c
View File

@@ -43,7 +43,6 @@ static unsigned char idle_stack[IDLE_STACK_BYTE_SIZE] ;
ATOM_TCB test_tcb ;
/**
* \b test_thread
*
@@ -78,7 +77,7 @@ main (void)
int i = 0 ;
uint32_t failures ;
printf ("atomthreads starting %s... \r\n", ATOMTHREADS_TEST) ;
printf ("Atomthreads starting %s... \r\n", ATOMTHREADS_TEST) ;
atomOSInit(&idle_stack[IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)], IDLE_STACK_BYTE_SIZE - sizeof(unsigned int)) ;
atomThreadCreate ((ATOM_TCB *)&test_tcb, TEST_THREAD_PRIO, test_thread, 0, &test_stack[(TEST_STACK_BYTE_SIZE) - sizeof(unsigned int)], TEST_STACK_BYTE_SIZE - sizeof(unsigned int));

15
platforms/qemu_lm3s/modules.c
View File

@@ -101,18 +101,15 @@ void
__context_tick_handler (void)
{
if (1) {
atomIntEnter();
atomIntEnter();
/* Call the OS system tick handler */
atomTimerTick();
/* Call the OS system tick handler */
atomTimerTick();
board_gptm0->ICR |= GPTM_TIMER_INT_TATOIM ;
board_gptm0->ICR |= GPTM_TIMER_INT_TATOIM ;
/* Call the interrupt exit routine */
atomIntExit(TRUE);
}
/* Call the interrupt exit routine */
atomIntExit(TRUE);
}

10
platforms/qemu_lm3s/modules.h
View File

@@ -86,7 +86,7 @@ typedef struct GPTM_TIMER_S {
#define GPTM_TIMER_CTL_TBEVENT_MASK ((unsigned int)0x03 << 10) // GPTM TimerB Event Mode
#define GPTM_TIMER_CTL_TBEVENT_PE ((unsigned int)0x00 << 10) // Positive edge
#define GPTM_TIMER_CTL_TBEVENT_NE ((unsigned int)0x01 << 10) // Negative edge
#define GPTM_TIMER_CTL_TBEVENT_NE ((unsigned int)0x03 << 10) // Both edges
#define GPTM_TIMER_CTL_TBEVENT ((unsigned int)0x03 << 10) // Both edges
#define GPTM_TIMER_CTL_TBSTALL ((unsigned int)0x01 << 9) // GPTM Timer B Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger
#define GPTM_TIMER_CTL_TBEN ((unsigned int)0x01 << 8) // GPTM TimerB Enable
// --------
@@ -96,7 +96,7 @@ typedef struct GPTM_TIMER_S {
#define GPTM_TIMER_CTL_TAEVENT_MASK ((unsigned int)0x03 << 2) // GPTM TimerA Event Mode
#define GPTM_TIMER_CTL_TAEVENT_PE ((unsigned int)0x00 << 2) // Positive edge
#define GPTM_TIMER_CTL_TAEVENT_NE ((unsigned int)0x01 << 2) // Negative edge
#define GPTM_TIMER_CTL_TAEVENT_NE ((unsigned int)0x03 << 2) // Both edges
#define GPTM_TIMER_CTL_TAEVENT ((unsigned int)0x03 << 2) // Both edges
#define GPTM_TIMER_CTL_TASTALL ((unsigned int)0x01 << 1) // GPTM Timer A Stall Enable. 0 Timer B continues counting while the processor is halted by the debugger
#define GPTM_TIMER_CTL_TAEN ((unsigned int)0x01 << 0) // GPTM TimerA Enable
// -------- GPTM_TIMER_IMR : (IMR Offset: 0x18) This register allows software to enable/disable GPTM controller-level interrupts. --------
@@ -191,7 +191,7 @@ typedef struct SCB_S {
} SCB_T, *PSCB_T ;
/* module definitions */
#define BOARD_BASE_ADDRESS_SYSTICK 0xE000E000
#define BOARD_BASE_ADDRESS_NVIC 0xE000E100
#define BOARD_BASE_ADDRESS_SCB 0xE000ED00
@@ -203,11 +203,11 @@ extern SCB_T* const board_scb ;
extern GPTM_TIMER_T* const board_gptm0 ;
/* Function prototypes */
extern int low_level_init (void) ;
extern void dbg_format_msg (char *format, ...) ;
extern void dbg_hard_fault_handler_c (unsigned int * hardfault_args) ;
#define DBG_MESSAGE(fmt_str) { dbg_format_msg fmt_str ; }
#define DBG_MESSAGE(fmt_str) { dbg_format_msg fmt_str ; }
#endif /* __MODULES_H__ */

16
platforms/qemu_lm3s/startup.S
View File

@@ -35,9 +35,9 @@
.global __interrupt_vector_table
.global tick_Handler
.global pendSV_Handler
.global dbg_hard_fault_handler_c
.extern archTickHandler
.extern archPendSVHandler
.extern dbg_hard_fault_handler_c
/**
* \b __interrupt_vector_table
@@ -58,7 +58,7 @@ __interrupt_vector_table:
.long sys_Handler
.long sys_Handler
.long 0
.long pendSV_Handler
.long archPendSVHandler
.long sys_Handler
/* External interrupts */
@@ -81,7 +81,7 @@ __interrupt_vector_table:
.long default_Handler // ADC Sequence 2
.long default_Handler // ADC Sequence 3
.long default_Handler // Watchdog timer
.long tick_Handler // Timer 0 subtimer A
.long archTickHandler // Timer 0 subtimer A
.long default_Handler // Timer 0 subtimer B
.long default_Handler // Timer 1 subtimer A
.long default_Handler // Timer 1 subtimer B
@@ -144,9 +144,9 @@ fault_Handler:
.thumb
.global reset_Handler
.global initialise_monitor_handles
.global low_level_init
.global main
.extern initialise_monitor_handles
.extern low_level_init
.extern main
/**

32
platforms/qemu_lm3s/system.ld
View File

@@ -1,26 +1,4 @@
/******************************************************************************
*
* hello_codered.ld - Code Red linker configuration file for hello.
*
* Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved.
* Software License Agreement
*
* Texas Instruments (TI) is supplying this software for use solely and
* exclusively on TI's microcontroller products. The software is owned by
* TI and/or its suppliers, and is protected under applicable copyright
* laws. You may not combine this software with "viral" open-source
* software in order to form a larger program.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
* NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
* CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
* DAMAGES, FOR ANY REASON WHATSOEVER.
*
* This is part of revision 9107 of the EK-LM3S6965 Firmware Package.
*
*****************************************************************************/
MEMORY
{
@@ -33,7 +11,7 @@ SECTIONS
_vRamTop = 0x20000000 + 0x00010000;
.text :
{
*(.vectors)
KEEP(*(.vectors))
*(.startup)
*(.text*)
*(.rodata*)
@@ -86,12 +64,6 @@ SECTIONS
_pvHeapStart = .;
} > SRAM
/*
* Note: (ref: M0000066)
* Moving the stack down by 16 is to work around a GDB bug.
* This space can be reclaimed for Production Builds.
*/
_vStackTop = _vRamTop - 16;
.stack _vStackTop :
{

29
ports/arm/README
View File

@@ -6,33 +6,12 @@ License: BSD Revised
---------------------------------------------------------------------------
ARM ARMv7 PORT
ARM PORT
This folder contains a port of the Atomthreads real time kernel for the
ARMv7 processor architecture. This port was only tested on a ARMv7 but
should work on other versions of the ARM processor as well.
ARM processor architecture. This port was tested on Cortex A9, Cortex A15
and the ARM926EJ-S (QEMU).
To Use:
1. From your platforms IRQ vector branch to the "__irq_context_handler()".
All interrupts from where calls to Atomthreads will be made should do
this. The "__irq_context_handler()" will call a platform specific
function called "__context_preempt_handler()" to dispatch the interrupt.
2. Implement the function "__context_preempt_handler()"
from where your platforms interrupt controller will be serviced and the
interrupt will be dispatched to a specific interrupt service routine. In
the case of your platforms timer tick interrupt call the "archTickHandler()"
implemented in "atomport.c".
3. Initialize your platforms timer tick hardware to generate an OS timer tick
interrupt.
4. Add code to acknowledge your timer hardware's interrupt in the
function "archTickHandler()" implemented in "atomport.c". This must
be done here because "atomIntExit()" might switch the context.
5. After your platforms c-runtime initialization has completed, start
Atomthreads from your runtime's "main()" function.
6. Include the port's Makefile in your platform build flow.
See the example project in the "platforms/qemu_integratorcp" directory.

39
ports/arm/atomport.c
View File

@@ -38,7 +38,6 @@
*/
typedef void * SYSCONTEXT ;
extern void contextInit (void) ;
extern void contextSwitch (SYSCONTEXT* save_context, SYSCONTEXT* new_context) ;
extern void contextStart (SYSCONTEXT* context) ;
extern void contextEnableInterrupts (void) ;
@@ -145,41 +144,3 @@ archContextSwitch (ATOM_TCB * p_sp_old, ATOM_TCB * p_sp_new)
}
/**
* \b archTimerTickIrqHandler
*
* System timer tick interrupt handler.
*
*/
void
archTickHandler (void)
{
atomIntEnter();
/* Call the OS system tick handler */
atomTimerTick();
/* ack the interrupt if needed */
/* ... */
/* Call the interrupt exit routine */
atomIntExit(TRUE);
}
/**
* \b archTickInit
*
* System timer initialization.
*
*/
void
archTickInit (void)
{
/* Initialize NVIC PendSV */
contextInit () ;
/* Initializa Timer Hardware */
/* ... */
}

1
ports/arm/atomport.h
View File

@@ -47,6 +47,7 @@
* Functions defined in atomport_arm.asm
*
*/
extern void contextInit (void) ;
extern uint32_t contextEnterCritical (void) ;
extern void contextExitCritical (uint32_t posture) ;

5
ports/arm/atomport_private.h
View File

@@ -32,8 +32,9 @@
/* Function prototypes */
extern void archTickHandler (void) ;
extern void archTickInit (void) ;
extern void archIRQHandler (void) ;
/* required interface */
extern void __context_preempt_handler (void) ;
#endif /* __ATOM_PORT_PRIVATE_H__ */

3
ports/arm/atomport_s.S
View File

@@ -34,7 +34,6 @@
.global archIRQHandler
.global contextEnterCritical
.global contextExitCritical
.global contextEnableInterrupts
@@ -44,7 +43,7 @@
.global contextInit
.global __context_preempt_handler
.extern __context_preempt_handler
/**/
.equ USR_MODE, 0x10

24
ports/cortex_m/README
View File

@@ -1,31 +1,17 @@
---------------------------------------------------------------------------
Library: Atomthreads CortexM3 Port
Library: Atomthreads ARM Cortex M Port
Author: Natie van Rooyen <natie@navaro.nl>
License: BSD Revised
---------------------------------------------------------------------------
ARM CortexM3 PORT
ARM Cortex M PORT
This folder contains a port of the Atomthreads real time kernel for the
ARM CortexM3 processor architecture.
ARM CortexM type processor architecture. This port was tested on the
Cortex M3 and the Cortex M4.
To Use:
1. Install the "pendSV_Handler" and "tick_Handler" implemented in the file
"atomport_arm.asm" in your platforms interrupt vectors.
2. Complete the function "archTickInit()" implemented in "atomport.c" to
initialize your platforms timer tick interrupt. If you use the build in
SysTick of the CortexM3 you also have to add code here to start it.
3. If required, add code to acknowledge your timer hardware's interrupt in
the function "archTickHandler()" also implemented in "atomport.c".
4. During your platform initialization call the function "archTickInit()"
exported from "atomport_private.h" to initialize the CortexM3
"PendSV_Handler".
5. After your platforms c-runtime initialization has completed, start
Atomthreads from your runtime's "main()" function.
See the example project in the "platforms/qemu_lm3s" directory.

38
ports/cortex_m/atomport.c
View File

@@ -156,41 +156,3 @@ archContextSwitch (ATOM_TCB * p_sp_old, ATOM_TCB * p_sp_new)
}
/**
* \b archTimerTickIrqHandler
*
* System timer tick interrupt handler.
*
*/
//void
//archTickHandler (void)
//{
// atomIntEnter();
//
// /* Call the OS system tick handler */
// atomTimerTick();
//
// /* ack the interrupt if needed */
// /* ... */
//
// /* Call the interrupt exit routine */
// atomIntExit(TRUE);
//}
/**
* \b archTickInit
*
* System timer initialization.
*
*/
//void
//archTickInit (void)
//{
// /* Initialize NVIC PendSV */
// contextInit () ;
//
// /* Initializa Timer Hardware */
// /* ... */
//}

7
ports/cortex_m/atomport_private.h
View File

@@ -32,7 +32,10 @@
/* Function prototypes */
extern void archTickHandler (void) ;
extern void archTickInit (void) ;
extern void archPendSVHandler (void) ;
extern void archTickHandler (void) ;
/* required interface */
extern void __context_tick_handler (void) ;
#endif /* __ATOM_PORT_PRIVATE_H__ */

16
ports/cortex_m/atomport_s.S
View File

@@ -28,17 +28,17 @@
*/
.global archPendSVHandler
.global archTickHandler
.global contextInit
.global contextSwitch
.global contextStart
.global contextEnableInterrupts
.global contextEnterCritical
.global contextExitCritical
.global pendSV_Handler
.global tick_Handler
.global __context_tick_handler
.extern __context_tick_handler
/**/
@@ -184,14 +184,14 @@ contextEnterCritical:
BX lr
/**
* \b PendSV_Handler
* \b archPendSVHandler
*
* CortexM3 PendSV_Handler. Switch context to a new stack.
* CortexM3 archPendSVHandler. Switch context to a new stack.
*
* @return None
*/
.thumb_func
pendSV_Handler:
archPendSVHandler:
#ifndef PLATFORM_QEMU_LM3S_HACK
CPSID i // Disable core int
#else
@@ -237,14 +237,14 @@ pendsv_handler_exit:
/**
* \b Tick_Handler
* \b archTickHandler
*
* System timer tick interrupt handler.
*
* @return None
*/
.thumb_func
tick_Handler:
archTickHandler:
PUSH {r4-r11, lr}
#ifndef PLATFORM_QEMU_LM3S_HACK