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120 lines
3.7 KiB
ArmAsm
120 lines
3.7 KiB
ArmAsm
/*
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* Copyright (c) 2010, Atomthreads Project. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. No personal names or organizations' names associated with the
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* Atomthreads project may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <atomport-asm-macros.h>
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.section .text
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/**
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* Function that performs the contextSwitch. Whether its a voluntary release
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* of CPU by thread or a pre-emption, under both conditions this function is
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* called. The signature is as follows:
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*
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* archContextSwitch(ATOM_TCB *old_tcb, ATOM_TCB *new_tcb)
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*/
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.globl archContextSwitch
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archContextSwitch:
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move v0, a0 /* return old tcb when we return from here */
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lw k0, 0(a0) /* assume that sp_save_ptr is always at base of ATOM_TCB */
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SAVE_REG(s0, k0)
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SAVE_REG(s1, k0)
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SAVE_REG(s2, k0)
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SAVE_REG(s3, k0)
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SAVE_REG(s4, k0)
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SAVE_REG(s5, k0)
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SAVE_REG(s6, k0)
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SAVE_REG(s7, k0)
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SAVE_REG(s8, k0)
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SAVE_REG(sp, k0)
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SAVE_REG(gp, k0)
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SAVE_REG(ra, k0)
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lw k1, 0(a1)
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LOAD_REG(s0, k1)
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LOAD_REG(s1, k1)
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LOAD_REG(s2, k1)
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LOAD_REG(s3, k1)
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LOAD_REG(s4, k1)
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LOAD_REG(s5, k1)
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LOAD_REG(s6, k1)
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LOAD_REG(s7, k1)
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LOAD_REG(s8, k1)
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LOAD_REG(sp, k1)
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LOAD_REG(gp, k1)
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LOAD_REG(ra, k1)
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lw k0, (cp0_epc_IDX * 4)(k1)
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bnez k0, 1f
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nop
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li k0, 0x00000001
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sw k0, (cp0_epc_IDX * 4)(k1)
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LOAD_REG(a0, k1)
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LOAD_REG(a1, k1)
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LOAD_REG(a2, k1)
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LOAD_REG(a3, k1)
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enable_global_interrupts
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1:
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jr ra
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nop
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/**
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* archFirstThreadRestore(ATOM_TCB *new_tcb)
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*
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* This function is responsible for restoring and starting the first
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* thread the OS runs. It expects to find the thread context exactly
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* as it would be if a context save had previously taken place on it.
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* The only real difference between this and the archContextSwitch()
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* routine is that there is no previous thread for which context must
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* be saved.
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*
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* The final action this function must do is to restore interrupts.
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*/
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.globl archFirstThreadRestore
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archFirstThreadRestore:
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move k0, a0 /* save the copy of tcb pointer in k0 */
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lw k1, 0(k0) /* Assume that sp_save_ptr is always at base of ATOM_TCB */
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lw a0, (a0_IDX * 4)(k1)
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lw sp, (sp_IDX * 4)(k1)
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lw s8, (s8_IDX * 4)(k1)
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lw k0, (ra_IDX * 4)(k1)
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mtc0 k0, CP0_EPC
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nop
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nop
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nop
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ehb
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li k0, 0x00000001
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sw k0, (cp0_epc_IDX * 4)(k1)
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nop
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ehb
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enable_global_interrupts
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ehb
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nop
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nop
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eret
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