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129 lines
8.2 KiB
C
129 lines
8.2 KiB
C
/*
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* Copyright (c) 2012, Natie van Rooyen. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. No personal names or organizations' names associated with the
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* Atomthreads project may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE ATOMTHREADS PROJECT AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MODULES_H__
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#define __MODULES_H__
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/*
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* Module definitions to use with the ARM Integrator/CP (ARM926EJ-S)
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*/
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#include "atomport.h"
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typedef volatile unsigned int REG_DWORD ;
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typedef volatile unsigned short REG_WORD ;
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typedef volatile unsigned char REG_BYTE ;
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// *****************************************************************************
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// INTEGRATORCP TIMER
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// *****************************************************************************
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typedef struct ICP_TIMER_S {
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// offset read/write word size reset Description
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REG_DWORD LOAD ; // 0x0000 Read/write 32 0x00000000 Load value for Timer
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REG_DWORD VALUE ; // 0x0004 Read 32 0xFFFFFFFF The current value for Timer
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REG_BYTE CONTROL ; // 0x0008 Read/write 8 0x20 Timer control register
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REG_DWORD INTCLR ; // 0x000C Write - - Timer interrupt clear
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REG_DWORD RIS ; // 0x0010 Read 1 0x0 Timer raw interrupt status
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REG_DWORD MIS ; // 0x0014 Read 1 0x0 Timer masked interrupt status
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REG_DWORD BGLOAD ; // 0x0018 Read/write 32 0x00000000 Background load value for Timer
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} ICP_TIMER_T, *PICP_TIMER_T ;
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// -------- ICP_TIMER_LOAD : (LOAD Offset: 0x00) Load value for Timer --------
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// -------- ICP_TIMER_VALUE : (LOAD Offset: 0x04) The current value for Timer --------
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// -------- ICP_TIMER_CONTROL : (CONTROL Offset: 0x04) Timer control register --------
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#define ICP_TIMER_CONTROL_MASK ((unsigned int)0x0F << 0) // Timer control mask
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#define ICP_TIMER_CONTROL_ENABLE ((unsigned int)0x01 << 7) // Timer enable: 0 = disabled 1 = enabled.
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#define ICP_TIMER_CONTROL_MODE ((unsigned int)0x01 << 6) // Timer mode: 0 = free running, counts once and then wraps to 0xFFFF 1 = periodic, reloads from load register at the end of each count..
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#define ICP_TIMER_CONTROL_IE ((unsigned int)0x01 << 5) // Interrupt enable.
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#define ICP_TIMER_CONTROL_R ((unsigned int)0x01 << 4) // Unused, always write as 0s.
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#define ICP_TIMER_CONTROL_PRESCALE_MASK ((unsigned int)0x03 << 2) // Prescale divisor
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#define ICP_TIMER_CONTROL_PRESCALE_NONE ((unsigned int)0x00 << 2) //
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#define ICP_TIMER_CONTROL_PRESCALE_16 ((unsigned int)0x01 << 2) //
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#define ICP_TIMER_CONTROL_PRESCALE_256 ((unsigned int)0x02 << 2) //
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#define ICP_TIMER_CONTROL_TIMER_SIZE ((unsigned int)0x01 << 1) // Selects 16/32 bit counter operation: 0 = 16-bit counter (default) 1 = 32-bit counter For 16-bit mode, write the high 16 bits of the 32-bit value as 0.
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#define ICP_TIMER_CONTROL_ONE_SHOT ((unsigned int)0x01 << 0) // Selects one-shot or wrapping counter mode: 0 = wrapping mode (default) 1 = one-shot mode
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// -------- ICP_TIMER_INTCLR : (INTCLR Offset: 0x0C) Timer interrupt clear --------
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// -------- ICP_TIMER_RIS : (RIS Offset: 0x10) Timer raw interrupt status --------
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// -------- ICP_TIMER_MIS : (MIS Offset: 0x14) Timer masked interrupt status --------
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#define ICP_TIMER_INT ((unsigned int)0x01 << 0) // Interrupt
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// -------- ICP_TIMER_BGLOAD : (BGLOAD Offset: 0x18) Timer masked interrupt status --------
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// *****************************************************************************
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// INTEGRATORCP PIC
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// *****************************************************************************
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typedef struct ICP_PIC_S {
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// offset read/write word size reset Description
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REG_DWORD IRQ_STATUS ; // 0x0000 Read 22 IRQ gated interrupt status
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REG_DWORD IRQ_RAWSTAT ; // 0x0004 Read 22 IRQ raw interrupt status
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REG_DWORD IRQ_ENABLESET ; // 0x0008 Read/write 22 IRQ enable set
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REG_DWORD IRQ_ENABLECLR ; // 0x000C Write 22 IRQ enable clear
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REG_DWORD INT_SOFTSET ; // 0x0010 Read/write 16 Software interrupt set
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REG_DWORD INT_SOFTCLR ; // 0x0014 Write 16 Software interrupt clear
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REG_DWORD RESERVED[2] ; // 0x0018
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REG_DWORD FIQ_STATUS ; // 0x0020 Read 22 FIQ gated interrupt status
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REG_DWORD FIQ_RAWSTAT ; // 0x0024 Read 22 FIQ raw interrupt status
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REG_DWORD FIQ_ENABLESET ; // 0x0028 Read/write 22 FIQ enable set
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REG_DWORD FIQ_ENABLECLR ; // 0x002C Write-only 22 FIQ enable clear
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} ICP_PIC_T, *PICP_PIC_T ;
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// -------- ICP_PIC_IRQ_STATUS : (IRQ_STATUS Offset: 0x00) IRQ gated interrupt status --------
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// -------- ICP_PIC_IRQ_RAWSTAT : (IRQ_RAWSTAT Offset: 0x04) IRQ raw interrupt status --------
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// -------- ICP_PIC_IRQ_ENABLESET : (IRQ_ENABLESET Offset: 0x08) IRQ enable set --------
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// -------- ICP_PIC_IRQ_ENABLECLR : (IRQ_ENABLECLR Offset: 0x0C) IRQ enable clear --------
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#define ICP_PIC_IRQ_MASK ((unsigned int)0x3FFFFF << 0) // IRQ mask
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#define ICP_PIC_IRQ_TIMERINT2 ((unsigned int)0x01 << 7) // TIMERINT2 Counter-timer 2 interrupt
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#define ICP_PIC_IRQ_TIMERINT1 ((unsigned int)0x01 << 6) // TIMERINT1 Counter-timer 1 interrupt
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#define ICP_PIC_IRQ_TIMERINT0 ((unsigned int)0x01 << 5) // TIMERINT0 Counter-timer 0 interrupt
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#define ICP_PIC_IRQ_SOFTINT ((unsigned int)0x01 << 0) // OFTINT Software interrupt
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// -------- ICP_PIC_INT_SOFTSET : (INT_SOFTSET Offset: 0x10) Software interrupt set --------
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// -------- ICP_PIC_INT_SOFTCLR : (INT_SOFTCLR Offset: 0x14) Software interrupt clear --------
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/* module definitions */
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#define BOARD_BASE_ADDRESS_TIMER_0 0x13000000
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#define BOARD_BASE_ADDRESS_PIC 0x14000000
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extern ICP_TIMER_T* const board_timer_0 ;
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extern ICP_PIC_T* const board_pic ;
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/* Function prototypes */
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extern int low_level_init (void) ;
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extern void dbg_format_msg (char *format, ...) ;
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#define DBG_MESSAGE(fmt_str) { dbg_format_msg fmt_str ; }
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#endif /* __MODULES_H__ */
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