mirror of
https://github.com/drasko/codezero.git
synced 2026-01-12 02:43:15 +01:00
Merge branch 'rebase' of git://www.b-labs.co.uk/~amit/codezero into amit-devel
This commit is contained in:
Bahadir Balban
@@ -58,7 +58,7 @@
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(c)->attr |= CAP_DEVTYPE_MASK & devtype;}
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#define cap_set_devnum(c, devnum) \
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{(c)->attr &= ~CAP_DEVNUM_MASK; \
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(c)->attr |= CAP_DEVNUM_MASK & devnum;}
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(c)->attr |= CAP_DEVNUM_MASK & (devnum << CAP_DEVNUM_SHIFT);}
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#define cap_devnum(c) \
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(((c)->attr & CAP_DEVNUM_MASK) >> CAP_DEVNUM_SHIFT)
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#define cap_devtype(c) ((c)->attr & CAP_DEVTYPE_MASK)
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@@ -1,27 +0,0 @@
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#ifndef __PLATFORM_IRQ_H__
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#define __PLATFORM_IRQ_H__
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#define IRQ_CHIPS_MAX 2
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#define IRQS_MAX 64
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/* IRQ indices. */
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#define IRQ_TIMER01 4
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#define IRQ_TIMER23 5
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#define IRQ_RTC 10
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#define IRQ_UART0 12
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#define IRQ_UART1 13
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#define IRQ_UART2 14
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#define IRQ_SIC 31
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/* Cascading definitions */
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#define PIC_IRQS_MAX 31 /* Total irqs on PIC */
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/* The local irq line of the dummy peripheral on this chip */
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#define LOCALIRQ_DUMMY 15
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/* The irq index offset of this chip, is the maximum of previous chip + 1 */
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#define SIRQ_CHIP_OFFSET (PIC_IRQS_MAX + 1)
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/* The global irq number of dummy is the local irq line + it's chip offset */
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#define IRQ_DUMMY (LOCALIRQ_DUMMY + SIRQ_CHIP_OFFSET)
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#endif /* __PLATFORM_IRQ_H__ */
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@@ -1,60 +0,0 @@
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/*
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* Describes physical memory layout of pb926 platform.
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*
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* Copyright (C) 2007 Bahadir Balban
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*/
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#ifndef __PLATFORM_PB926_OFFSETS_H__
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#define __PLATFORM_PB926_OFFSETS_H__
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/* Physical memory base */
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#define PHYS_MEM_START 0x00000000 /* inclusive */
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#define PHYS_MEM_END 0x08000000 /* 128 MB, exclusive */
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/*
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* These bases taken from where kernel is `physically' linked at,
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* also used to calculate virtual-to-physical translation offset.
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* See the linker script for their sources. PHYS_ADDR_BASE can't
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* use a linker variable because it's referred from assembler.
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*/
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#define PHYS_ADDR_BASE 0x100000
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/* Device memory base */
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#define PB926_DEV_PHYS 0x10000000
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/* Device offsets in physical memory */
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#define PB926_SYSTEM_REGISTERS 0x10000000 /* System registers */
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#define PB926_SYSCTRL_BASE 0x101E0000 /* System controller */
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#define PB926_WATCHDOG_BASE 0x101E1000 /* Watchdog */
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#define PB926_TIMER01_BASE 0x101E2000 /* Timers 0 and 1 */
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#define PB926_TIMER23_BASE 0x101E3000 /* Timers 2 and 3 */
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#define PB926_RTC_BASE 0x101E8000 /* Real Time Clock */
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#define PB926_VIC_BASE 0x10140000 /* Primary Vectored IC */
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#define PB926_SIC_BASE 0x10003000 /* Secondary IC */
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#define PB926_UART0_BASE 0x101F1000 /* Console port (UART0) */
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/*
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* Uart virtual address until a file-based console access
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* is available for userspace
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*/
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#define USERSPACE_UART_BASE 0x500000
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/*
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* Device offsets in virtual memory. They offset to some virtual
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* device base address. Each page on this virtual base is consecutively
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* allocated to devices. Nice and smooth.
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*/
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#define PB926_TIMER01_VOFFSET 0x00000000
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#define PB926_UART0_VOFFSET 0x00001000
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#define PB926_VIC_VOFFSET 0x00002000
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#define PB926_SIC_VOFFSET 0x00003000
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#define PB926_SYSREGS_VOFFSET 0x00005000
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#define PB926_SYSCTRL_VOFFSET 0x00006000
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#define PB926_UART0_VBASE (IO_AREA0_VADDR + PB926_UART0_VOFFSET)
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#define PB926_TIMER01_VBASE (IO_AREA0_VADDR + PB926_TIMER01_VOFFSET)
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#define PB926_SYSCTRL_VBASE (IO_AREA0_VADDR + PB926_SYSCTRL_VOFFSET)
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#define PB926_VIC_VBASE (IO_AREA0_VADDR + PB926_VIC_VOFFSET)
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#define PB926_SIC_VBASE (IO_AREA0_VADDR + PB926_SIC_VOFFSET)
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#endif /* __PLATFORM_PB926_OFFSETS_H__ */
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@@ -1,22 +0,0 @@
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#ifndef __PLATFORM_PB926_PLATFORM_H__
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#define __PLATFORM_PB926_PLATFORM_H__
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/*
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* Platform specific ties between drivers and generic APIs used by the kernel.
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* E.g. system timer and console.
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*
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* Copyright (C) Bahadir Balban 2007
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*/
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#include INC_PLAT(offsets.h)
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#include INC_GLUE(memlayout.h)
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#define PLATFORM_CONSOLE_BASE PB926_UART0_VBASE
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#define PLATFORM_TIMER_BASE PB926_TIMER01_VBASE
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#define PLATFORM_SP810_BASE PB926_SYSCTRL_VBASE
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#define PLATFORM_IRQCTRL_BASE PB926_VIC_VBASE
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#define PLATFORM_SIRQCTRL_BASE PB926_SIC_VBASE
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void platform_irq_enable(int irq);
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void platform_irq_disable(int irq);
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void timer_start(void);
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#endif /* __PLATFORM_PB926_PLATFORM_H__ */
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@@ -1,15 +0,0 @@
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#ifndef __PLATFORM__PB926__PRINTASCII__H__
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#define __PLATFORM__PB926__PRINTASCII__H__
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#define dprintk(str, val) \
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{ \
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printascii(str); \
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printascii("0x"); \
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printhex8((val)); \
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printascii("\n"); \
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}
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void printascii(char *str);
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void printhex8(unsigned int);
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#endif /* __PLATFORM__PB926__PRINTASCII__H__ */
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@@ -1,20 +0,0 @@
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/*
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* Platform specific ties to generic uart functions that putc expects.
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*
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* Copyright (C) 2007 Bahadir Balban
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*
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*/
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#ifndef __PLATFORM_PB926_UART_H__
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#define __PLATFORM_PB926_UART_H__
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#include INC_PLAT(offsets.h)
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#include INC_GLUE(memlayout.h)
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#define PLATFORM_CONSOLE_BASE PB926_UART0_VBASE
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#include <l4/drivers/uart/pl011/pl011_uart.h>
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void uart_init(void);
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void uart_putc(char c);
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#endif /* __PLATFORM_PB926_UART_H__ */
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@@ -13,14 +13,14 @@
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#include <l4/generic/cap-types.h>
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#include <l4/generic/resource.h>
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#define PLATFORM_CONSOLE0_BASE PB926_UART0_VBASE
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#define PLATFORM_CONSOLE0_BASE PB926_UART0_VBASE
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/* SP804 timer has TIMER1 at TIMER0 + 0x20 address */
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#define PLATFORM_TIMER0_BASE PB926_TIMER01_VBASE
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#define PLATFORM_TIMER0_BASE PB926_TIMER01_VBASE
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#define PLATFORM_SP810_BASE PB926_SYSCTRL_VBASE
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#define PLATFORM_IRQCTRL_BASE PB926_VIC_VBASE
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#define PLATFORM_SIRQCTRL_BASE PB926_SIC_VBASE
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#define PLATFORM_IRQCTRL_BASE PB926_VIC_VBASE
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#define PLATFORM_SIRQCTRL_BASE PB926_SIC_VBASE
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/* Total number of timers present in this platform */
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#define TOTAL_TIMERS 4
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@@ -30,6 +30,16 @@
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#define PLATFORM_TIMER2 2
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#define PLATFORM_TIMER3 3
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/* Wrapping Plaform specific Physical Device Addresses */
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#define PLATFORM_CONSOLE0_PHY_BASE PB926_UART0_BASE
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#define PLATFORM_CONSOLE1_PHY_BASE PB926_UART1_BASE
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#define PLATFORM_CONSOLE2_PHY_BASE PB926_UART2_BASE
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#define PLATFORM_CONSOLE3_PHY_BASE PB926_UART3_BASE
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#define PLATFORM_TIMER0_PHY_BASE PB926_TIMER01_BASE
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#define PLATFORM_TIMER1_PHY_BASE PB926_TIMER23_BASE
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int platform_setup_device_caps(struct kernel_resources *kres);
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void platform_irq_enable(int irq);
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void platform_irq_disable(int irq);
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@@ -1,25 +0,0 @@
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#ifndef __PLATFORM_IRQ_H__
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#define __PLATFORM_IRQ_H__
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/* TODO: Not sure about this, need to check */
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#define IRQ_CHIPS_MAX 4
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#define IRQS_MAX 96
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/*
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* IRQ indices, 32-63 and 72-89 index
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* available for external sources
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* 0-32: used for SI, provided by
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* distributed interrupt controller
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*/
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#define IRQ_TIMER01 36
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#define IRQ_TIMER23 37
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#define IRQ_TIMER45 73
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#define IRQ_TIMER67 74
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#define IRQ_RTC 42
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#define IRQ_UART0 44
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#define IRQ_UART1 45
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#define IRQ_UART2 46
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#define IRQ_UART3 47
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#endif /* __PLATFORM_IRQ_H__ */
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@@ -1,77 +0,0 @@
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/*
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* Describes physical memory layout of pb926 platform.
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*
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* Copyright (C) 2007 Bahadir Balban
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*/
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#ifndef __PLATFORM_PBA8_OFFSETS_H__
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#define __PLATFORM_PBA8_OFFSETS_H__
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/* Physical memory base */
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#define PHYS_MEM_START 0x00000000 /* inclusive */
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#define PHYS_MEM_END 0x10000000 /* 256 MB, exclusive */
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/*
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* These bases taken from where kernel is `physically' linked at,
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* also used to calculate virtual-to-physical translation offset.
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* See the linker script for their sources. PHYS_ADDR_BASE can't
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* use a linker variable because it's referred from assembler.
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*/
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#define PHYS_ADDR_BASE 0x100000
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/* Device memory base */
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#define PBA8_DEV_PHYS 0x10000000
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/* Device offsets in physical memory */
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#define PBA8_SYSTEM_REGISTERS 0x10000000 /* System registers */
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#define PBA8_SYSCTRL0_BASE 0x10001000 /* System controller 0 */
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#define PBA8_UART0_BASE 0x10009000 /* UART 0 */
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#define PBA8_UART1_BASE 0x1000A000 /* UART 1 */
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#define PBA8_UART2_BASE 0x1000B000 /* UART 2 */
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#define PBA8_UART3_BASE 0x1000C000 /* UART 3 */
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#define PBA8_WATCHDOG0_BASE 0x1000F000 /* WATCHDOG 0 */
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#define PBA8_WATCHDOG1_BASE 0x10010000 /* WATCHDOG 1 */
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#define PBA8_TIMER01_BASE 0x10011000 /* TIMER 0-1 */
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#define PBA8_TIMER23_BASE 0x10012000 /* TIMER 2-3 */
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#define PBA8_RTC_BASE 0x10017000 /* RTC interface */
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#define PBA8_TIMER45_BASE 0x10018000 /* TIMER 4-5 */
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#define PBA8_TIMER67_BASE 0x10019000 /* TIMER 6-7 */
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#define PBA8_SYSCTRL1_BASE 0x1001A000 /* System controller 1 */
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#define PBA8_GIC0_BASE 0x1E000000 /* GIC 0 */
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#define PBA8_GIC1_BASE 0x1E010000 /* GIC 1 */
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#define PBA8_GIC2_BASE 0x1E020000 /* GIC 2 */
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#define PBA8_GIC3_BASE 0x1E030000 /* GIC 3 */
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/*
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* Uart virtual address until a file-based console access
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* is available for userspace
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*/
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#define USERSPACE_UART_BASE 0x500000
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/*
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* Device offsets in virtual memory. They offset to some virtual
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* device base address. Each page on this virtual base is consecutively
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* allocated to devices. Nice and smooth.
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*/
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#define PBA8_SYSREGS_VOFFSET 0x00000000
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#define PBA8_SYSCTRL0_VOFFSET 0x00001000
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#define PBA8_SYSCTRL1_VOFFSET 0x00002000
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#define PBA8_UART0_VOFFSET 0x00003000
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#define PBA8_TIMER01_VOFFSET 0x00004000
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#define PBA8_GIC0_VOFFSET 0x00005000
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#define PBA8_GIC1_VOFFSET 0x00006000
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#define PBA8_GIC2_VOFFSET 0x00007000
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#define PBA8_GIC3_VOFFSET 0x00008000
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#define PBA8_SYSREGS_VBASE (IO_AREA0_VADDR + PBA8_SYSREGS_VOFFSET)
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#define PBA8_SYSCTRL0_VBASE (IO_AREA0_VADDR + PBA8_SYSCTRL0_VOFFSET)
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#define PBA8_SYSCTRL1_VBASE (IO_AREA0_VADDR + PBA8_SYSCTRL1_VOFFSET)
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#define PBA8_UART0_VBASE (IO_AREA0_VADDR + PBA8_UART0_VOFFSET)
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#define PBA8_TIMER01_VBASE (IO_AREA0_VADDR + PBA8_TIMER01_VOFFSET)
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#define PBA8_GIC0_VBASE (IO_AREA0_VADDR + PBA8_GIC0_VOFFSET)
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#define PBA8_GIC1_VBASE (IO_AREA0_VADDR + PBA8_GIC1_VOFFSET)
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#define PBA8_GIC2_VBASE (IO_AREA0_VADDR + PBA8_GIC2_VOFFSET)
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#define PBA8_GIC3_VBASE (IO_AREA0_VADDR + PBA8_GIC3_VOFFSET)
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#endif /* __PLATFORM_PBA8_OFFSETS_H__ */
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@@ -1,32 +0,0 @@
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#ifndef __PBA8_PLATFORM_H__
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#define __PBA8_PLATFORM_H__
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/*
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* Platform specific ties between drivers and generic APIs used by the kernel.
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* E.g. system timer and console.
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*
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* Copyright (C) Bahadir Balban 2007
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*/
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#include INC_PLAT(offsets.h)
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#include INC_GLUE(memlayout.h)
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#define PLATFORM_CONSOLE0_BASE PBA8_UART0_VBASE
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#define PLATFORM_TIMER0_BASE PBA8_TIMER01_VBASE
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#define PLATFORM_SP810_BASE PBA8_SYSCTRL0_VBASE
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/* Total number of timers present in this platform */
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#define TOTAL_TIMERS 8
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#define PLATFORM_TIMER0 0
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#define PLATFORM_TIMER1 1
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#define PLATFORM_TIMER2 2
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#define PLATFORM_TIMER3 3
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#define PLATFORM_TIMER4 4
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#define PLATFORM_TIMER5 5
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#define PLATFORM_TIMER6 6
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#define PLATFORM_TIMER7 7
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void platform_irq_enable(int irq);
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void platform_irq_disable(int irq);
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void timer_start(void);
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#endif /* __PBA8_PLATFORM_H__ */
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@@ -1,15 +0,0 @@
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#ifndef __PLATFORM__PBA8__PRINTASCII__H__
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#define __PLATFORM__PBA8__PRINTASCII__H__
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#define dprintk(str, val) \
|
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{ \
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printascii(str); \
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printascii("0x"); \
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printhex8((val)); \
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printascii("\n"); \
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}
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void printascii(char *str);
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void printhex8(unsigned int);
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#endif /* __PLATFORM__PBA8__PRINTASCII__H__ */
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@@ -1,20 +0,0 @@
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/*
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||||
* Platform specific ties to generic uart functions that putc expects.
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||||
*
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||||
* Copyright (C) 2007 Bahadir Balban
|
||||
*
|
||||
*/
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#ifndef __PLATFORM_PBA8_UART_H__
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#define __PLATFORM_PBA8_UART_H__
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#include INC_PLAT(offsets.h)
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#include INC_GLUE(memlayout.h)
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#define PLATFORM_CONSOLE_BASE PBA8_UART0_VBASE
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#include <l4/drivers/uart/pl011/pl011_uart.h>
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void uart_init(void);
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||||
void uart_putc(char c);
|
||||
|
||||
#endif /* __PLATFORM_PB926_UART_H__ */
|
||||
Reference in New Issue
Block a user